Alyssa Rosenzweig [Fri, 16 Apr 2021 02:51:47 +0000 (22:51 -0400)]
agx: Implement fsin/fcos
First, we lower to fsin_agx and some ALU in NIR. Then, we implement
fsin_agx with the underlying transcental ops.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Wed, 14 Apr 2021 19:28:13 +0000 (15:28 -0400)]
agx: Implement simple floating point ops
These are all direct translations of NIR->AIR.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Mon, 12 Apr 2021 03:45:35 +0000 (23:45 -0400)]
agx: Implement ld_vary
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Mon, 12 Apr 2021 03:00:35 +0000 (23:00 -0400)]
agx: Terminate programs with stop and traps
The function of stop is clear. The function of trap, let alone a whole
sled of them, is less so. Maybe a debugging feature for later.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 17 Apr 2021 22:11:05 +0000 (18:11 -0400)]
agx: Add st_vary(_final) instruction packing
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sat, 17 Apr 2021 21:01:20 +0000 (17:01 -0400)]
agx: Add packing for memory loads/stores
Encoding is dramatically different from ALU.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Mon, 12 Apr 2021 03:49:30 +0000 (23:49 -0400)]
agx: Add instruction packing
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 20:01:47 +0000 (16:01 -0400)]
agx: Add a trivial register allocator
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 19:29:08 +0000 (15:29 -0400)]
agx: Add instruction printing
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 19:19:49 +0000 (15:19 -0400)]
agx: Implement fragment_out
For a single colour render target.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 19:10:39 +0000 (15:10 -0400)]
agx: Implement vec2/vec3/vec4 ops
As p_combine, to un-stub emit_alu.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 19:09:36 +0000 (15:09 -0400)]
agx: Add agx_alu_src_index helper for emit_alu
Since we don't use abs/neg in NIR, this just needs to construct
p_extract ops to deal with swizzles.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 19:09:03 +0000 (15:09 -0400)]
agx: Implement direct st_vary
Indirection can come later, if at all..
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 19:08:44 +0000 (15:08 -0400)]
agx: Implement load_const as mov
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 15:26:00 +0000 (11:26 -0400)]
agx: Stub emit_intrinsic
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 15:05:52 +0000 (11:05 -0400)]
agx: Stub NIR instruction iteration
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 14:57:55 +0000 (10:57 -0400)]
agx: Stub control flow walking
From Bifrost. We'll need to diverge (no pun intended) due to exec_mask
handling specific to Apple.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 2 May 2021 13:44:15 +0000 (09:44 -0400)]
agx: Remap varyings to match AGX ABI
It's not clear if this is software or hardware defined, but until we
know more about linkage, let's match the blob. Fixes dEQP issues with
gl_PointSize.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 02:03:19 +0000 (22:03 -0400)]
agx: Stub NIR backend compiler
A fork of the Bifrost compiler, tailored to AGX. nir_register support is
removed, as I want to use an SSA-based allocator for AGX. (There are no
VLIW-like requirements and extremely limited vector semantics, so we can
use an ACO approach with ease.)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Thu, 15 Apr 2021 23:08:26 +0000 (19:08 -0400)]
agx: Generate builder routines
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Thu, 15 Apr 2021 23:08:00 +0000 (19:08 -0400)]
agx: Generate runtime-accessible opcode table
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Thu, 15 Apr 2021 23:08:13 +0000 (19:08 -0400)]
agx: Generate opcode list
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Wed, 14 Apr 2021 20:50:23 +0000 (16:50 -0400)]
agx: Add opcode descriptions as Python
Pattern lifted from NIR.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 11 Apr 2021 00:17:21 +0000 (20:17 -0400)]
asahi: Stub command-line compiler for AGX G13B
Based on the Bifrost standalone compiler, which was based on Midgard's
standalone compiler, which was based on Freedreno's standalone compiler,
which was.....
It's like sour dough!
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Fri, 16 Apr 2021 02:46:45 +0000 (22:46 -0400)]
nir: Add fsin_agx opcode
Used to split up the fsin/fcos lowering for AGX between NIR and the
backend, to permit algebraic optimizations without polluting NIR with
too many hardware details. The backend NIR lowering produces an
fmul/ffma of the input so we can optimize code like sin(2*x).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
Alyssa Rosenzweig [Sun, 2 May 2021 17:16:17 +0000 (13:16 -0400)]
util/bitset: Add BITSET_COUNT helper
Expressible as a prefix sum but that's a bit unnatural, so add a
convenience helper.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mike Blumenkrants <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10581>
Lionel Landwerlin [Mon, 19 Oct 2020 07:12:43 +0000 (10:12 +0300)]
anv: implement VK_KHR_fragment_shading_rate
Available on Gen11+.
v2: Order shading rate in correct order (Samuel)
v3: Move CPS_STATE emission to genX_state.c
v4: Don't override various output structures (Jason)
v5: Rebase on top master (Lionel)
v6: Fix invalid VkPhysicalDeviceFragmentShadingRatePropertiesKHR
(min|max)FragmentShadingRateAttachmentTexelSize values (Ken)
Drop #endif comment
v7: Limit extension to Gfx11+ (Lionel)
Support conservative raster (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Jason Ekstrand [Fri, 5 Feb 2021 14:11:01 +0000 (08:11 -0600)]
intel/fs: Stop using brw_dp_read/write_desc in Gen7+ only code
Those helpers exist primarily to sort out some of the weirdness around
Gen4-6 dataport access. On Gen5 and earlier, everything was called
"dataport" and, instead of the SFID we have today there was a "target
cache" parameter in the descriptor. There are also some bits that moved
around on various gens depending on read vs. write. Starting with Gen6,
most things which target one of the data cache SFIDs should use
brw_dp_desc() instead.
v2: Drop backward comment (Ken)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Jason Ekstrand [Fri, 5 Feb 2021 14:09:47 +0000 (08:09 -0600)]
intel/eu: SVB writes only happen on Gen6
It's a Gen6 XFB thing. It's never used for anything else so there's no
point in having a target cache switch.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Thu, 29 Oct 2020 13:17:16 +0000 (15:17 +0200)]
intel/compiler: add restrictions related to coarse pixel shading
v2: Update to BITSET_TEST()
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Tue, 9 Feb 2021 11:20:17 +0000 (13:20 +0200)]
intel/compiler: add coarse pixel offset on Gfx12.5+
Gfx12.5 has a slightly different code path.
v2: Document the oddness
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Thu, 29 Oct 2020 13:10:59 +0000 (15:10 +0200)]
intel/compiler: add support for fragment coordinate with coarse pixels
v2: Drop new internal opcodes (Jason)
Simplify code (Jason)
v3: Add Z computation for coarse pixels
v4: Document things a little
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Thu, 29 Oct 2020 13:19:30 +0000 (15:19 +0200)]
intel/compiler: add support for fragment shading rate variable
v2: Drop old register type initializers (Jason)
Simplify instruction snippet (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Thu, 22 Oct 2020 10:23:06 +0000 (13:23 +0300)]
intel/compiler: handle coarse pixel in render target writes descriptors
v2: Use the new inst->ex_desc field (Jason)
v3: Drop CPS LoD compensation from sampler messages (Lionel)
v4: Drop useless uses_rate_shading (Ken)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Thu, 22 Oct 2020 10:25:33 +0000 (13:25 +0300)]
intel/compiler: use existing helpers to pull bits of descriptors
v2: Use new RT descriptor helper
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Thu, 4 Feb 2021 09:49:29 +0000 (11:49 +0200)]
intel/compiler: rework message descriptors for render targets
Render target message descriptors are slightly different from the
dataport ones. In particular the msg_type field is on bits 14:17 for
RT while bits 14:18 for DP.
v2: Drop unused send_commit_msg field in brw_fb_write_desc() (Ken)
v3: Rebase on top renaming (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Fri, 30 Oct 2020 15:41:02 +0000 (17:41 +0200)]
intel/compiler: make sure we keep the lowest dispatch limit
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Wed, 21 Oct 2020 12:26:06 +0000 (15:26 +0300)]
intel/decoder: decode CPS_STATE
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Fri, 16 Oct 2020 13:11:53 +0000 (16:11 +0300)]
intel/genxml: Add coarse pixel shading instructions
v2: Add Gen12.5
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Lionel Landwerlin [Wed, 21 Oct 2020 08:40:49 +0000 (11:40 +0300)]
intel/dev: printout correct subslice/dualsubslice name
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
Rob Clark [Sat, 1 May 2021 18:32:10 +0000 (11:32 -0700)]
freedreno: Fix TC last_fence optimization
Grabbing the fence value in fd_fence_repopulate() without waiting on
fd_submit_fence::ready doesn't work with async flushes, since we are
waiting for the first flush to complete (ie. we don't have the kernel-
side fence value yet). Just simplify it and make the "repopulated"
fence delagate to the original fence.
Fixes:
e9a9ac6f77f ("freedreno/drm: Async submit support")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4726
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10567>
Rob Clark [Sat, 1 May 2021 17:57:40 +0000 (10:57 -0700)]
freedreno/drm: Initialize control->fence
Don't rely on getting a zero'd out buffer, we could hit the bo-cache.
Fixes:
7dabd624649 ("freedreno/drm: Userspace fences")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10567>
Vasily Khoruzhick [Sun, 2 May 2021 05:45:30 +0000 (22:45 -0700)]
lima: switch resource to linear layout if there's to many full updates
Overwriting entire resource multiple times indicates streaming and in this
case it's more efficient to use linear layout to avoid expensive linear->tiled
conversions.
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10572>
Vinson Lee [Sat, 1 May 2021 20:08:51 +0000 (13:08 -0700)]
glx: Fix macOS build.
In file included from ../src/glx/apple/apple_glx_context.c:49:
../src/glx/glxclient.h:56:10: fatal error: 'loader.h' file not found
^~~~~~~~~~
Fixes:
1cb664c15cb3 ("glx: s/dri_message/glx_message/")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4702
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10568>
Bastian Beranek [Sat, 1 May 2021 07:52:01 +0000 (09:52 +0200)]
glx: Assign unique serial number to GLXBadFBConfig error
Since commit
f39fd3dce72 a new GLX error is issued in case context creation
fails. This broke wine on certain hardware: While wine installs an error handler
to ignore this kind of error, it does not function because it expects the
dpy->request serial number of the error to be incremented since the installation
of the handler.
Workaround this by artificially increasing the request number. This also
guarantees a unique serial number for the error.
Fixes:
f39fd3dce72eaef59ab39a23b75030ef9efc2a40
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3969
Signed-off-by: Bastian Beranek <bastian.beischer@rwth-aachen.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10565>
Ilia Mirkin [Thu, 25 Mar 2021 01:16:35 +0000 (21:16 -0400)]
nv50: add indirect compute support
There's no hardware support for anything indirect, so just read the
parameters out.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Sun, 21 Mar 2021 03:40:00 +0000 (23:40 -0400)]
nv50: add support for doing membars
This requires an address that's safe to read from.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Sat, 20 Mar 2021 00:10:24 +0000 (20:10 -0400)]
nv50: add remapping of buffers/images into unified space
This allows us to use up to 15 images or buffers (but not both). GL
supports the concept of combined resource maximums though.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Tue, 2 Mar 2021 05:18:07 +0000 (00:18 -0500)]
nv50: add compute invocations counter
This is a purely software counter alongside the other hardware counters
for ease of use and consistency. However we have to make room for it in
the allocated query space. Use this opportunity to make the nv50 queries
work like the nvc0 ones in terms of space allocation.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Tue, 2 Mar 2021 00:19:23 +0000 (19:19 -0500)]
nv50/ir: add lowering for shared atomics
This is best-effort for pre-nva0 ... works with a single invocation,
i.e. no locking.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Thu, 25 Feb 2021 03:23:48 +0000 (22:23 -0500)]
nv50/ir: add surface op lowering
This handles BUFQ, SUQ, as well as all the various texture types and
formats, driven by data supplied by the driver (and shader itself).
TODO:
- 2d linear surfaces
- format via key for writeonly
These will be included in a later change. ES3.1 doesn't require
writeonly, and it's very hard to generate a 2d linear surface.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Tue, 2 Mar 2021 23:54:37 +0000 (18:54 -0500)]
nv50: pass surface/buffer parameters to shader via aux buffer
These are needed to implement things like imageSize() as well as feed
data into lowering logic for various access types not handled by the
hardware.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Wed, 10 Mar 2021 04:59:31 +0000 (23:59 -0500)]
nv50/ir: optimize shift of 0 bits
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Wed, 3 Mar 2021 23:52:13 +0000 (18:52 -0500)]
nv50/ir: wipe any info about memory when seeing a locking op
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Thu, 25 Feb 2021 03:23:08 +0000 (22:23 -0500)]
nv50/ir: mark ATOM as having 3 arguments
Otherwise the final argument doesn't get emitted for CAS in the nv50
emitter.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Thu, 25 Feb 2021 03:17:40 +0000 (22:17 -0500)]
nv50/ir: "zero" register does not work with g[] memory
Evidence suggests that having it anywhere, even as a regular e.g. atom
argument, causes issues.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Mon, 12 Apr 2021 22:15:04 +0000 (18:15 -0400)]
nv50/ir: refine limitation on load/store loading offsets, include atomics
Note that shared memory loads can actually do offsets. The restrictions
vary by generation, this will be added in a later change.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Ilia Mirkin [Sun, 11 Apr 2021 21:54:32 +0000 (17:54 -0400)]
nv50/ir: offset accesses to shared memory
Ideally this should include the size of the inputs as well. This will be
updated when we add support for kernels which take actual inputs.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
Marek Olšák [Thu, 22 Apr 2021 04:11:18 +0000 (00:11 -0400)]
gallium+(u_threaded,r300,r600,radeonsi): move transfer offset into pipe_transfer
Let's use the 4 bytes of unused padding usefully in pipe_transfer.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10527>
Marek Olšák [Thu, 22 Apr 2021 03:40:51 +0000 (23:40 -0400)]
gallium: remove 4 bytes from pipe_transfer
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10527>
Marek Olšák [Thu, 22 Apr 2021 03:40:26 +0000 (23:40 -0400)]
gallium: renumber PIPE_MAP_* enums to remove holes
We could change the type into 16 bits if needed.
PB_USAGE flags need to match PIPE_MAP flags due to static assertions.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10527>
Rob Clark [Sat, 1 May 2021 15:44:25 +0000 (08:44 -0700)]
freedreno/ci: Update piglit skips/fails
Add spec@arb_pixel_buffer_object@texsubimage cube_map_array pbo to a530
fails for the same reason as spec@arb_texture_cube_map_array@texsubimage cube_map_array
(it is sometimes triggering gpu hangs that cause other flakes).
And remove two a630 xfails that started showing up as UnexpectedPass.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
Rob Clark [Sat, 1 May 2021 15:25:34 +0000 (08:25 -0700)]
freedreno/ci: Mark client_wait_sync_finish as flake
This one has shown up a couple times since fd/go-fast, I'm still trying
to reproduce/debug.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
Rob Clark [Thu, 29 Apr 2021 18:10:46 +0000 (11:10 -0700)]
freedreno: Flush resources harder
pctx->flush_resource() has the same expectations that the resource can
be shared with an external client as pctx->flush(), but without the
convenience of a fence to know *when* the resource must be visible to
that external client. So we need to ensure the batch is flushed all the
way to the kernel so that implicit-sync can do it's job.
Fixes:
e9a9ac6f77f ("freedreno/drm: Async submit support")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
Rob Clark [Thu, 29 Apr 2021 18:31:25 +0000 (11:31 -0700)]
freedreno/drm: Allow FD_BO_PREP_FLUSH without _NOSYNC
This provides the upper layer (gallium, etc) a way to ensure that
rendering involving the bo has been flushed all the way to the kernel.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
Rob Clark [Thu, 29 Apr 2021 16:02:09 +0000 (09:02 -0700)]
freedreno: Remove samples-per-tex tracking
Looks like this was unused, and only served to segfault when unbinding
textures.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10530>
Rob Clark [Fri, 30 Apr 2021 19:48:42 +0000 (12:48 -0700)]
freedreno/ci: Isolate dEQP-EGL reset_context tests
To reduce flakes, separate out the dEQP-EGL tests that are intentionally
triggering GPU hangs. This avoids some kernel side issues with bad
handling of ringbuffer-full scenarios, causing innocent tests to flake.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10560>
Rob Clark [Fri, 30 Apr 2021 19:41:03 +0000 (12:41 -0700)]
ci: Add DEQP_CASELIST_INV_FILTER
Inverts the match compared to DEQP_CASELIST_FILTER
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10560>
Eric Anholt [Fri, 30 Apr 2021 17:19:29 +0000 (10:19 -0700)]
ci/freedreno: Mark another recent piglit flake.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10552>
Eric Anholt [Fri, 30 Apr 2021 17:18:03 +0000 (10:18 -0700)]
ci/freedreno: Mark new flakes from the go-fast branch.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10552>
Eric Anholt [Fri, 30 Apr 2021 17:12:56 +0000 (10:12 -0700)]
ci/freedreno: Mark dEQP-EGL flakes reported on IRC since its introduction.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10552>
Icecream95 [Fri, 30 Apr 2021 10:18:09 +0000 (22:18 +1200)]
panfrost: Fix viewport scissor for preload draws
The max values are inclusive, so add 1 before aligning. This means
that a max of 32 will be aligned up to 64 then be decremented to 63.
Add a comment to the pan_fb_info struct to document maxx and maxy as
inclusive.
Fixes:
8ba2f9f6985 ("panfrost: Create a blitter library to replace the existing preload helpers")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10542>
Icecream95 [Fri, 30 Apr 2021 10:16:12 +0000 (22:16 +1200)]
panfrost: Remove incorrect comment
The comment was wrong in its original location and is wrong here, just
remove it.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10542>
Dylan Baker [Wed, 28 Apr 2021 23:14:58 +0000 (16:14 -0700)]
meson/vulkan: fix linkage on windows
The current approach likley breaks icl and clang-cl, but it seems that
the problem isn't even really related to MSVC, but to Meson's Visual
Studio backend, as such, let's use link-whole unless we're using a
Visual Studio backend.
Fixes:
48d31a6280c4de07279435606a5c0524c1787cad
("meson: link vulkan_util with link_whole on mingw")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: James Park <jpark37@lagfreegames.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10506>
Gustavo Padovan [Fri, 23 Apr 2021 11:20:42 +0000 (08:20 -0300)]
gitlab-ci: enable all 3 intel devices as manual in MR pipelines
This uses the rule created by .test-manual-mr that enables experimental
devices in MR pipelines, but not for Marge.
The goal is to expose the devices to more possibility of testing before
we enable them automatically.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10405>
Gustavo Padovan [Thu, 22 Apr 2021 11:17:40 +0000 (08:17 -0300)]
gitlab-ci: rule anchor for experimental devices as manual in MRs
We want to give developers the option to run their jobs on devices
that are still being stabilized in the CI infrastructure.
These jobs should be optional and not prevent merging from happening.
The is-forked-branch-or-pre-merge anchor was not being used anywhere,
so it was changed to is-forked-branch-or-pre-merge-not-for-marge to
create this new rule.
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10405>
Jason Ekstrand [Fri, 30 Apr 2021 03:47:35 +0000 (22:47 -0500)]
intel/isl: Fix isl_color_value_unpack to match the prototype
The prototype uses a pointer and the actual function definition had an
array. For some reason, GCC never complained about this until GCC 11.
This fixes a compile warning when building with GCC 11.
Fixes:
09ced6542049 "intel/isl: Add format conversion code"
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10537>
Danylo Piliaiev [Tue, 27 Apr 2021 11:51:26 +0000 (14:51 +0300)]
ir3: do not move varying inputs that depend on unmovable instrs
Not all varying fetches could be pulled into the start block.
If there are fetches we couldn't pull, like load_interpolated_input
with offset which depends on a non-reorderable ssbo load or on a
phi node, this pass is skipped since it would be hard to find a place
to set (ei) flag (beside at the very end).
We also don't have to manually set (ei) in such cases since a5xx and
a6xx do automatically release varying storage at the end.
Earlier gens need further testing, however they do not support
interpolateAt* functions at moment, so unless we would like to support
sample shading on them - they are fine.
Fixes crash in GTA V.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10483>
Martin Peres [Thu, 29 Apr 2021 14:42:47 +0000 (17:42 +0300)]
ci: add the dEQP expectations for radv on Renoir
This patch should not be backported directly to 21.1, as master already
fixed one failure. I'll post a backport of this series with the
additional failure documented when this one gets merged.
v2:
- remove dEQP-VK.synchronization.* from the skip list (Hakzsam)
- drop dEQP-VK.memory.pipeline_barrier.* from the skip list (Hakzsam, me)
v3:
- re-introduce dEQP-VK.memory.pipeline_barrier.transfer_src_transfer_dst.1048576
Signed-off-by: Martin Peres <martin.peres@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10539>
Erik Faye-Lund [Fri, 30 Apr 2021 08:03:49 +0000 (10:03 +0200)]
zink: also enable float16 from KHR extension
This allows us to use 16 bit floats on pre Vulkan 1.2 drivers as well.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
Erik Faye-Lund [Fri, 30 Apr 2021 08:00:50 +0000 (10:00 +0200)]
zink/codegen: prefer first definition of prop/feature structs
Some extensions have renamed their property and/or feature structs,
listing the "correct" type first. So we should prefer that one rather
than overwriting it with a later one.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
Erik Faye-Lund [Wed, 7 Apr 2021 14:50:22 +0000 (16:50 +0200)]
zink: enable 16-bit float support
This finally enables the 16-bit float feature.
Ideally we would also check VK_KHR_shader_float16_int8, but the python
code for that is giving me some issues now, so let's deal with that
later.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
Erik Faye-Lund [Thu, 8 Apr 2021 08:31:15 +0000 (10:31 +0200)]
zink: perform fp16 texture-lookups as fp32 and then convert
SPIR-V doesn't seem to have any opcodes to sample textures using lower
precision directly, so let's sample and downcast later instead.
Ideally, we'd do this as a NIR-pass first, but this does the trick for
now.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
Erik Faye-Lund [Wed, 7 Apr 2021 14:50:22 +0000 (16:50 +0200)]
zink: support emitting 16-bit float types
This prepares us for being able to support using 16-bit float types
in shaders, which might help performance in some cases.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
Erik Faye-Lund [Tue, 6 Apr 2021 16:52:19 +0000 (18:52 +0200)]
zink: enable 16-bit int support
The mysterious support_16bit_int_alu-option doesn't really mean what it
says. Instead it means "we support 16 bit compares, if 16 bit ALU
operations occur". And since 16 bit operations only appear if we're
lowering mediump/lowp, we can always set this option.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
Erik Faye-Lund [Tue, 6 Apr 2021 16:51:06 +0000 (18:51 +0200)]
zink: support emitting 16-bit int types
This prepares us for being able to support using 16-bit int types in
shaders, which might help performance in some cases.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
Erik Faye-Lund [Wed, 7 Apr 2021 17:26:33 +0000 (19:26 +0200)]
zink: always lower function-temp derefs
We're about to need this in order to support 16-bit floats, because the
lowering code for that emits function-temp derefs, and we don't handle
it.
A better long-term solution would be to just support function-temp
variables and indirect derefs. But that's more work, and kinda
orthogonal to what this patchset tries to accomplish, so let's save that
for another day.
Fixes the following piglit:
- spec@arb_gl_spirv@execution@ubo@array-inside-ubo-copy
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
Erik Faye-Lund [Tue, 6 Apr 2021 15:27:13 +0000 (17:27 +0200)]
zink: run nir_opt_algebraic_late
This pass is needed to finish off the [ui]2imp lowering. Follow what
other drivers do and perform some dead-code elimimation etc when
lowering happens.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
Erik Faye-Lund [Wed, 7 Apr 2021 12:09:54 +0000 (14:09 +0200)]
zink: respect bit-size of dref-result
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
Erik Faye-Lund [Thu, 8 Apr 2021 08:23:08 +0000 (10:23 +0200)]
zink: use UINT32_MAX instead of UINT_MAX
This is a 32-bit argument, so on platforms where UINT_MAX is larger,
this is going to... well, do exactly the same thing, but this is
slightly clearer why.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10101>
Icecream95 [Wed, 28 Apr 2021 23:27:28 +0000 (11:27 +1200)]
pan/mdg: Fix calculation of available work registers
Make the rmu variable signed; otherwise the MAX2 has no effect and
work_count can end up being larger than 16.
Fixes INSTR_OPERAND_FAULTs in SuperTuxKart.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4707
Fixes:
c6ed8bf77cb ("panfrost: Fix uniform_count on Midgard")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10507>
Jordan Justen [Thu, 29 Apr 2021 22:12:10 +0000 (15:12 -0700)]
intel/compiler: Fix INTEL_DEBUG=hex
With the missing else, this prints the compacted hex followed by hex
for an uncompacted version of the compacted instruction. It also
doesn't print hex for instructions that are not compacted.
Fixes:
bc4a127d6e1 ("intel/disasm: Label support in shader disassembly for UIP/JIP")
Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4245
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10535>
Jose Maria Casanova Crespo [Fri, 30 Apr 2021 00:29:48 +0000 (02:29 +0200)]
ci/v3d: Update piglit expectations.
As piglit job is manual, I forgot to update three new test passing at
spec@ext_image_dma_buf_import subgroup after merging
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10524
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10536>
Mike Blumenkrantz [Sun, 11 Apr 2021 17:48:20 +0000 (13:48 -0400)]
util/tc: split out drawid-using draws into a separate call
we can pre-filter these to reduce merge overhead
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10166>
Mike Blumenkrantz [Tue, 20 Apr 2021 15:50:06 +0000 (11:50 -0400)]
gallium: remove padding members from pipe_draw_info
these are no longer used, and the tc usage can be moved to the tc struct
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10166>
Mike Blumenkrantz [Sun, 11 Apr 2021 17:35:38 +0000 (13:35 -0400)]
gallium: split drawid out of pipe_draw_info and as a separate draw_vbo param
the only case in which this is nonzero is if a multidraw gets split by the frontend,
i.e., mesa core, and in all other cases it can be ignored. the value can also be ignored
for all indirect draws, though it seems many (most?) gallium drivers are not aware of this
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10166>
Mike Blumenkrantz [Mon, 19 Apr 2021 13:33:15 +0000 (09:33 -0400)]
mesa/st: rename DrawGalliumComplex -> DrawGalliumMultiMode
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10166>
Mike Blumenkrantz [Sun, 11 Apr 2021 14:26:29 +0000 (10:26 -0400)]
gallium: move pipe_draw_info::index_bias to pipe_draw_start_count_bias
this moves index_bias into the multidraw struct, enabling draws where the value
changes to be merged; the draw_info struct member is renamed and moved to the end
of the struct for tc use
u_vbuf still has some checks to split draws if index_bias changes, maybe
this can be removed at some point?
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10166>
Mike Blumenkrantz [Sun, 11 Apr 2021 13:49:49 +0000 (09:49 -0400)]
gallium: rename pipe_draw_start_count -> pipe_draw_start_count_bias
and add an index_bias member
no functional changes yet, just the rename and unused struct member
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10166>
Timothy Arceri [Tue, 27 Apr 2021 04:01:08 +0000 (14:01 +1000)]
mesa: fix glShaderSource() error handling
Section 7.1 (SHADER OBJECTS) of the OpenGL 4.6 spec says:
"An INVALID_VALUE error is generated if count is negative."
However a count of 0 is not an error. Previously it would cause a
GL_OUT_OF_MEMORY error.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10477>
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