bin/gen_release_notes.py: do not end "features" with "None"

Currently, the "New features" list unconditionally ends with a "None"
point, which makes no sense. The original author probably meant to check
whether the file is empty, so remove the else clause, and add the check
for emptiness.

Cc: mesa-stable
Signed-off-by: Konstantin Kharlamov <Hi-Angel@yandex.ru>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20241>
(cherry picked from commit bd807eecd16eb308e121ff6d51210edee8635083)

gen_release_notes: strip second newline in new features

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20132>
(cherry picked from commit 980d6a91eecb58acf5cdc356ec5a422304145af5)

.pick_status.json: Update to 38d6185432d1f19a5653b3892069cd350187f5b8

radeonsi/vcn: av1 film_grain output fix

use film grain surface as the output instead of target,
which should be kept for DPB process.

fixed: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6903

CC: 22.3
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20139>
(cherry picked from commit a7b3a279fb544431043908d12d5503916e18942e)

frontends/va: pass in film_grain_target as new output

In av1 film grain case, to use the film_grain_target
as the output, instead of target buffer, which is kept
as the input for DPB processing in film_grain output
scenario.

CC: 22.3
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20139>
(cherry picked from commit af695149e96bf276b52ff3715076ddc847c6b959)

frontneds/va: use current_display_picture from VA for film grain

use the interface defined in vaapi for av1 film grain's output
https://github.com/intel/libva/blob/master/va/va_dec_av1.h#L296-L304

CC: 22.3
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Mark Thompson <sw@jkqxz.net>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20139>
(cherry picked from commit 7e91f9486418ad69aaef9ca5ce539ae47995e1d9)

frontends/omx: initialize film_grain_target

set film_grain_target to NULL, and not using it
in omx path.

CC: 22.3
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20139>
(cherry picked from commit 7f71f732ea76e0376e58069200d19beb74b2cb62)

gallium: add film_grain_target into av1 dec desc

In vaapi, film_grain output will need to direct into
other output surface instead of the current render_target.

CC: 22.3
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20139>
(cherry picked from commit b70953f5baacb9066fc737ec56be678a2ebad425)

intel: Fix a hang caused by invalid dispatch enables on gfx6/7

Because commit b9403b1c477 moved dispatch enable handling away from the
compiler, brw_fs_get_dispatch_enables must be used to ensure valid
dispatch enable values.

v2: Fix gfx6 build and use brw_fs_get_dispatch_enables for gfx6 in crocus

Fixes: b9403b1c477 ("intel: factor out dispatch PS enabling logic")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20267>
(cherry picked from commit 4c986c58b3f2bf06ca17adb9bee0a79fa19bddd9)

docs/relnotes: add sha256sum for 22.3.2

VERSION: bump for 22.3.2

docs: add release notes for 22.3.2

etnaviv: disable linear PE by default

Linear PE causes a lot of issues in the ZS stage. While some of those issues
can be worked around on newer GPU cores by doing all ZS operations in the
late stage, GC600 r4653 exhibits spurious Z fails when linear PE is active
even though this GPU does not even have a early Z stage.

Disable linear PE for now, until the issue can be analyzed further. Leave the
debug option in place to allow to enable linear PE for testing.

Fixes: 43eb5e777e4b ("etnaviv: add debug option to disable linear PE feature")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20405>
(cherry picked from commit c5231025beea8e14ac549d62dce43074aa7b3755)

anv: handle null push descriptors in deferred optimization

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b49b18f0 ("anv: reduce BT emissions & surface state writes with push descriptors")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20410>
(cherry picked from commit 739a08ad2352f1c10bad623350c1e321d0fbc9af)

radv: Include view index SET_SH_REG in ace_predication_size.

This fixes an issue when conditional rendering and multiple views
were used with a task+mesh draw call.

Fixes: 2479b6286974c1467bec5120df96650d297dcb7f
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20098>
(cherry picked from commit d368914a388a209b2264b1e17b0a13feb1b25e95)

r600/sfn: Don't try to re-use the iterator when uses is updated

It seems on libc++ the iterator is invalidated when an element is removed
from the set, so make sure that we don't implicitely use the old,
invalidated iterator in the range based - open code the loop using while
instead.

Fixes: f3415c (r600/sfn: copy propagate register load chains)

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7931

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20394>
(cherry picked from commit 05fab97b2ce8ebd8420ded175101a0fa5110172c)

radv: Destroy mesh shader scratch ring in radv_queue_state_finish.

Fixes: 0280b526d58e85d65b53d3f9c8b0f7364d853751
Signed-off--by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20010>
(cherry picked from commit 64aa555909f414a6dd01c188af4d2b903c6a5338)

anv: Ensure we clear ANV_PIPE_PSS_STALL_SYNC_BIT on flush

Add the PSS stall bit to ANV_PIPE_STALL_BITS so that it get's cleared on
flush.

Fixes: f3c62973 ("anv,iris: PSS Stall Sync around color fast clears")

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20317>
(cherry picked from commit ad9c0e8cd9a95862b555615159b8a261036a7324)

radv/rt: Refactor exiting PLOC

The previous approach was susceptible to sync hazards, causing hangs in Doom Eternal.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7897
Fixes: 271865373 ("radv: Add PLOC shader")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20377>
(cherry picked from commit f0f5d5c5e5f50f6142afc9d3d28c88753c47207a)

radv/rt: Execute memory barrier before updating the phase end count

We want to be sure that the values were updated before letting other invocations continue.

Fixes: 271865373 ("radv: Add PLOC shader")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20377>
(cherry picked from commit 54ca0665c8a57e85525b569c890cb3dc3ccc679b)

radv/rt: PLOC fixes for active_leaf_count

Fixes: 271865373 ("radv: Add PLOC shader")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20377>
(cherry picked from commit 0e0f42723e992701413b315f3eea344c7e7a0cfd)

etnaviv: Do expose 2D texture support on pre-halti GPUs

Commit d08bd9a8d8b ("etnaviv: don't expose array and 3D texture support on pre-halti GPUs")
started returning 0 from PIPE_CAP_MAX_TEXTURE_2D_SIZE as well due to switch
case fallthrough. Reinstate the behavior of PIPE_CAP_MAX_TEXTURE_2D_SIZE,
while at the same time, retain the new behavior introduced by commit
d08bd9a8d8b , Otherwise not even kmscube displays the spinning cube,
weston does not display desktop and so on.

Triggered on "Vivante GC600 rev 4653" , i.MX8M Mini .

Fixes: d08bd9a8d8b ("etnaviv: don't expose array and 3D texture support on pre-halti GPUs")
Closes: #7898
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20373>
(cherry picked from commit 18f4dc6b75b1e3697d40f8c6a39d41179ccd2238)

panfrost: Align WSI strides for tiled AFBC

When calculating legacy WSI strides for tiled AFBC, we need to account for the
greater alignment requirement of tiled AFBC, or importing resources will fail
later.

Since tiled AFBC is only supported on v7 and later, and AFBC of window surfaces
isn't being used on Linux on v7 and later, this probably hasn't been hit in
practice. Probably.

We're about to fix AFBC of window surfaces so we need to fix this side first.

Fixes: 0255f554f39 ("panfrost: Advertise 16x16 tiled AFBC")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20311>
(cherry picked from commit a3f9aa3b3e4db19d7a33bc0017d0291336efea10)

OpenCL/draw module: Support linking with LLVM and clang 15 static libraries

Cc: mesa-stable
Closes: #7243

Closes: #7487

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19009>
(cherry picked from commit f69b43ae3ef9a34ea360d96dfc698f83fad7a823)

radv/gfx11: disable mesh shaders

Even if the perftest is used, these should be disabled on GFX11. We
don't implement it yet

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 22.3 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20358>
(cherry picked from commit 74ceff1816ff4145e41893f53e048d2b10a0e767)

aco/gfx11: export mrtz in discard early exit for non-color shaders

If a shader doesn't export any color targets and instead only exports
mrtz, the discard early exit block should match.

Fixes artifacts on Lara in Rise of the Tomb Raider benchmark and hair in
The Witcher 3 (classic).

https://reviews.llvm.org/D128185

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: bc8da20dda6 ("aco: export MRT0 instead of NULL on GFX11")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20345>
(cherry picked from commit 192486b7aa5ef3b24516e16b0e219fad7032fb7c)

v3dv: be more careful when restoring dirty state after meta operations

So far we have been only restoring dirty dynamic states used by meta
pipelines however, static state from meta pipelines will also clear
dirty flags, preventing follow-up draw calls in the command buffer
to honor these if they are flagged as dynamic states in their
pipelines. Fix this by always resetting all dirty state flags after
a meta operation so we re-emit all the state we need with the next draw
call.

Fixes:
dEQP-VK.dynamic_state.monolithic.image.clear

cc: mesa-stable

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20356>
(cherry picked from commit df8611e816295eb27139ce966a6d37d78893fa65)

v3dv: pipeline creation feedback may not request all stages

Nothing in the spec seems to require that the number of stages for
which creation feedback is requested must match the number of stages
available in the pipeline. In fact, the spec explicitly mentions
that this number could be 0:

   "If pipelineStageCreationFeedbackCount is not 0,
    pPipelineStageCreationFeedbacks must be a valid pointer to an
    array of pipelineStageCreationFeedbackCount
    VkPipelineCreationFeedback structures"

Fixes an assert crash in:
dEQP-VK.pipeline.monolithic.creation_feedback.graphics_tests.vertex_stage_fragment_stage_no_cache_zero_out_feedback_cout

cc: mesa-stable

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20352>
(cherry picked from commit 3cc863649fe6040c1284d8ac753cd418aaad3c75)

r300: be more careful with presubtract and non-native swizzles

The problematic scenario is when we have the same source used by both
normal and presubtract argument. We check that case currently and count
the source only once. However if one of the arguments uses a non-native
swizzle, we have to rewrite it later and the source changes. Therefore
we end with too many sources and fail later during pair translation.

Example:
ADD temp[21].xy, temp[20].xy__, temp[17].xy__;
MAD temp[22].xy, temp[17].zw__, temp[11].xy__, temp[21].xy__;

will get converted to

MAD temp[22].xy, temp[17].zw__, temp[11].xy__, (temp[17] + temp[20]).xy__;

however after dataflow swizzles pass we end with

MOV temp[3].x, temp[17].z___;
MOV temp[3].y, temp[17]._w__;
MAD temp[22].xy, temp[3].xy__, temp[11].xy__, (temp[17] + temp[20]).xy__;

Just skip the "don't count the same source twice" optimization when a
non-native swizzle is used to fix 2 dEQP atan2 tests.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Tested-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19764>
(cherry picked from commit 6738a7b5b4ae7a8f14fda0d39f760db4e29db186)

v3dv: honor render area in subpass resolve fallback

When falling back to handling subpass resolves via separate
image resolves we were resolving the entire attachment instead
of limiting the resolve to the render area defined for the render
pass.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20331>
(cherry picked from commit ce94d3e48d4b4bf9a7d3d15fbf4a400fd0749522)

v3dv: handle depth/stencil resolves we can't implement via TLB

If we can't use the TLB to do a subpass resolve we have a fallaback
that emits separate image resolves, but this fallback was only
handling color resolves. This adds depth/stencil as well.

Fixes some of the issues we have with CTS 1.3.4 in:
dEQP-VK.pipeline.monolithic.multisample.misc.*

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20331>
(cherry picked from commit 9ac053e0a2d3ae431145b632119e5cfa3a3007cf)

v3dv: don't resolve by averaging samples on depth/stencil resolves

For these we always want to use sample_0, averaging is reserved for
color formats. We were already doing this correctly for depth/stencil
resolved in render passes, but not for those happening through
vkCmdResolveImage.

Fixes some of the issues we have with CTS 1.3.4 in:
dEQP-VK.pipeline.monolithic.multisample.misc.*

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20331>
(cherry picked from commit 284285376bc7498d608dafe8b75352216fc3f483)

v3dv: always store/restore attachment state during meta operations

attachment state is only relevant during render passes, however,
there is a corner case: if we can't resolve an attachment in a
subpass using the hardware, we emit a manual image resolve in the
driver which can trigger a meta operation via blit. In this case,
we pretend we are not in a render pass (since vulkan disallows
blits/resolves in a render pass) but we really want to keep the
attachment state after the meta operation.

Fixes some of the issues we have with CTS 1.3.4 in:
dEQP-VK.pipeline.monolithic.multisample.misc.*

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20331>
(cherry picked from commit 6117f855ee700e7addc14be64b8370f9b91a2120)

anv: fixup another dirty issue with gpu_memcpy

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20335>
(cherry picked from commit b21cd1ee1ba85065b27bf71a7d3b8498dcdd6b76)

radv/rra: Emit leaf node ids for leaf nodes instead of internal nodes

Fixes: e4283d8 ("radv/rra: Handle box16 nodes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20184>
(cherry picked from commit ab8777b384e5083ed3508a5143f73c7b411f139d)

aco: Don't accept constants on p_bpermute.

The sequence emitted for this pseudo instruction is not ready
to handle constants or literals at all.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20293>
(cherry picked from commit 614348f28be16fb8a3763bd68064652160975411)

zink: Fix reversed cap declarations for ImageBuffer

Fixes validation fails on
KHR-GLES31.core.texture_buffer.texture_buffer_texture_buffer_range.

Fixes: f55a4407ef97 ("zink: more accurately set {Sampled,Image}Buffer caps")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20308>
(cherry picked from commit 9dedbf66f62bdeda7126f0f6cd38c2597c930391)

.pick_status.json: Update to def474e916b69b86ed49c895c7418ba54a0e8252

docs/relnotes: add 22.3.1 to index

docs/relnotes: add sha256sum for 22.3.1

VERSION: bump for 22.3.1

docs: add release notes for 22.3.1

gallium/vl: return the buffer plane order for yuv444p format

plane order is expected when trying to render yuv surfaces, update it for yuv444p

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19445>
(cherry picked from commit f1ea0bc18aa6dd62554d7c556c087640dbc8a168)

frontends/va: fix crash during grayscale rendering

crash is observed as format is assumed to be yuv and buffer plane
order is undefined for monochrome. luma only format is not to be
considered yuv format. It has to be rendered with rgb=rrr.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20165>
(cherry picked from commit 6a3179c5a97f9a45006af2781d0af4b437784515)

anv: disable Wa_1806565034 when robustImageAccess is enabled

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5711
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7859
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20280>
(cherry picked from commit a921486e2a6ca5fc873a6e2f9c61fb5bef4cf3d9)

intel/fs: make Wa_1806565034 conditional to non robust access

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20280>
(cherry picked from commit 94bb4a13fa294204e32b88a098c2d49a0c82a5c3)

isl: make Wa_1806565034 conditional to non robust access

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20280>
(cherry picked from commit 89a550a37b0bb32bc3dfd92062f9fe6eb05c11db)

glsl_to_nir: Fix NIR bit-size of ir_triop_bitfield_extract and ir_quadop_bitfield_insert

Previously these would return result->bit_size of 32 even though the
type might have been int16_t or uint16_t.  This prevents many assertion
failures in "glsl: Use nir_type_convert instead of
nir_type_conversion_op" on zink.

Fixes: 5e922fbc160 ("glsl_to_nir: fix bitfield_extract with 16-bit operands")
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15121>
(cherry picked from commit 43da8223121b8807d2dd7fcf1276d145242365e6)

v3dv: skip some invalid tests

Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20305>
(cherry picked from commit 408f1c689c2bcd3e746d025bfbb623dd8c6c81ef)

radeonsi/vcn: fix regression in yuv422 jpeg decode

- yuv422 decode was blocked in 12acee17fad5, enable it back.
- nv12 yuv422 and grayscale decode is supported on all versions.
- JPEG2 and higher versions supports 444p decode.
- add l8_unorm to supported formats, can be used for grayscale.

Fixes: 12acee17fad5 (frontends/va: reallocate surface for yuv400/yuv444 picture)

v2: indent the switch case correctly (Thong Thai)

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20165>
(cherry picked from commit 7ad4a5079e8ad0b9f3ab7924cc3dfec5f74ea88d)

radeonsi/vcn: enable yuv422 jpeg decode

add yuv422 to supported decode format on asics that support it.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19445>
(cherry picked from commit 581220aa5471f4957a33d3156b07a03969972136)

radv: do not remove the PointSize built-in for polygon mode as points

Determine if it can be removed when generating the graphics pipeline
key because of dynamic states.

Fixes new CTS dEQP-VK.rasterization.polygon_as_large_points.* and also
spec@!opengl 1.1@polygon-offset with Zink/RADV.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20073>
(cherry picked from commit b4f940913d386bad0e25a1e224d0f39631124593)

vdpau: allow building vdpau st with virgl only

Fixes: 6b5aecb1955 ("virgl: add support for hardware video acceleration")

Signed-off-by: Jan Palus <jpalus@fastmail.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20108>
(cherry picked from commit 8560ce28c22f82895dd95c185b59dcaaab249c6a)

radv: Handle NULL miss shaders

Fixes reflections in DOOM Eternal.

Fixes: 85580faa ("radv: Add ray traversal loop.")
Closes: #6210
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20270>
(cherry picked from commit 568fa71ef8d825b735fdbf6747ada3d7cfe95eff)

intel: Fix crashes for importing drm buffer

image_aspect_to_binding() converts aspect to index by subrracting
VK_IMAGE_ASPECT_MEMORY_PLANE_0_BIT_EXT, however these enum values
are bitfields, not consecutive numbers, so comparing and subtracting
them won't work.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20269>
(cherry picked from commit 7642f3b99c8b17c7cfa1f140c65ce82e7dbcea2b)

anv: fixup descriptor copies

I did not properly understood that we cannot access the views written
to the descriptor sets because they might have been destroyed after
the write operation and the copy operation is allowed to copy what is
invalid data. The shader just can't access it.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 03e1e19246 ("anv: Refactor descriptor copy")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20222>
(cherry picked from commit a0991c7c794da39bf1a4b5fb5484b77afde200cc)

hasvk: pipelineStageCreationFeedbackCount is allowed to be 0

Fixes: 6601e5d6fc6 ("anv: implement VK_EXT_pipeline_creation_feedback")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20216>
(cherry picked from commit 68b546ec3daacc93513b31583cbe6eb7f8fdc25c)

intel/nir/rt: fixup primitive id

There is a delta index value in the hit structure, we forgot to add it
to the base value.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 046571479028 ("intel/nir/rt: add more helpers for ray queries")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7565
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19346>
(cherry picked from commit 610639682533783796fe32bdcb2b4d3375fae56f)

radv: fix hashing descriptor set layout

Shouldn't have pointers.

Fixes: 19f8d338761 ("radv: Use vk_descriptor_set_layout")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20250>
(cherry picked from commit 13f39da71a69026445fc5455d749858aa7ad94dc)

nir: Do not consider phis with incompatible dests equal

CSE tries to collapse equal instructions, and collapsing two phis with incompatible dests is illegal.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Fixes: 6bdce55c ("nir: Add a basic CSE pass")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19960>
(cherry picked from commit a54c2c828941ef1325fc1a3b49eba32f3c964f0d)

Revert "anv: compile anv_acceleration_structure.c"

This reverts commit 74d0be27ae9eb666df948874a20a3b4464df7db1.

Also remove anv_acceleration_structure.c, it was meant to be removed
earlier. There was probably a rebase issue somewhere.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20248>
(cherry picked from commit d608706875996b05df48b0e35ee0456f0f2ae8cf)

aco/ra: don't swap p_create_vector operand with definition blocker for scc

SCC is 1-bit, and we can't copy a 32-bit value into it.

Fixes dEQP-VK.spirv_assembly.type.scalar.i32.iequal_tesse with
ACO_DEBUG=noopt.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 9476986e6f6 ("aco/ra: special-case get_reg_for_create_vector_copy()")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20240>
(cherry picked from commit a05dd58309caf7e3857eb7f02084d8c9667c9efc)

frontends/va: fix gst videotestsrc h264 enc fail issue.

problem:
when doing "gst-launch-1.0 -v videotestsrc num-buffer=10 !
   vaapih264enc ! fakeink"

The command will fail due to gst will fetch the first
available supported format in the list, it becomes P010_LE
due to the commit in

[0b02db3007]
frontends/va: fixed av1 decoding 10bit ffmpeg output YUV issue

fix:
move the P010_LE code block to the end of the function, the sequence
of the supported formats restored to its original.

cc: mesa-stable

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20242>
(cherry picked from commit a73e86e0a5eb58e2f25f7b7419a78c122cc5ab1a)

anv: emit sample mask state independent of fragment stage

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7861
Fixes: 9f6af43743d ("anv: dynamic multisample sample mask")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20221>
(cherry picked from commit 68ef0d84481fd92df6cde8935f079d958e6b36e9)

radeonsi: disable av1 decode for navi24

Disable AV1 decode for Navi24 since hardware doesn't support.

fixed: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7855

cc: mesa-stable

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20230>
(cherry picked from commit 5233551e1912519b456515ac8da7a62c9779fca8)

intel/fs: implement Wa_14017989577

The first instruction of any kernel should have non-zero emask. This
restriction needs to be obeyed to avoid GPU hangs.

Patch adds a function to insert dummy mov as first instruction
to make sure this requirement is fulfilled.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20194>
(cherry picked from commit bc4b7de0d0469e296f7ec4626fccdf97926b1c8e)

intel/compiler: Set NoMask on cr0 access for float controls mode

This is trying to clear a bit in the control register.  However, it's
executing with whatever channel mask happens to be active.  Typically
this is the one at the start of the program, so at least some channels
will be active.  Typically the first channel will be active due to
packed dispatch, but that's not always guaranteed.  Without NoMask,
the float controls writes may randomly not happen.

Recent GPUs also seem to have a hang issue when the first instruction in
the shader doesn't have any active channels.  Having an instruction with
NoMask at the start of the program works around the issue.  See HSD bug
14017989577.  In our case, the float controls preamble was breaking that
restriction every time, causing us to run into this problem frequently.

Thanks to Tapani Pälli for finding this hang issue, and Francisco
Jerez and Lionel Landwerlin for helping pinpoint this issue during
review of a workaround patch in !20194.

Fixes GPU hangs in Elder Scrolls Online, Witcher 3, and likely more.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7639
Fixes: 9da56ffc522 ("i965/fs: add emit_shader_float_controls_execution_mode() and aux functions")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20214>
(cherry picked from commit bafbe7c23a1cdd8c27ee5ea2da6b0575c53e2c5f)

vulkan: VkPolygonMode has a bit more than two values

Fixes: 9d0ed9cbcc0 ("vulkan: Add more dynamic rasterizer state")

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20212>
(cherry picked from commit e1ab7629f8a459df87009c7cb28b41acfb17e45c)

anv/hasvk: Clamping Scissor Rect values in a valid range

On cmd_buffer_emit_scissor(), if VkViewport height or width are set to
a value lower than 1.0, y_max or x_max can be attributed negative values,
causing an overflow. That leads to ScissorRectangleYMax or
ScissorRectangleXMax to be set to values on an unsupported range.

Clamping x_max and y_max in the valid range solves the problem.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7471
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20200>
(cherry picked from commit 2e775b8bdbc5cd0d120b5c757188f6e85bf0d59d)

meson: Do not enable drm for KGSL Turnip build

Android may use either DRM or some downstream solution, KGSL is a
downstream kernel driver for Adreno. Don't enable DRM when we want
Turnip to use KGSL instead of DRM.

Fixes: 09ac29cca9bf7978911f81bcfce12ce71c260a97
("meson: Enable system_has_kms_drm for android")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20168>
(cherry picked from commit 1cfc413c9a4cdd26222197ab0a518c2b603d82b1)

glx: fix xshm check to init xshm_opcode.

Found and proposed by Ray Strode (halfline)

Fixes: 68e89401140d ("glx/drisw: use xcb instead of X to query connection")
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20188>
(cherry picked from commit 57b7102ef96a282128ead4e7a8c03c7fdb53e71a)

zink: don't use defunct custom-flag

We're no longer respecting this flag, so there's no need in setting it.

Fixes: 00dc0036bb6 ("zink: flatten out buffer creation usage flags codepath")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20183>
(cherry picked from commit 2ccf481c17ccded161b9eecb63a257d81056e3ec)

venus: fix deqp tests failed on iub descriptor type

Fixes: abae9d4831b ("Add the iub binding count tracking")

Signed-off-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20064>
(cherry picked from commit fbf4c6e43ff810625ff916d40c6b00429adaaf14)

radv: fix guardband if the polygon mode is points or lines

If points or lines are drawn using the polygon mode, the guardband
should be adjusted for large points/lines.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20185>
(cherry picked from commit 12f26b5e6d57a1fd03c1f1fb0ab8ccae657026ab)

nir/lower_task_shader: fix task payload corruption when shared memory workaround is enabled

We were not taking into account that when all invocations within workgroup
are active, we'll copy more data than needed, corrupting task payload
of other workgroups.

Fixes: 8aff8d3dd42 ("nir: Add common task shader lowering to make the backend's job easier.")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20080>
(cherry picked from commit ffefa386fda5aec8f66b4499d93b41a846a0b86c)

aco: more carefully apply constant offsets into scratch accesses

Death stranding does scratch_arr[80-idx]. This doesn't seem to work if we
try to combine the subtraction into the access.

fossil-db (navi21):
Totals from 52 (0.04% of 135636) affected shaders:
Instrs: 78560 -> 79036 (+0.61%)
CodeSize: 427940 -> 431188 (+0.76%)
Latency: 1313809 -> 1318142 (+0.33%)
InvThroughput: 292833 -> 293842 (+0.34%)
VClause: 2361 -> 2555 (+8.22%); split: -0.51%, +8.73%
Copies: 8767 -> 8746 (-0.24%); split: -0.35%, +0.11%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 0e783d687a3 ("aco: use scratch_* for scratch load/store on GFX9+")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7735
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20117>
(cherry picked from commit 381de3c809fce5427308c696bbd313360194eff4)

radeonsi/vcn: adding av1 decoding film grain block

add the logic for calculating film grain related
coefficients for VCN to generate film grain output.

Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19660>
(cherry picked from commit b28356745686571676742f3822fd371b95e8742b)

radv: use LATE_Z for depth/stencil attachments used in feedback loops

To make sure shader invocations read the correct values.

Fixes dEQP-VK.rasterization.rasterization_order_attachment_access.*.samples_*.multi_draw_barriers

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19728>
(cherry picked from commit a42f8d49c39eb59a520fde05fdcab0ffab3a16c6)

nir: fix nir_link_varying_precision

link_varyings ignores precisions and can assign the same location to
variables with different precisions.  nir_link_varying_precision should
check location_frac as well.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20113>
(cherry picked from commit 7244d885164aa59ca136358d256a0078b24a455d)

intel: add missing restriction on fragment simd dispatch

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7755
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20169>
(cherry picked from commit d4cd33630a9b90b95390f10d3aaa52f6f5e20245)

intel: factor out dispatch PS enabling logic

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Tested-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20169>
(cherry picked from commit b9403b1c477e7af04114ae6a4e16ca370e22253c)

radv: do not set ZPASS_INCREMENT_DISABLE on GFX11

This field no longer exists.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20090>
(cherry picked from commit b051719b05894c3c5b9f0f8ad919be478b43697b)

radv: fix emitting invalid color attachments

Note sure how this happened.

Fixes: 97dc28b1776 ("radv: fix configuring COLOR_INVALID on GFX11")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20127>
(cherry picked from commit 664aa7a37b540b27f8bd96b1d685c8e449d6a711)

dzn: Don't crash when libd3d12.so can't be found

`dzn_instance_create` will call `dzn_instance_destroy` when the d3d12
library fails to load. Just like the issue in `d3d12_screen`, this will
lead to a crash because `d3d12_mod` is NULL.

To fix this, only close the library after if it was actually opened.

Cc: mesa-stable
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20145>
(cherry picked from commit b5133894005720db24a8e0cc17e047a291953ff4)

d3d12: Don't crash when libd3d12.so can't be found

`d3d12_destroy_screen` is called by `d3d12_create_dxcore_screen` after
`d3d12_init_screen_base` fails and attempts to call `util_dl_close` on
a NULL pointer, leading to an abort.

To fix this, only close the library after if it was actually opened.

Cc: mesa-stable
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20145>
(cherry picked from commit b3d1ae19f2f4d93cf0a5f45a598149ac4e8e05aa)

anv: Defer flushing PIPE_CONTROL bits forbidden in CCS while in GPGPU mode

Fixes: 313aeee8 ("anv: Use pending pipe control mechanism in flush_pipeline_select()
")

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7816
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20124>
(cherry picked from commit 77ecf9149c7fdadbb24b471785c4d5b4e285f2df)

dxil: Use nir_const_value_for_uint in dxil_nir_lower_int_samplers

This change should avoid any accidental rounding issues because of
border colors getting stored in a float in dxil_wrap_sampler_state.  It
also switches us to using the correct helpers for nir_const_value so we
can avoid any weird uninitialized data failures that can be caused by
filling out the fields in the struct directly.

Fixes: b9c61379ab4c ("microsoft/compiler: translate nir to dxil")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19689>
(cherry picked from commit cd5c66e165374026d62692bcbf69a7157e460f91)

r600/nir: Fix u64vec2 immediate lowering

There were a couple of issues here:

 1. We should be using nir_const_value_for_uint instead of setting the
    union fields directly to ensure the rest of the union is zeroed.

 2. It was always filling out the first two components of val even if
    the incoming constant had 2 64-bit components.

Fixes: 165fb5117bf7 ("r600/sfn: add lowering passes to get 64 bit ops lowered to 32 bit vec2")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19689>
(cherry picked from commit f3f1c28f8e6d40823e3d12415a8d0ea622f9fa20)

st/mesa: Use nir_const_value_for_bool() in ATIFS

Fixes: 0a179bb6e26b ("st/mesa: Generate NIR for ATI_fragment_shader instead of TGSI.")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19689>
(cherry picked from commit 49d86200e5cd8ac15c14131772644b21bf57865e)

nir: Use nir_const_value_for_int in nir_lower_subgroups

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7670
Fixes: e4e79de2a420 ("nir/subgroups: Support > 1 ballot components")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19689>
(cherry picked from commit e6de164e0305d517fb66c01c9fc8931c278867f6)

radv/rra: Set the metadata size correctly

Fixes: 5749806 ("radv: Add Radeon Raytracing Analyzer trace dumping utilities")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20047>
(cherry picked from commit bb6b45e26ed56af8a94357a58fd849143671cf7f)

nir/nir_opt_offsets: Prevent offsets going above max

In try_fold_load_store when trying to extract const addition from
non-const offset source, we should take into account that there is
already a constant base offset, which should count towards the limit.

The issue was found in "Monster Hunter: World" running on Turnip.

Fixes: cac6f633b21799bd1ecc35471d73a0bd190ccada
("nir/opt_offsets: Use nir_ssa_scalar to chase offset additions.")

Well, the issue was present before this commit but it made a lot
of changes in surrounding code.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20099>
(cherry picked from commit 5d025f4003b34c3540b62f9146a5e68da7756cf2)

anv: correctly predicate ray tracing

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 7479fe6ae093 ("anv: Implement vkCmdTraceRays and vkCmdTraceRaysIndirect")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20011>
(cherry picked from commit af3f7948d149faded1b4f24ec5e6ae03001e7cfb)

isl: don't report I915_FORMAT_MOD_Y_TILED_CCS on Gfx8

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19852>
(cherry picked from commit 0626b68c88df50e30e61e9fd2ba3e46144ff9ad5)

ir3: Reduce the maximum allowed imm offset for shared var load/store

STL/LDL have 13 bits to store imm offset. However the most significant
bit in the offset is a sign bit, so the positive offset is limited by
12 bits.

nir_opt_offsets only has the upper limit and doesn't deal with
negative offsets, so shared_max should be changed to `(1 << 12) - 1`.

The issue was found in "Monster Hunter: World".

Fixes: 0b2da9d795610df15346a594384c39a096be338f
("ir3: Limit the maximum imm offset in nir_opt_offset for shared vars")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20100>
(cherry picked from commit 8f0177b3345f8bcc3673b8a2a7c36ea36cbaa029)

ci: Rebalance radv/grunt testing

We've recently rebalanced our lab devices to get a fewer number of
grunts. Switch to scheduling only on the newer shinier ones, running
fewer tests. We'll evaluate the runtime, and if they're quick enough
then we can increase the amount of testing we do.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20081>
(cherry picked from commit 921cfcf4c4f5cb6f82ef978587e0462218093542)

v3dv: fix job serialization for single sync path

The idea in the single sync path is that we serialize any job that
needs to wait, however, our ANY queue syncobj only tracks the last job
submitted to any hardware queue, so in practice when we wait on this
we are only serializing against the queue to which we have submitted
the last job, which is not correct.

Fix that by accumulating the last job sync into the ANY queue synbcobj
to ensure that waiting on this syncobj effectively waits on all
hardware queues.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20078>
(cherry picked from commit 4276ec9f2af33da270ca9cf6a6a9a62b2a4d060a)

v3dv: make single-sync paths more explicit

Instead of having functions that return early in multi-sync mode
let's only call them when we are in single-sync mode. I think this
makes the code more explicit.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20078>
(cherry picked from commit 95b9293eeb02f3b43fb7de5afc6f7c89ffffe92f)

intel/compiler: user payload starts after TUE header & its padding

All data written by the user are offset by TUE header size.
Without this patch we copy the correct amount of user data, but both
"from" and "to" offsets are wrong.

Fixes: 37e78803d7b ("intel/compiler: use nir_lower_task_shader pass")

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19409>
(cherry picked from commit db0e6f9a07b49a95d99c2b2c25fd8a008466c4e8)

nir/lower_task_shader: allow offsetting of the start of payload

We need this, because on Intel task payload starts with private header,
followed by user-accessible data.

Fixes: 37e78803d7b ("intel/compiler: use nir_lower_task_shader pass")

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19409>
(cherry picked from commit f6adfd6278301aa772d3d44fc64ade21c9860574)