Rhys Perry [Fri, 11 Jun 2021 09:51:52 +0000 (10:51 +0100)]
radv: allow VK_FORMAT_R8G8_SRGB sampling
No reason why we can't do this. AMDVLK also allows this.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11317>
Jason Ekstrand [Fri, 18 Jun 2021 13:17:14 +0000 (08:17 -0500)]
nir: Document all the ALU opcodes
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11438>
Jason Ekstrand [Fri, 18 Jun 2021 13:16:18 +0000 (08:16 -0500)]
nir,docs: Add docs for NIR ALU instructions
About half or more of the text here is actually from Connor Abbot. I've
edited it a bit to bring it up-to-date and make a few things more clear.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11438>
Jason Ekstrand [Thu, 17 Jun 2021 15:32:34 +0000 (10:32 -0500)]
nir: Require vectorized ALU ops to be all-or-nothing
Long ago, the semantics of bcsel were such that it took a single boolean
value and selected between whole vectors. These days, it takes a vector
boolean with the assumption that if you want the old behavior you can
just use a .xxxx swizzle. There currently are no opcodes which use a
output_size of 0 but have a scalar or fixed-vector input. Let's
disallow it for now to force us to think through the semantics again if
this ever comes up as something someone actually wants.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11438>
Rhys Perry [Wed, 13 Jan 2021 15:50:52 +0000 (15:50 +0000)]
nir/propagate_invariant: add invariant_prim option
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11035>
Mike Blumenkrantz [Mon, 21 Jun 2021 13:49:18 +0000 (09:49 -0400)]
zink: handle custom border color without matching wrap mode case
this is just default border color and the custom color is ignored
Fixes:
36f4e61403a ("zink: rework border color handling")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11495>
Jason Ekstrand [Mon, 21 Jun 2021 14:05:23 +0000 (09:05 -0500)]
vulkan: Update the XML and headers to 1.2.182
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11497>
Jason Ekstrand [Fri, 18 Jun 2021 14:28:59 +0000 (09:28 -0500)]
nir,vc4: Suffix a bunch of unorm 4x8 opcodes _vc4
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11463>
Jason Ekstrand [Fri, 18 Jun 2021 14:21:07 +0000 (09:21 -0500)]
nir,panfrost: Suffix fsat_signed and fclamp_pos with _mali
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11463>
Jason Ekstrand [Fri, 18 Jun 2021 14:17:01 +0000 (09:17 -0500)]
nir,amd: Suffix nir_op_cube_face_coord/index with _amd
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11463>
Timur Kristóf [Mon, 14 Jun 2021 15:31:33 +0000 (17:31 +0200)]
aco: Fix checking if load_shared is used by cross lane instructions.
This commit fixes two issues with it:
1. Prevent it from going into an infinite loop.
2. Check all uses, not just first use.
Closes: #4916
Fixes:
b4e22eb4822d74a6e981c629ddff9bcd29b9a0ec
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11361>
Andres Gomez [Fri, 26 Mar 2021 22:56:46 +0000 (00:56 +0200)]
ci: use bash with download-git-cache.sh
It's a bash script, so make sure we use bash and not just sh.
Reviewed-by: Benjamin Tissoires <benjamin.tissoires@gmail.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9865>
Bas Nieuwenhuizen [Sat, 19 Jun 2021 23:15:29 +0000 (01:15 +0200)]
util/fossilize_db: Only lock the db file, not the index.
This thing is entirely opt-in wrt caring about it when writing to
a file anyway. Since we also lock the two at the same time and they
have an 1-1 relation we can just lock one of the two files. Saves
some syscalls.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11485>
Bas Nieuwenhuizen [Sat, 19 Jun 2021 23:06:53 +0000 (01:06 +0200)]
util/fossilize_db: Do not lock the fossilize db permanently.
This avoids all locks for reads and using lock only while actually
writing.
This is enabled by doing two things:
1) Reading the index incrementally. This way we get new entries
written by other processes and do not write duplicate entries.
2) Taking the lock only during writes, and applying the incremental
read while holding the lock so we always append to the actual end of the file.
Fixes:
eca6bb9540d ("util/fossilize_db: add basic fossilize db util to read/write shader caches")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11485>
Bas Nieuwenhuizen [Sat, 19 Jun 2021 17:51:09 +0000 (19:51 +0200)]
util/fossilize_db: Split out reading the index.
Fixes:
eca6bb9540d ("util/fossilize_db: add basic fossilize db util to read/write shader caches")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11485>
Bas Nieuwenhuizen [Sat, 19 Jun 2021 16:40:49 +0000 (18:40 +0200)]
util/fossilize_db: Pull seek into lock.
Otherwise the seek can overlap with other reads/writes.
Fixes:
eca6bb9540d ("util/fossilize_db: add basic fossilize db util to read/write shader caches")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11485>
Bas Nieuwenhuizen [Fri, 18 Jun 2021 22:02:52 +0000 (00:02 +0200)]
radv: Add -Wpointer-arith.
Gives earlier indications of MSVC issues.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11478>
Timur Kristóf [Sat, 19 Jun 2021 14:09:38 +0000 (16:09 +0200)]
ac/nir: Update TCS output barriers with nir_var_mem_shared.
Output loads and stores are lowered to shared memory access,
so we have to update the barriers to also reflect this.
Closes: #4955
Fixes:
bf966d1c1dd968116b8b547ca2739f5113caccb5
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11484>
Erik Faye-Lund [Fri, 18 Jun 2021 14:34:42 +0000 (16:34 +0200)]
docs: use rst captions
This is slightly stronger semantically.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11464>
Erik Faye-Lund [Fri, 18 Jun 2021 11:38:31 +0000 (13:38 +0200)]
docs: use more file-roles
This makes the documentation a bit easier to read, and aids
spell-checkers, so let's specify these using file-roles.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11464>
Erik Faye-Lund [Fri, 18 Jun 2021 11:35:31 +0000 (13:35 +0200)]
docs: drop historic meson details
Similar to the last few commits, we require Meson 0.52 now. There's no
point in confusing users with specifying what versions supports what
here, as all supported versions works the same way now.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11464>
Erik Faye-Lund [Fri, 18 Jun 2021 11:32:27 +0000 (13:32 +0200)]
docs: remove outdated clarification
Similar to the previous commit, we now require Meson 0.52 all the time,
so there's no point in singling this out.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11464>
Erik Faye-Lund [Fri, 18 Jun 2021 11:28:48 +0000 (13:28 +0200)]
docs: remove outdated meson-section
We're already requiring Meson 0.52, so there's no point in mentioning
this old work-around.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11464>
Iago Toral Quiroga [Thu, 17 Jun 2021 08:53:02 +0000 (10:53 +0200)]
v3dv: remove const qualifier for resource pointer in view objects
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11443>
Iago Toral Quiroga [Thu, 17 Jun 2021 08:26:36 +0000 (10:26 +0200)]
v3dv: expose VK_KHR_copy_commands2
Relevant CTS tests:
dEQP-VK.api.copy_and_blit.copy_commands2.*
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11443>
Iago Toral Quiroga [Thu, 17 Jun 2021 08:18:14 +0000 (10:18 +0200)]
v3dv: implement vkCmdResolveImage2KHR
The common Vulkan code will call this to implement vkCmdResolveImage.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11443>
Iago Toral Quiroga [Thu, 17 Jun 2021 08:06:33 +0000 (10:06 +0200)]
v3dv: implement vkCmdCopyImage2KHR
The common Vulkan code will call this to implement vkCmdCopyImage.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11443>
Iago Toral Quiroga [Thu, 17 Jun 2021 07:58:02 +0000 (09:58 +0200)]
v3dv: implement vkCmdCopyBufferToImage2KHR and vkCmdCopyImageToBuffer2KHR
The common Vulkan code will call this to implement vkCmdCopyImageToBuffer.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11443>
Iago Toral Quiroga [Thu, 17 Jun 2021 07:46:37 +0000 (09:46 +0200)]
v3dv: implement vkCmdCopyBuffer2KHR
The common Vulkan code will call this to implement vkCmdCopyBuffer.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11443>
Iago Toral Quiroga [Thu, 17 Jun 2021 07:30:13 +0000 (09:30 +0200)]
v3dv: implement vkCmdBlitImage2KHR
The common Vulkan code will call this to implement vkCmdBlitImage.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11443>
Yurii Kolesnykov [Wed, 30 Sep 2020 11:35:30 +0000 (14:35 +0300)]
c_std=c11 in meson default_options
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/1020
Co-authored-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Signed-off-by: Yurii Kolesnykov <root@yurikoles.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6935>
Marek Olšák [Mon, 17 May 2021 14:17:52 +0000 (10:17 -0400)]
ac/surface: don't set DCC_PIPE_ALIGN modifier bit for gfx10 with 1 RB
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11486>
Marek Olšák [Mon, 24 May 2021 18:55:11 +0000 (14:55 -0400)]
ac/surface/tests: fix RB counts
The real number of RBs can be less than what GB_ADDR_CONFIG contains.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11486>
Marek Olšák [Tue, 1 Jun 2021 05:40:37 +0000 (01:40 -0400)]
radeonsi: move the accepting code into the bbox cull branch in NGG cull code
This reduces the number of jumps. No change in behavior.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11486>
Marek Olšák [Tue, 1 Jun 2021 05:09:57 +0000 (01:09 -0400)]
ac/llvm: add a callback to ac_cull_triangle to generate code in inner-most block
This will reduce jumps in culling code.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11486>
Marek Olšák [Mon, 31 May 2021 23:40:49 +0000 (19:40 -0400)]
radeonsi: fix multi draws for the prim discard CS
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11486>
Marek Olšák [Mon, 31 May 2021 23:36:53 +0000 (19:36 -0400)]
radeonsi: fix incorrect counting of compute_num_verts_rejected
Both cases should subtract to undo what is done in the conditional.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11486>
Marek Olšák [Mon, 31 May 2021 00:32:25 +0000 (20:32 -0400)]
radeonsi: use ac_build_bit_count instead of opencoding it
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11486>
Marek Olšák [Mon, 24 May 2021 19:44:55 +0000 (15:44 -0400)]
radeonsi: fix compile failures with SI_PRIM_DISCARD_DEBUG enabled
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11486>
Eleni Maria Stea [Thu, 10 Jun 2021 11:09:02 +0000 (14:09 +0300)]
egl: fix in expected type
Function mincore expects a pointer of type char* but we use an unsigned
char* instead generating signedness related warnings.
v2: Made the fix FreeBSD specific because the type is unsigned char* for
Linux and char* for FreeBSD. (Adam Jackson)
v3: We'd rather cast the param to (void*) to avoid warnings in all
systems (Adam Jackson)
Signed-off-by: Eleni Maria Stea <elene.mst@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11298>
Jason Ekstrand [Fri, 18 Jun 2021 22:17:17 +0000 (17:17 -0500)]
crocus: Drop extra_aux support
This exists for combined MCS+CCS or HiZ+CCS which was introduced on
Tigerlake. Crocus will never support hardware that has these features
so there's no point carrying the dead copied+pasted code from iris.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11483>
Bas Nieuwenhuizen [Wed, 31 Mar 2021 01:12:55 +0000 (03:12 +0200)]
radv: Enable VK_KHR_acceleration_structure with RADV_PERFTEST=rt.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
Bas Nieuwenhuizen [Fri, 28 May 2021 23:06:59 +0000 (01:06 +0200)]
radv: Add rt perftest flag.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
Bas Nieuwenhuizen [Fri, 9 Apr 2021 00:15:50 +0000 (02:15 +0200)]
radv: Expose formats for acceleration structure.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
Bas Nieuwenhuizen [Mon, 5 Apr 2021 10:03:37 +0000 (12:03 +0200)]
radv: Implement load_vulkan_descriptor for acceleration structures.
It always uses nir_address_format_64bit_global.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
Bas Nieuwenhuizen [Mon, 5 Apr 2021 09:42:37 +0000 (11:42 +0200)]
radv: Convert lower_intrinsics to a switch statement
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
Bas Nieuwenhuizen [Sun, 4 Apr 2021 23:23:43 +0000 (01:23 +0200)]
radv: Add acceleration structure descriptor set support.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
Bas Nieuwenhuizen [Tue, 18 May 2021 11:25:00 +0000 (13:25 +0200)]
radv: Implement device-side BVH building.
Same naive algorithm as the host build.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
Bas Nieuwenhuizen [Mon, 18 Jan 2021 11:11:19 +0000 (12:11 +0100)]
radv: Add initial CPU BVH building.
The algorithm used for the BVH:
1) first create 1 leaf per primitive (triangle/aabb/instance)
2) Then create internal layers from the bottom up until we are left with
1 node in the top layer. Node i in the layer will have children
(i*4+0) ... (i*4+3) in the previous layer.
This results in a very naive algorithm but it is also very simple to implement.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
Bas Nieuwenhuizen [Mon, 18 Jan 2021 00:28:35 +0000 (01:28 +0100)]
radv: Use the global BO list for acceleration structures.
We have nested structures so tracking this from the descriptor
set is going to be a mess.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
Jason Ekstrand [Mon, 22 Jun 2020 20:13:29 +0000 (15:13 -0500)]
util: Move the 4x4 matrix inverse function to u_math
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
Rob Clark [Fri, 18 Jun 2021 19:41:51 +0000 (12:41 -0700)]
freedreno/ci: Increase # of jobs for CI runners
The idea is that the tests will spend *some* time stalling waiting to
read back results from the GPU. So use a # of jobs that is slightly
more than the # of CPUs to keep the CPUs more busy.
Locally this is dropping a bit more than a minute off a parallel
deqp-gles31 run, so turn it on across the board for a6xx.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11477>
Rob Clark [Thu, 17 Jun 2021 20:57:15 +0000 (13:57 -0700)]
freedreno/ci: Start longest traces first
Shave off a bit of runtime on the CI job by starting the longer traces
first.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11477>
Dave Airlie [Fri, 18 Jun 2021 05:15:24 +0000 (15:15 +1000)]
crocus/gen6: fix depth blit blorp regression.
The tesseract fix broke depth blits using blorp as depth blits
on gen6 are done using the color engine. Just disable aux
up front on the destination for this case.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11456>
Emma Anholt [Wed, 16 Jun 2021 16:52:04 +0000 (09:52 -0700)]
freedreno/ir3: Move NIR printing to mesa_log.
Now we can get some NIR debug on Android.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
Emma Anholt [Wed, 16 Jun 2021 18:13:54 +0000 (11:13 -0700)]
nir: Add an interface for logging shaders with mesa_log*.
For debug on Android, it's useful to be able to print shaders to the
android log interface, since you don't usually have stdout/stderr.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
Emma Anholt [Wed, 16 Jun 2021 18:06:01 +0000 (11:06 -0700)]
freedreno/ir3: Move the native code output to mesa_log as well.
I didn't feel like rewriting ir3_shader_disasm() off of FILE *s, so use
the same trick as the disasm_info path above to write to memory and then
hand the multi-line blob off to mesa_log.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
Emma Anholt [Wed, 16 Jun 2021 17:30:19 +0000 (10:30 -0700)]
freedreno/ir3: Use mesa_log_stream() for ir3 disassembly.
This means you can get dumps on android, and output on Linux goes to
stderr. However, this does mean that on Linux the output goes from
looking like:
AFTER: ir3_legalize:
block3276208368 {
0000:0001:002: cov.u32s16 hr2.x, c2.x
0000:0002:002: mov.u32u32 r0.x, c0.x
[...]
to:
MESA: info: AFTER: ir3_legalize:
MESA: info: block3405271904 {
MESA: info: 0000:0001:002: cov.u32s16 hr2.x, c2.x
MESA: info: 0000:0002:002: mov.u32u32 r0.x, c0.x
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
Emma Anholt [Wed, 16 Jun 2021 17:20:35 +0000 (10:20 -0700)]
util/log: Add a streaming printf interface.
Often disassemblers and things in our drivers want to be able to
incrementally printf together a line, but that gets in the way of
Android's logging that wants to see a whole line all at once. Make a
little wrapper to do the ralloc_asprintf_rewrite_tail() and flushing lines
as they appear.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
Emma Anholt [Wed, 16 Jun 2021 16:49:01 +0000 (09:49 -0700)]
freedreno/ir3: Move the assert output to mesa_loge().
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
Emma Anholt [Wed, 16 Jun 2021 16:47:12 +0000 (09:47 -0700)]
freedreno: Move some driver debug printfs to mesa_logd.
This means the logging will work on Android, and won't get mixed up in
application stdout on Linux.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
Emma Anholt [Fri, 18 Jun 2021 05:15:52 +0000 (22:15 -0700)]
i915g: Add triangle provoking vertex support.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11470>
Eric Engestrom [Fri, 18 Jun 2021 16:42:34 +0000 (17:42 +0100)]
docs: update calendar and link releases notes for 21.1.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11472>
Eric Engestrom [Fri, 18 Jun 2021 16:35:13 +0000 (17:35 +0100)]
docs: add release notes for 21.1.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11472>
Mike Blumenkrantz [Fri, 18 Jun 2021 15:50:36 +0000 (11:50 -0400)]
nine: add zink to the build target
Reviewed-by: Axel Davy <davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11467>
Mike Blumenkrantz [Fri, 18 Jun 2021 16:56:43 +0000 (12:56 -0400)]
nine: only enable tgsi disk cache if the driver supports it
this crashes otherwise
Reviewed-by: Axel Davy <davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11471>
Samuel Pitoiset [Tue, 15 Jun 2021 06:20:24 +0000 (08:20 +0200)]
radv: fix dynamic culling and depth/stencil related dynamic states
To avoid overwriting previous dynamic state with default state from
the pipeline.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4926
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11375>
Mike Blumenkrantz [Fri, 18 Jun 2021 13:08:40 +0000 (09:08 -0400)]
radv: move pipe_misaligned and l2_coherent image checks to flags set on init
this should save 4-5% cpu in some cases
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11462>
Boyuan Zhang [Wed, 16 Jun 2021 15:39:16 +0000 (11:39 -0400)]
radeon/vcn: allocate non-tmz context buffer for VCN2+
By design, context buffer should be allocated as TMZ buffer for secure playback
for VCN 1 only. For VCN 2&2+, context buffer should be moved out of TMZ.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11388>
Boyuan Zhang [Mon, 14 Jun 2021 17:35:48 +0000 (13:35 -0400)]
radeon/vcn: move calc_dpb_size into create_decoder
Dpb buffer size calculation should based on the values provided in player's
decoder creation call. db_alignmet should be decided in decoder creation
call as well. Therefore, move db_alignment and dpb buffer size calculation
from rvcn_dec_message_decode to radeon_create_decoder function.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11378>
Jason Ekstrand [Tue, 15 Jun 2021 21:57:25 +0000 (16:57 -0500)]
docs/isl: Add detailed documentation about CCS compression
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
Jason Ekstrand [Tue, 15 Jun 2021 21:20:14 +0000 (16:20 -0500)]
docs/isl: Add detailed documentation about tiling on Intel GPUs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
Jason Ekstrand [Tue, 15 Jun 2021 04:44:05 +0000 (23:44 -0500)]
docs/isl: Add detailed documentation about isl formats
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
Jason Ekstrand [Tue, 15 Jun 2021 02:33:35 +0000 (21:33 -0500)]
docs/isl: Document ISL's units
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
Jason Ekstrand [Tue, 15 Jun 2021 02:33:18 +0000 (21:33 -0500)]
isl: Document more members of isl_surf
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
Jason Ekstrand [Mon, 14 Jun 2021 21:55:21 +0000 (16:55 -0500)]
docs: Begin documenting ISL
This commit mostly just adds the framework required to scrape
documentation out of the ISL sources and headers. The method chosen
here is a combination of doxygen and breathe (a sphinx extension for
doxygen integration). I'll freely admit that doxygen is pretty terrible
but it seems like the best option we have available to us today.
Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Daniel Stone <daniels@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
Mike Blumenkrantz [Tue, 11 May 2021 16:10:05 +0000 (12:10 -0400)]
zink: remove inlinable_uniforms_dirty_mask
this should've always just been flagging the shaders dirty directly
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11405>
Mike Blumenkrantz [Fri, 18 Jun 2021 04:17:10 +0000 (00:17 -0400)]
zink: remove duplicated bitflag filtering for inline uniforms
'bits' already does this
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11405>
Samuel Pitoiset [Wed, 9 Jun 2021 12:29:25 +0000 (14:29 +0200)]
radv: create only one pipeline for decompressing depth/stencil images
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11263>
Samuel Pitoiset [Wed, 9 Jun 2021 12:26:15 +0000 (14:26 +0200)]
radv: always decompress both aspects of a depth/stencil image
If compressed rendering is only used for the depth aspect of a
depth/stencil image, stencil might also be compressed and it needs
to be decompressed. This only happens for non-TC compatible images.
As long as the driver needs to decompress the depth aspect, I don't
think that decompressing the stencil aspect introduces extra cost.
Fixes dEQP-VK.renderpass*late_fragment_tests*.d32_sfloat_s8_uint for
chips that don't support TC-compat HTILE.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11263>
Samuel Pitoiset [Thu, 17 Jun 2021 12:46:50 +0000 (14:46 +0200)]
radv: reject binding buffer/image when the device memory is too small
From the Vulkan spec 1.2.181:
"The difference of the size of memory and memoryOffset must be
greater than or equal to the size member of the
VkMemoryRequirements structure returned from a call to
vkGetImageMemoryRequirements with the same image"
This is invalid usage but adding a check in the driver is safe and
might avoid spurious failures.
This is a workaround for the inventory GPU hang with Cyberpunk 2077
which is actually a game bug. Luckily the game handles this error
gracefully.
Since the addrlib change from March, addrlib now selects a better
swizzle mode (4KB instead of 64KB) which reduces image size. Though,
the game assumes that an image with 2 mips is always smaller than the
same image but with 6 mips. This is not always true if the swizzle mode
is different. Then, it creates a D312 heap that is too small for the 2
mips image and the GPU hang with a memory violation, ugh...
Note that next vkd3d-proton release should also reject this but
fixing both sides is fine.
Cc: 21.1 mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4823
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4593
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11448>
Pierre-Eric Pelloux-Prayer [Mon, 14 Jun 2021 07:53:45 +0000 (09:53 +0200)]
radeonsi: skip instance_count==0 draws on <= GFX9
This changes seems to prevent a hang, at least on Renoir chips.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4866
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11356>
Vinson Lee [Mon, 14 Jun 2021 00:09:46 +0000 (17:09 -0700)]
nvc0/ir: Initialize Limits members in constructor.
Fix defect reported by Coverity Scan.
Uninitialized scalar field (UNINIT_CTOR)
uninit_member: Non-static class member min is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member max is not initialized in this constructor nor in any functions that it calls.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11351>
Vinson Lee [Sun, 13 Jun 2021 05:50:32 +0000 (22:50 -0700)]
intel/vec4: Add missing break statement.
Fix defect reported by Coverity Scan.
Missing break in switch (MISSING_BREAK)
unterminated_case: The case for value
VEC4_OPCODE_ZERO_OOB_PUSH_REGS is not terminated by a break
statement.
Fixes:
89fd196f6b5 ("intel/vec4: Add support for masking pushed data")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11347>
Emma Anholt [Tue, 18 May 2021 23:04:47 +0000 (16:04 -0700)]
i915g: Switch to using nir-to-tgsi.
This fixes ~10% of the GLES2 failures thanks to having a better compiler,
though in some cases we get some new compile fails due to instr count or
uniform count. We still have to do NIR-to-TGSI because the NIR gallivm
draw path isn't ready for non-native-integer NIR code, and st/mesa treats
native-integer as a screen property instead of a stage property.
Other than the noted regressions in the xfails, for
dEQP-GLES2.functional.uniform_api.random.74: compile fail changes reasons
triggering an aassertion instead of drawing magenta.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
Emma Anholt [Sun, 13 Jun 2021 16:39:23 +0000 (09:39 -0700)]
i915g: Handle fragment depth being in OUT[1] not OUT[0].
Prevents regressions when switching to nir-to-tgsi which orders the
outputs differently.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
Emma Anholt [Sun, 13 Jun 2021 15:07:14 +0000 (08:07 -0700)]
nir_to_tgsi: Support integer sysvals on !CAP_INTEGERS hardware.
glsl_to_tgsi does the same thing, needed for the draw path on i915g.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
Emma Anholt [Thu, 3 Jun 2021 23:20:12 +0000 (16:20 -0700)]
nir_to_tgsi: Fix internal handling of NIR uints for !CAP_INTEGERS
If we called nir_lower_int_to_float(), then ALU-consumed ints got turned
into floats and we have to interpret them that way.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
Eric Anholt [Wed, 12 Aug 2020 18:17:28 +0000 (11:17 -0700)]
nir: Do peephole select on other instructions if the limit is ~0.
limit==0 is the signal for "don't peephole anything but a move that will
be optimized aways." limit > 0 is "up to N alu instructions may be moved
out." nir-to-tgsi uses ~0 as the indicator of "No, we really need to
eliminate all if instructions" on hardware like i915 that doesn't have
control flow.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
Emma Anholt [Thu, 3 Jun 2021 18:10:48 +0000 (11:10 -0700)]
nir/lower_int_to_float: Make sure the cursor is in the right spot.
We need to make get it updated after we may have nir_instr_remove()d an
instruction, and when we cross blocks. This didn't really matter before
because the only builder usage was idiv, which other users of
lower_int_to_float were probably never hitting.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
Emma Anholt [Mon, 7 Jun 2021 22:09:33 +0000 (15:09 -0700)]
i915g: Allow fragment coord conventions TGSI properties to be set.
The frontend lowering handles normalizing the conventions to the only
model we support, we just need to ignore the property in the TGSI.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
Emma Anholt [Mon, 7 Jun 2021 18:32:08 +0000 (11:32 -0700)]
i915: Drop assertion failure about seeing each const decled once.
nir_to_tgsi sometimes emits multiple decls currently, but we don't
actually care because we're just checking which ones are live.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
Emma Anholt [Tue, 8 Jun 2021 19:05:42 +0000 (12:05 -0700)]
i915: Disable vertex texturing and delete the code.
It's not a required feature of the GL2.1 or GLES2, and you really don't
want to be doing SW VS access of the write-combined texture data. Also,
avoids memory corruption in deqp:
Test case 'dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_nearest_linear_repeat'..
Mesa: User error: GL_INVALID_ENUM in glGetIntegerv(pname=GL_MAJOR_VERSION)
Fail (Image comparison failed)
Test case 'dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_equal_depth_always'..
==559181== Invalid read of size 4
==559181== at 0x641E8D0: i915_drm_buffer_unmap (i915_drm_buffer.c:204)
==559181== by 0x64151EB: i915_cleanup_vertex_sampling (i915_state.c:449)
==559181== by 0x640AEA7: i915_draw_vbo (i915_context.c:134)
==559181== by 0x640AEA7: i915_draw_vbo (i915_context.c:55)
==559181== by 0x61367B1: cso_draw_vbo (cso_context.c:1524)
[...]
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
Yiwei Zhang [Wed, 9 Jun 2021 22:23:24 +0000 (22:23 +0000)]
anv: enable multi-planar support for drm format modifier
This patch only enables the below VkFormat:
- VK_FORMAT_G8_B8R8_2PLANE_420_UNORM
This patch ensures the proper behavior of the below APIs:
- vkGetPhysicalDeviceFormatProperties2
- vkGetPhysicalDeviceImageFormatProperties2
- vkCreateImage
- vkGetImageSubresourceLayout
- vkGetImageDrmFormatModifierPropertiesEXT
- vkGetImageMemoryRequirements
- vkGetImageMemoryRequirements2
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chad@kiwitree.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11281>
Yiwei Zhang [Wed, 9 Jun 2021 00:53:55 +0000 (00:53 +0000)]
anv: support multi-planar format in add_all_surfaces_explicit_layout
Add initial multi-planar format support on the images with modifiers:
- With aux usage,
- Format plane count must be 1.
- Memory plane count must be 2.
- Without aux usage,
- Each format plane must map to a distinct memory plane.
For the other cases, currently there is no way to properly map memory
planes to format planes and aux planes due to the lack of defined ABI
for external multi-planar images.
This patch doesn't include some potentially supported cases like all
format planes mapping to a single memory plane, additional refactoring
is needed to workaround explicit base offset + ANV_OFFSET_IMPLICIT.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chad@kiwitree.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11281>
Yiwei Zhang [Wed, 16 Jun 2021 20:53:47 +0000 (20:53 +0000)]
anv: fix some log formats
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chad@kiwitree.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11281>
Emma Anholt [Thu, 17 Jun 2021 23:03:31 +0000 (16:03 -0700)]
freedreno: Add some cheza flakes from the last week.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11453>
Emma Anholt [Thu, 17 Jun 2021 20:24:45 +0000 (13:24 -0700)]
freedreno: Skip staging blits from uninitialized resources.
When storing depth- or stencil-only texture data that has been packed into
a depth/stencil texture, the tex store gets PIPE_MAP_READ added onto it
since the other channel will get ORed into the incoming data, but
sometimes we know that the other component is undefined because the whole
texture is either fresh or just invalidated.
Cleans up a confusing extra blit in a dEQP case I've been debugging, and
should be less work for dEQP CI.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11452>
Emma Anholt [Thu, 17 Jun 2021 19:06:25 +0000 (12:06 -0700)]
freedreno: Add more detailed blit debug in FD_MESA_DEBUG=msgs.
For debugging the batch cache, it really helps to see the blits that
happen, and which are staging blits in the transfer map process.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11452>
Emma Anholt [Thu, 17 Jun 2021 19:57:31 +0000 (12:57 -0700)]
freedreno/fdl: Give the tiling mode a nice name in debug dumps.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11452>