Fabien Parent [Tue, 29 Nov 2016 13:31:31 +0000 (14:31 +0100)]
davinci: omapl138_lcdk: use correct name for CONFIG_SYS_NAND_MASK_CLE
CONFIG_SYS_CLE_MASK is not used anywhere. It has probably been
renamed to CONFIG_SYS_NAND_MASK_CLE. Rename it and remove the former
from the config_whitelist.txt file.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Fabien Parent [Tue, 29 Nov 2016 13:31:30 +0000 (14:31 +0100)]
davinci: omapl138_lcdk: use correct define for 16 bit NAND chips
The omapl138_lcdk header defines CONFIG_SYS_NAND_BUSWIDTH_16_BIT while
the correct name is CONFIG_SYS_NAND_BUSWIDTH_16BIT.
While renaming the only occurrence of CONFIG_SYS_NAND_BUSWIDTH_16_BIT,
let's also remove it from the config_whitelist.txt file.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Fabien Parent [Tue, 29 Nov 2016 13:31:29 +0000 (14:31 +0100)]
NAND: davinci: add support for NAND chips with 16 bits bus
The OMAPL138-LCD board uses a NAND chip with a 16 bits bus. Add
support into the davinci driver for 16 bit bus NAND chips.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Fabien Parent [Tue, 29 Nov 2016 13:23:41 +0000 (14:23 +0100)]
davinci: omapl138_lcdk: add u-boot sector for mmc/sd boot
Set the correct CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR value in order
to be able to boot from MMC/SD.
The SPL is stored at sector 0x75, while u-boot will follow at
sector 0xb5.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Fabien Parent [Tue, 29 Nov 2016 13:23:40 +0000 (14:23 +0100)]
davinci: da850evm: fix empty boot method list in the SPL
The list of available boot method is not part of the binary which
prevent the SPL from booting u-boot or Linux.
Add the missing .u_boot_list* sections to the binary to fix it.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Fabien Parent [Tue, 29 Nov 2016 13:23:39 +0000 (14:23 +0100)]
davinci: omapl138_lcdk: configure ddr2
The SPL is unable to load u-boot because the DDR2 is not configured.
Configure the DDR2.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Fabien Parent [Tue, 29 Nov 2016 13:23:38 +0000 (14:23 +0100)]
davinci: omapl138_lcdk: configure pll0
The SPL is not able to boot properly because the PLL0 is not
configured. Configure it.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Fabien Parent [Tue, 29 Nov 2016 13:23:37 +0000 (14:23 +0100)]
ARM: davinci: Move CONFIG_SYS_DA850_DDR_INIT to Kconfig
Clean config headers by moving CONFIG_SYS_DA850_DDR_INIT away to a
Kconfig file.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Fabien Parent [Tue, 29 Nov 2016 13:23:36 +0000 (14:23 +0100)]
ARM: davinci: Move CONFIG_SYS_DA850_PLL_INIT to Kconfig
Clean config headers by moving CONFIG_SYS_DA850_PLL_INIT away to a
Kconfig file.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Tue, 29 Nov 2016 09:52:00 +0000 (15:22 +0530)]
ARM: DRA7x/AM57xx: Get rid of CONFIG_AM57XX
CONFIG_AM57XX is just an unnecessary macro that is redundant given So,
remove the same instead of spreading through out the u-boot source
code and getting in the way to maintain common code for DRA7x family.
Acked-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Tue, 29 Nov 2016 09:51:59 +0000 (15:21 +0530)]
usb: xhci: Remove assumption of DWC instance based on DRA7 SoC type
Both AM57xx and DRA7xx share the same set of base addresses for DWC
controllers. The usage however differ with DWC2 instance used typically
in AM57xx evms while DWC1 instances used in DRA7x platforms.
Use TARGET_SOC config to differentiate so that CONFIG_AM57XX can be dropped.
Eventually, this needs to be dt-fied.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Tue, 29 Nov 2016 06:37:50 +0000 (12:07 +0530)]
ARM: K2G: DDR3: Fix up priv ID for MPU
For ECC enabled DDR, we use EDMA to reset all memory values to 0. For
K2E/L/H/K the priv ID of 8 was indicative of ARM, but that is not the
case for K2G, where it is 1.
Unfortunately, ddr3 code had hard coded the privID and had missed
identification previously. Fix the same, else unforeseen behavior can
be expected in our reset of DDR contents to 0 for ECC enablement.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Tue, 29 Nov 2016 06:28:03 +0000 (11:58 +0530)]
ARM: AMx3xx: Make FIT boot as default boot on HS devices
Verification has to be done before booting any images on HS devices. So
default the boot to FIT on HS devices.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Tue, 29 Nov 2016 06:28:02 +0000 (11:58 +0530)]
ARM: AM57xx: Make FIT boot as default boot on HS devices
Verification has to be done before booting any images on HS devices. So
default the boot to FIT on HS devices.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Tue, 29 Nov 2016 06:28:01 +0000 (11:58 +0530)]
ARM: DRA7: Make FIT boot as default boot on HS devices
Verification has to be done before booting any images on HS devices. So
default the boot to FIT on HS devices.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Tue, 29 Nov 2016 06:28:00 +0000 (11:58 +0530)]
ti_armv7_common: env: Add support for loading FIT images
FIT is a new image format which is a Tree like structure and gives more
flexibility in handling of various images. Mainly used for unification of
multiple images in a single blob and provide security information for each
image.
U-Boot already has support for loading such images, so adding the environment
support to load FIT image on all TI platforms.
Reviewed-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Tue, 29 Nov 2016 06:27:59 +0000 (11:57 +0530)]
ti_armv7_common: env: Consolidate support for loading images from mmc
Support for loading images from mmc is duplicated in all TI platforms.
Add this information to DEFAULT_MMC_TI_ARGS so that it can be reused
in all TI platforms.
Reviewed-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Madan Srinivas [Tue, 29 Nov 2016 06:19:15 +0000 (11:49 +0530)]
configs: am43x: hs: Modify SPL load address to fix UART boot issue
An issue in the TI secure image generation tool causes the ROM to
load the SPL at a different load address than what is specified by
CONFIG_ISW_ENTRY_ADDR while doing a peripheral boot.
This causes the SPL to fail on secure devices during peripheral
boot.
The TI secure image generation tool has been fixed so that the SPL
will always be loaded at 0x403018E0 by the ROM code for both
peripheral and memory boot modes. am43x hs defconfig file have been
updated to reflect this change.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:36 +0000 (00:15 +0200)]
r2dplus: fixup CONFIG_SYS_TEXT_BASE to account arch/sh changes
This change allows to reserve enough space at the end of board SDRAM
to store two copies of U-Boot and malloc heap.
Due to selection of the CONFIG_SYS_TEXT_BASE the second code/data
copying is not avoided, first of all this may depend on a used
toolchain, secondly at this point some level of volatility is wanted
to do more platform changes and do not care about probably changed
calculated in runtime relocation offset.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:35 +0000 (00:15 +0200)]
sh: generate position independent code for all platforms
Finally add fpic compilation option to produce relocatable code.
Note that this requires to define CONFIG_NEEDS_MANUAL_RELOC for all
board files, also relocation support still has some limitations
(e.g. a developer should care not to overwrite the executing code or
memset() with zeroes not yet relocated data on malloc init etc.),
which may be fixed while switching to PIE.
Due to short investigation the architecture code is not ready for PIE
linking, this will require some manipulations with .dyn* sections.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:34 +0000 (00:15 +0200)]
sh: share the correct version of start.S among all cpus
It is easy to note that SH2/SH3/SH4 start.S code is practically
the same with a minor difference for SH2 where a short data header is
present. To avoid unwanted code duplication and to automatically
convert SH2 and SH3 platforms to generic board support move fixed SH4
start.S into arch/sh/lib/start.S and share it among all platforms.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:33 +0000 (00:15 +0200)]
sh4: fix start.S by calling board_init_f() after first code relocation
Like on ARM platform keep the first code relocation from a U-boot
image storage to RAM at CONFIG_SYS_TEXT_BASE, then pass execution to a
generic board_init_f() with empty GD flags. If CONFIG_SYS_TEXT_BASE is
equal to a calculated by board_init_f() relocation address there will
be no more code and data copy, however it's worth to mention that the
first copy happens even if $pc on _start is the same as
CONFIG_SYS_TEXT_BASE, on practice this works without a problem.
Also note that _sh_start is renamed back to _start to correct
gd->mon_len calculation by setup_mon_len(), the opposite rename was
done in pre-generic board commit
2024b968ee9 ("sh: Fix build in start.S").
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:32 +0000 (00:15 +0200)]
sh: add shared relocate_code() function and call board_init_r()
Commits
b61e90e6fd83 ("sh: Drop the arch-specific board init") and
f41e6088eb1a ("sh: Fix build errors for generic board") left code and
data relocation done in start.S, however further actual U-boot
configuration is not started anymore. Practically SH boards with the
code relocated into the expected position by start.S still can be
booted, so the change adds this option and provides an option how to
relocate code for board_init_r() execution.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:31 +0000 (00:15 +0200)]
sh: add common dram_init() function for all boards
Generic board support assumes a different method of specifying
DRAM size on board, also it can be shared among all boards, notably
only sh7763rdp board has a custom legacy dram_init(), however
the difference is only in printing some additional information,
this feature can be removed.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:30 +0000 (00:15 +0200)]
sh: define CONFIG_DISPLAY_BOARDINFO to print board information
All SH boards define a checkboard() function which outputs basic board
information on boot, however generic board support requires to define
CONFIG_DISPLAY_BOARDINFO to do that, so define it for the boards.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:29 +0000 (00:15 +0200)]
sh: remove undefined DEBUG preprocessor token from board config files
By default this undef is a noop, moreover at this point when the
platform support is broken is prevents debugging of U-boot by manual
insertion of #define DEBUG into common files, so it makes sense to
remove the option from all SH boards as a harmful one.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:28 +0000 (00:15 +0200)]
sh: add MEMORY command to a shared linker script
At the moment in runtime all defined sections are copied into or
created in RAM, specify this explicitly to assert potential out of RAM
placements of the sections.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:27 +0000 (00:15 +0200)]
sh: define entry point and reloc_dst inside a linker script
No functional change, concentrate linker script commands in one
place for convenience. Entry point is set to CONFIG_SYS_TEXT_BASE by
default on build, so this option can be omitted from being added to
the linker script.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:26 +0000 (00:15 +0200)]
sh: place board lowlevel_init code in the beginning of .text
Reference lowlevel_init of all supported SH2A/SH3/SH4/SH4A boards
from a shared linker script, the lowlevel_init function will be called
by a relative address.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:25 +0000 (00:15 +0200)]
sh4: use single u-boot linker script for all boards
Three supported SH4/SH4A boards with the bootloader image stored on
SPI flash have own flavour of a linker script, in turn they are equal
among each other. The only difference is that the text from
lowlevel_init.o is placed right after start.o, which makes sense.
Note that .bss section is not marked as NOLOAD, because for about
10 years this is a default option of a GNU linker, either the
attribute is found or not the resulting image file is the same.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:24 +0000 (00:15 +0200)]
common: sh: add necessary define bits to board_f
Since a platform conversion to generic board support has not been
accomplished some architecture specific bits are missing from board_f
init sequence, the change adds a number of basic expected callbacks
into early init sequence.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:23 +0000 (00:15 +0200)]
r2dplus: select rtl8139 driver in defconfig
CONFIG_RTL8139 was moved to a board defconfig by a commit
86e9dc86b1a2
("net: Move CONFIG_RTL8139 to Kconfig"), however it was done
incorrectly due to a missing CONFIG_NETDEVICES selection, thus
virtually it was just a removal of the driver compilation.
As an unlucky consequence the option was completely removed by a purge
commit
adad96e60d0e ("configs: Re-sync HUSH options"), restore the
driver inclusion back.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:22 +0000 (00:15 +0200)]
r2dplus: use P1 area space for text base and PCI system memory
While both options are acceptable use P1 area physical addresses
instead of external memory space of text base and PCI system memory
for unification purposes, all other supported superh boards have the
same selection.
This allows to easily ensure that CONFIG_SYS_TEXT_BASE is located
within available DRAM.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:21 +0000 (00:15 +0200)]
sh4: remove __io config options from r2dplus and r7780mp boards
Defined __io is no-op for the SH architecture and it can be removed
from board files without any functional change.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:20 +0000 (00:15 +0200)]
pci: sh7751: map PCI memory space into SDRAM
For ease of use and accounting a condition that on SH4
pci_phys_to_bus() and pci_bus_to_phys() are one in one mappings due to
unimplemented __iomem() conversion, this change fixes access to SDRAM
memory by PCI devices.
This change also generalizes PCI system memory configuration, which is
taken from board specific defines rather than hardcoded in the PCI
host driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:19 +0000 (00:15 +0200)]
pci: sh7751: fix up PCI I/O space address
The change actually maps PCI I/O window to the same address on PCI bus
as it is stated by a comment, before the change transfers to the PCI I/O
space are failed due to misconfiguration of the most significant 14 bits
of the PCI address in PCIIOBR (note that it is set to 0x0).
Most probably the problem remained unnoticed, because communcation
to all tested PCI devices is done over PCI memory space only.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:18 +0000 (00:15 +0200)]
sh4: cache: move exported cache manipulation functions into cache.c
No functional change, moving cache manipulation functions into cache.c
allows to collect all of them in a single location and as a pleasant
side effect cache_control() function can be unexported now.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:17 +0000 (00:15 +0200)]
sh: cache: don't modify CCR from P1 area
cache_wback_all() is a local function and it is called from
cache_control() only, which is in turn jumps to P2 area.
The change fixes an issue when cache_wback_all() returns from P2 to
P1, however cache_control() continues to manipulate with CCR
register, according to the User's Manual this is restricted.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:16 +0000 (00:15 +0200)]
sh: cache use jump_to_P2() and back_to_P1() from asm/system.h
Both jump_to_P2() and back_to_P1() functions are found in asm/system.h
header file and functionally they are the same, don't redefine them.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:15 +0000 (00:15 +0200)]
sh3: remove unused cache.c file from being built
The change is similar to commit
994b56616bae ("sh: delete an unused
source file") for SH2, however here the removed cache.c file was
built and included into an image as a dead code.
If it is needed in future the contents can be reused from a similar
arch/sh/cpu/sh4/cache.c file, which is in turn will be moved to
a shared among all core flavours location at arch/sh/lib/cache.c.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:14 +0000 (00:15 +0200)]
sh4: cache: correct flush_cache() to writeback and invalidate
In common usecases flush_cache() assumes both cache invalidation and
write-back to memory, instead of doing cache invalidation only with
the wrapped 'ocbi' instruction pin flush_cache() to cache invalidation
with memory write-back done by 'ocbp'.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vladimir Zapolskiy [Sun, 27 Nov 2016 22:15:13 +0000 (00:15 +0200)]
sh4: cache: correct dcache flush to invalidate with write-back
In common usecases flush_cache() assumes both cache invalidation and
write-back to memory, thus in flush_dcache_range() implementation
change SH4 cache write-back only instruction 'ocbwb' with cache purge
instruction 'ocbp', according to the User's Manual there should be no
performance penalty for that.
Note that under circumstances only cache invalidation is expected from
flush_cache() call, in these occasional cases the current version of
flush_cache() works, which is a wrapper over invalidate_dcache_range()
at the moment, this will be fixed in the following change.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Jonathan Gray [Sat, 26 Nov 2016 04:18:00 +0000 (15:18 +1100)]
compiler.h: use u-boot endian macros on OpenBSD
When building u-boot on sparc64 and powerpc hosts it became clear that
u-boot expects endian conversion defines to be macros:
lib/crc32.c:87: error: braced-group within expression allowed only inside a function
For OpenBSD switch from using system definitions equivalent to the u-boot ones
and define glibc __BYTE_ORDER __BIG_ENDIAN __LITTLE_ENDIAN names, as at least
some parts of the non-cross build assumes those names are present (ie crc32.c).
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Sekhar Nori [Fri, 25 Nov 2016 08:55:55 +0000 (14:25 +0530)]
ARM: am57xx_evm: enable DFU support
AM57xx GP EVM has USB2 port of the SoC exposed as
USB client port.
It is useful to be able to use this port for USB
DFU downloads.
Enable USB DFU support. Tested on AM57x GP EVM Rev
A3 using DFU to download to connected SD card.
configs for HS version of the AM57x EVM are
included in the patch but not really tested.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Sekhar Nori [Fri, 25 Nov 2016 08:55:54 +0000 (14:25 +0530)]
ARM: ti: consolidate dfu environment variables
Introduce include/environment/ti/dfu.h that
consolidates environment variable definitions
for various TI boards that support DFU today.
Tested on AM335x EVM, AM437x SK EVM and DRA74x
EVM by using DFU to write to SD card.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Michal Simek [Wed, 30 Nov 2016 11:18:36 +0000 (12:18 +0100)]
cmd: scsi: Make private functions static
Two functions should be static because they are not exported to any
other file.
Warnings were reported by sparse C=1.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Wed, 30 Nov 2016 11:50:58 +0000 (12:50 +0100)]
scsi: Separate SCSI private block description initialization
When blk_create_device() is called some parameters in blk_desc are
automatically filled. Separate SCSI private initialization and SCSI full
block device initialization not to rewrite already prepared data.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Wed, 30 Nov 2016 11:12:31 +0000 (12:12 +0100)]
scsi: Change scsi_scan() to be able to return value
With DM_SCSI this function will return more than one return value to
cover errors.
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Wed, 30 Nov 2016 10:53:43 +0000 (11:53 +0100)]
scsi: Make private functions static
Several functions should be static because they are not exported to any
other file.
Warnings were reported by sparse C=1.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Wed, 30 Nov 2016 10:54:52 +0000 (11:54 +0100)]
scsi: Remove completely unused functions
These functions are not called for any location.
This patch removes them scsi_trim_trail(), scsi_get_disk_count()
and scsi_setup_read6().
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Fri, 18 Nov 2016 15:22:42 +0000 (16:22 +0100)]
scsi: Simplify scsi_read/scsi_write()
There is no reason to directly point to static allocated array
when we have proper block_dev pointer available via parameter
in !CONFIG_BLK. For CONFIG_BLK this is read directly from uclass
platdata.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Fri, 18 Nov 2016 15:14:24 +0000 (16:14 +0100)]
scsi: Move pccb buffer initalization directly to scsi_detect_dev
pccb is pointer to temporary buffer which is used only for sending
command. Make it local as is done in scsi_read/scsi_write.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Fri, 18 Nov 2016 14:52:51 +0000 (15:52 +0100)]
scsi: Take lun from device block description
Prepare LUN(Logical unit number) directly in block description structure
and reuse it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Fri, 18 Nov 2016 14:42:13 +0000 (15:42 +0100)]
scsi: Extract device detection algorithm
The patch enables running detection algorithm on block device
description structure.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Fri, 18 Nov 2016 14:27:00 +0000 (15:27 +0100)]
scsi: Extract block device initialization
Extract block device initialization to specific function.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Wed, 16 Nov 2016 07:41:01 +0000 (08:41 +0100)]
common: miiphyutil: Work and report phy address in hex in mdio cmd
It is confusing that mdio commands work and report phy id as
decimal value when mii is working with hex values.
For example:
ZynqMP> mdio list
gem:
21 - TI DP83867 <--> ethernet@
ff0e0000
ZynqMP> mdio read ethernet@
ff0e0000 0
Reading from bus gem
PHY at address 21:
0 - 0x1140
ZynqMP> mii dump 21 0
Incorrect PHY address. Range should be 0-31
...
ZynqMP> mii dump 15
0. (1140) -- PHY control register --
(8000:0000) 0.15 = 0 reset
U-Boot normally takes hex values that's why this patch is changing mdio
command to handle hex instead of changing mii command to handle decimal
values.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Siva Durga Prasad Paladugu [Fri, 7 Oct 2016 05:41:52 +0000 (11:11 +0530)]
ARM: zynq: Enable SD1 and qspi for picozed board
Enable SD1 and qspi for picozed board.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Masahiro Yamada [Thu, 13 Oct 2016 15:40:00 +0000 (00:40 +0900)]
ARM: zynq(mp): remove unneeded CONFIG_USB_MAX_CONTROLLER_COUNT defines
ARCH_ZYNQ(MP) selects DM_USB, where CONFIG_USB_MAX_CONTROLLER_COUNT
is not used.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Moritz Fischer <moritz.fischer@ettus.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 26 Oct 2016 07:24:32 +0000 (09:24 +0200)]
ARM64: zynqmp: List secondary software boot modes
Using alternative bootmode field to support automatic secondary boot
modes. It is purely software setting where SW modes are using free
bootmode combinations.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 29 Nov 2016 11:03:51 +0000 (12:03 +0100)]
ARM64: zynqmp: Use DTS name for different psu_init_gpl* files in SPL
CONFIG_SYS_CONFIG_NAME is not proper config option for different low
level init files because different board revisions requires different
psu_init_gpl* files.
Also at the end of moving drivers to DM all board specific configuration
files should be removed.
The same changes was done for Zynq.
"ARM: zynq: Simplify zynq configuration"
(sha1:
ad5b5801264e573bfbf17a20b04c546985c5bfc1)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 30 Aug 2016 14:17:27 +0000 (16:17 +0200)]
ARM64: zynqmp: Force certain bootmode for SPL
ZynqMP provides an option to overwrite bootmode setting which
can change SPL behavior.
For example: boot SPL via JTAG and then SPL loads images from SD.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tom Rini [Thu, 1 Dec 2016 14:24:02 +0000 (09:24 -0500)]
Merge git://www.denx.de/git/u-boot-marvell
Chris Packham [Wed, 9 Nov 2016 09:21:45 +0000 (22:21 +1300)]
tools/kwbimage: add DEBUG option
Offset 0x1 in the generated kwb image file is a set of flags, bit 0
enables debug output from the BootROM firmware. Allow a DEBUG option in
the kwb configuration to request debug output from the BootROM firmware.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Wed, 9 Nov 2016 09:07:45 +0000 (22:07 +1300)]
tools/kwbimage: add BAUDRATE option
Offset 0x18 in some Marvell datasheets this field is redacted as
"reserved". This offset is actually a set of options and bits 2:0 allow
the selection of the UART baudrate.
Allow a BAUDRATE option to set the UART baudrate for any messages coming
from the BootROM firmware.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Wed, 26 Oct 2016 01:08:30 +0000 (14:08 +1300)]
arm: mvebu: move SYS_MVEBU_PLL_CLOCK to Kconfig
The main PLL frequency is 2GHz for Armada-XP and 1GHZ for Armada 375,
38x and 39x.
[ Linux commit
ae142bd9976532aa5232ab0b00e621690d8bfe6a ]
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Mon, 24 Oct 2016 22:40:55 +0000 (11:40 +1300)]
mvebu: db-88f6820-amc: Enable FIT support
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Vasut [Thu, 1 Dec 2016 01:06:35 +0000 (02:06 +0100)]
SPL: mmc: Make spl_mmc_load_image available
Make the spl_mmc_load_image() available globally, so it can be
invoked directly by SPL on extremely space-constrained systems.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Marek Vasut [Thu, 1 Dec 2016 01:06:33 +0000 (02:06 +0100)]
mmc: Tinification of the mmc code
Add new configuration option CONFIG_MMC_TINY which strips away all
memory allocation within the MMC code and code for handling multiple
cards. This allows extremely space-constrained SPL code use the MMC
framework.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Marek Vasut [Thu, 1 Dec 2016 01:06:32 +0000 (02:06 +0100)]
mmc: Fix warning if debug() is not used
If debug() is not used, then the whole content of debug(...) will
be removed by the preprocessor, which will result in the following
warning. This patch adds __maybe_unused annotation to fix this.
drivers/mmc/mmc.c: In function ‘mmc_init’:
drivers/mmc/mmc.c:1685:11: warning: variable ‘start’ set but not used [-Wunused-but-set-variable]
unsigned start;
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Tomas Melin [Fri, 25 Nov 2016 09:01:03 +0000 (11:01 +0200)]
mmc: add bkops-enable command
Add new command that provides possibility to enable the
background operations handshake functionality
(BKOPS_EN, EXT_CSD byte [163]) on eMMC devices.
This is an optional feature of eMMCs, the setting is write-once.
The command must be explicitly taken into use with
CONFIG_CMD_BKOPS_ENABLE.
Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
Seung-Woo Kim [Thu, 24 Nov 2016 06:05:51 +0000 (15:05 +0900)]
mmc: s5p_sdhci: fix to check proper pinmux id
At sdhci_get_config(), there was wrong condition to check pimux
id, so this patch fixes to check proper pinmux id.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Tom Rini [Wed, 30 Nov 2016 19:14:47 +0000 (14:14 -0500)]
ts4600: Disable CONFIG_DISPLAY_CPUINFO
Without this change we see:
../arch/arm/cpu/arm926ejs/mxs/mxs.c: In function ‘print_cpuinfo’:
../arch/arm/cpu/arm926ejs/mxs/mxs.c:181:23: warning: unused variable ‘data’ [-Wunused-variable]
../arch/arm/cpu/arm926ejs/mxs/mxs.c:180:6: warning: variable ‘cpurev’ set but not used [-Wunused-but-set-variable]
So the easy solution is to disable CONFIG_DISPLAY_CPUINFO
Reviewed-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 30 Nov 2016 19:08:28 +0000 (14:08 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-mips
Tom Rini [Wed, 30 Nov 2016 19:05:08 +0000 (14:05 -0500)]
travis.yml: Split Freescale ARM job up more
In order to avoid running into the time limit, split the 32bit and 64bit
Freescale boards into separate jobs. We could either pass
"freescale & armv8" to buildman or exclude all of the 32bit CPUs. While
the former is shorter I fear the amount of possible escaping required
would make things less readable.
Signed-off-by: Tom Rini <trini@konsulko.com>
Paul Burton [Mon, 26 Sep 2016 18:28:57 +0000 (19:28 +0100)]
MIPS: Fix map_physmem for cached mappings
map_physmem should return a pointer that can be used by the CPU to
access the given memory - on MIPS simply returning the physical address
as it does prior to this patch doesn't achieve that. Instead return a
pointer to the memory within (c)kseg0, which matches up consistently
with the (c)kseg1 pointer that uncached mappings return via ioremap.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Mon, 26 Sep 2016 18:28:56 +0000 (19:28 +0100)]
MIPS: Use ram_top, not bi_memsize, in arch_lmb_reserve
When calculating the region to reserve for the stack in
arch_lmb_reserve, make use of ram_top instead of adding bi_memsize to
CONFIG_SYS_SDRAM_BASE. This avoids overflow if the system has enough
memory to reach the end of the address space.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Marek Vasut [Fri, 25 Nov 2016 22:32:22 +0000 (23:32 +0100)]
mips: Let cache.h be included from assembly source
Add ifdef __ASSEMBLY__ around the function prototype to let cache.h
be included from assembly code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Daniel Schwierzeck [Sat, 9 Jan 2016 17:34:15 +0000 (18:34 +0100)]
common/board_f: enable initr_trap for MIPS
Enable initr_trap hook also for MIPS to install and enable
U-Boot's specific MIPS exception handlers.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Daniel Schwierzeck [Sat, 9 Jan 2016 17:34:14 +0000 (18:34 +0100)]
MIPS: add handling for generic and EJTAG exceptions
Add exception handlers for generic and EJTAG exceptions. Most of
the assembly code is imported from Linux kernel and adapted to U-Boot.
The exception vector table will be reserved above the stack before
U-Boot is relocated. The exception handlers will be installed and
activated after relocation in the initr_traps hook function.
Generic exceptions are handled by showing a CPU register dump similar
to Linux kernel. For example:
malta # md 1
00000001:
Ooops:
$ 0 :
00000000 00000000 00000009 00000004
$ 4 :
8ff7e108 00000000 0000003a 00000000
$ 8 :
00000008 00000001 8ff7cd18 00000004
$12 :
00000002 00000000 00000005 0000003a
$16 :
00000004 00000040 00000001 00000001
$20 :
00000000 8fff53c0 00000008 00000004
$24 :
ffffffff 8ffdea44
$28 :
90001650 8ff7cd00 00000004 8ffe6818
Hi :
00000000
Lo :
00000004
epc :
8ffe6848 (text
bfc28848)
ra :
8ffe6818 (text
bfc28818)
Status:
00000006
Cause :
00000410 (ExcCode 04)
BadVA :
8ff9e928
PrId :
00019300
### ERROR ### Please RESET the board ###
EJTAG exceptions are checked for SDBBP and delegated to the SDBBP handler
if necessary. Otherwise the debug mode will simply be exited. The SDBBP
handler currently prints the contents of registers c0_depc and c0_debug.
This could be extended in the future to handle semi-hosting according to
the MIPS UHI specification.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Tested-by: Paul Burton <paul.burton@imgtec.com>
Daniel Schwierzeck [Sat, 9 Jan 2016 17:34:14 +0000 (18:34 +0100)]
MIPS: reserve space for exception vectors
In order to set own exception handlers, a table with the exception
vectors must be built in DRAM and the CPU EBase register must be
set to the base address of this table.
Reserve the space above the stack and use gd->irq_sp as storage
for the exception base address.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Daniel Schwierzeck [Sat, 9 Jan 2016 17:34:14 +0000 (18:34 +0100)]
MIPS: add asm-offsets for struct pt_regs
Import asm-offsets.c from kernel to generate offset for struct pt_regs
needed by exception handlers.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Daniel Schwierzeck [Sat, 4 Jun 2016 14:13:21 +0000 (16:13 +0200)]
MIPS: add possibility to setup initial stack and global data in SRAM
This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which
a SoC can select if it supports some kind of SRAM. Together with
CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be
set up in that SRAM. This can be used to provide a C environment
also for lowlevel_init().
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Daniel Schwierzeck [Sun, 25 Sep 2016 16:36:38 +0000 (18:36 +0200)]
MIPS: factor out code for initial stack and global data
Move the code for setting up the initial stack and global data
to a macro to be able to use it more than once.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Daniel Schwierzeck [Sun, 7 Feb 2016 23:37:59 +0000 (00:37 +0100)]
MIPS: fix iand optimize setup of CP0 registers
Clear cp0 status while preserving implementation specific bits.
Set bits BEV and ERL as the arch specification requires after
a reset or soft-reset exception.
Extend and fix initialization of watch registers. Check if additional
watch register sets are implemented and initialize them too.
Initialize cp0 count as early as possible to get the most
accurate boot timing.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Daniel Schwierzeck [Sun, 7 Feb 2016 18:39:58 +0000 (19:39 +0100)]
MIPS: fix ROM exception vectors
When booting from ROM, early exceptions can't be handled
properly. Instead of busy-looping give the developer the
possibilty to examine the situation. Invoke an UHI
exception operation which can be read as unhandled exception
by a hardware debugger if one is attached. If the debugger
doesn't support UHI, the exception is read as unexpected
breakpoint.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Daniel Schwierzeck [Sun, 14 Feb 2016 17:52:57 +0000 (18:52 +0100)]
MIPS: make inclusion of ROM exception vectors configurable
This adds a compile time option to include code for static
exception vectors. Static exception vectors are only needed,
when the U-Boot entry point is equal to the CPU reset exception
vector address. For instance this is the case when U-Boot is
used as ROM in Qemu or booted from parallel NOR flash. When
U-Boot is booted from RAM (e.g. loaded there by SPL), the
exception vectors need to be setup dynamically, which is done
in follow-up commits.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tom Rini [Wed, 30 Nov 2016 14:57:52 +0000 (09:57 -0500)]
Merge branch 'master' of git://denx.de/git/u-boot-imx
Lukasz Majewski [Mon, 28 Nov 2016 06:18:14 +0000 (07:18 +0100)]
imx6: clock: Enable External Memory Interface [EIM] clock (eim_slow_clock)
This patch extends the imx6 clock code to enable or disable the EIM
slow clock, which in necessary when one wants to use EIM interface t
o read/write from external memory (e.g. NOR).
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Christoph Fritz [Tue, 29 Nov 2016 15:13:40 +0000 (16:13 +0100)]
mx6sx: Add initial support for Samtec VIN|ING 2000 board
This patch adds initial support for Samtec VIN|ING 2000 board.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Tom Rini [Wed, 30 Nov 2016 00:42:48 +0000 (19:42 -0500)]
Merge git://git.denx.de/u-boot-mpc85xx
Tom Rini [Tue, 29 Nov 2016 17:41:19 +0000 (12:41 -0500)]
travis.yml: Add samsung and rockchip builds
The catch-all job is failing due to time limits depending on factors out
of our control, so move Samsung and Rockchip boards into their own jobs
and then exclude them from the general ARM and AArch64 jobs.
Signed-off-by: Tom Rini <trini@konsulko.com>
Angus Ainslie [Fri, 11 Nov 2016 18:31:39 +0000 (11:31 -0700)]
imx7: SPI: add suport for SPI flash in mikroBUS slot
Enable the escpi3 nets attached to the mikroBUS slot
on the i.MX7 Sabre evalution board. Also enble the SPI flash
commands to work with the "flash click" board.
This is V2 of this patch with changes recommended by the maintainer
CC: Jagan Teki <jteki@openedev.com>
Stefan Agner [Tue, 15 Nov 2016 18:38:23 +0000 (10:38 -0800)]
arm: mx6: specify SPL padding
Specify standard padding for payload to 68KB. This is derived from
the maximum header size plus maximum SPL size. It matches the
already defined offset for SD/eMMC devices (69KB) too. This allows
to use the u-boot-with-spl.imx build target to generate a directly
flashable image which can be flashed using:
dd if=u-boot-with-spl.imx of=/dev/mmcblk0 bs=512 skip=2
While the patch has been created with SD/eMMC in mind, this also
works with other boot media. The board file needs to configure the
media specific (absolute) payload offset accordingly. Especially
the IVT offset is boot media specific and can be retrieved from the
reference manual (Table 8-25. Image Vector Table Offset and Initial
Load Region Size). For NAND boot a define like this should do the
job:
#define CONFIG_SYS_NAND_U_BOOT_OFFS (SPL_PAD_TO + 0x400)
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Breno Lima [Fri, 25 Nov 2016 18:56:57 +0000 (16:56 -0200)]
mx6sx: Add initial support for UDOO Neo Board
UDOO Neo Board is a development board from Seco that has three models:
- UDOO Neo Basic
- UDOO Neo Basic Kick Starter
- UDOO Neo Extended
- UDOO Neo Full
All versions are based on the i.MX6 SoloX processor.
For more details about the UDOO Neo board, please refer to:
http://www.udoo.org/udoo-neo/
This work is based on a previous commit of Francesco Montefoschi
<francesco.monte@gmail.com>:
https://github.com/fmntf/u-boot/commit/
877b71184a5105e708024f232d36aed574961844
Only tested on the UDOO Neo Full board.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Sanchayan Maity [Fri, 25 Nov 2016 10:49:17 +0000 (16:19 +0530)]
colibri_vf: Read kernel and device tree from static UBI volumes
Our update scripts write the kernel and device tree in seperate
UBI volumes. This allows to use a lot less UBI/UBIFS support in
U-Boot, which should lower the risk of hitting bugs in this area.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Sebastien Bourdelin [Tue, 8 Nov 2016 17:18:07 +0000 (12:18 -0500)]
ARM: ts4600: add basic board support
This commit adds basic support including:
MMC, Serial console
Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Ken Lin [Fri, 18 Nov 2016 17:20:54 +0000 (12:20 -0500)]
board: ge: bx50v3: add the PMIC configuration support
Change the PMIC bulk configuration from auto mode to sync mode to avoid
voltage dropout issue seen in auto mode.
Signed-off-by: Ken Lin <ken.lin@advantech.com.tw>
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Eric Nelson [Sun, 30 Oct 2016 23:33:50 +0000 (16:33 -0700)]
ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routines
The DDR calibration routines are gated by conditionals for the
i.MX6DQ SOCs, but with the use of the sysinfo parameter, these
are usable on at least i.MX6SDL and i.MX6SL variants with DDR3.
Also, since only the Novena board currently uses the dynamic
DDR calibration routines, these routines waste space on other
boards using SPL.
Add a KConfig entry to allow boards to selectively include the
DDR calibration routines.
Signed-off-by: Eric Nelson <eric@nelint.com>
Eric Nelson [Sun, 30 Oct 2016 23:33:49 +0000 (16:33 -0700)]
mx6: ddr: add routine to return DDR calibration data
Add routine mmdc_read_calibration() to return the output of DDR
calibration. This can be used for debugging or to aid in construction
of static memory configuration.
This routine will be used in a subsequent patch set adding a virtual
"mx6memcal" board, but could also be useful when gathering statistics
during an initial production run.
Signed-off-by: Eric Nelson <eric@nelint.com>
Eric Nelson [Sun, 30 Oct 2016 23:33:48 +0000 (16:33 -0700)]
mx6: ddr: pass mx6_ddr_sysinfo to calibration routines
The DDR calibration routines have scattered support for bus
widths other than 64-bits:
-- The mmdc_do_write_level_calibration() routine assumes the
presence of PHY1, and
-- The mmdc_do_dqs_calibration() routine tries to determine
whether one or two DDR PHYs are active by reading MDCTL.
Since a caller of these routines must have a valid struct mx6_ddr_sysinfo
for use in calling mx6_dram_cfg(), and the bus width is available in the
"dsize" field, use this structure to inform the calibration routines which
PHYs are active.
This allows the use of the DDR calibration routines on CPU variants
like i.MX6SL that only have a single MMDC port.
Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Marek Vasut <marex@denx.de>