Revert "egl: Don't add hardware device if there is no render node v2."

This reverts commit 5743a36b2b32a91eaf82c8d109932fe4fea01233.

Now that _eglAddDevice is always called with the correct software
hint, no need to bail out if the device doesn't have a render node.
On split render/display SoCs, the DRM device won't have a render
node, yet rendering is hardware-accelerated (via kmsro).

Signed-off-by: Simon Ser <contact@emersion.fr>
Fixes: 5743a36b2b32 ("egl: Don't add hardware device if there is no render node v2.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4178
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9697>

egl: only take render nodes into account when listing DRM devices

We don't want to expose an EGL device for a display-only DRM devices
(like VKMS). For these DRM devices we have a separate software-rendering
device (the first in the list, always present).

There is a similar check in _eglAddDRMDevice, however it will be
removed in a future commit to allow split render/display devices
to be properly added. We can't figure out whether we're on a split
render/display system before loading the driver.

Signed-off-by: Simon Ser <contact@emersion.fr>
Fixes: 5743a36b2b32 ("egl: Don't add hardware device if there is no render node v2.")
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9697>

egl: fix software flag in _eglAddDevice call on DRM

On the EGL DRM platform, call _eglAddDevice with the software flag
set if GBM has loaded a software driver. This allows _eglAddDevice
to make the difference between llvmpipe and kmsro.

This is important on split render/display SoCs: we don't want to
advertise EGL_MESA_device_software on these systems.

Completely drop disp->Options.ForceSoftware, because GBM is
responsible for choosing software rendering and doesn't take this
hint into account.

Signed-off-by: Simon Ser <contact@emersion.fr>
Fixes: 5743a36b2b32 ("egl: Don't add hardware device if there is no render node v2.")
References: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4178
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9697>

mesa/st: fix lower_tex_src_plane in multiple samplers scenario

"plane[0].i32" is the plane being lowered, it's not the sampler we're looking
for.

It worked when there's a single sampler because, eg for NV12, plane[0].i32 for
the UV plane would be 1 and the added ":uv" sampler would also land at binding
point 1.

Fixes: 079e5f73d72 ("mesa/st: rewrite src var when lowering tex_src_plane")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9812>

panfrost: Get rid of panfrost_pool_alloc()

This one is no longer used.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9827>

panfrost: Use the descriptor allocators where appropriate

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9827>

panfrost: Emit surface descriptors with pan_pack()

Now that we have surface descriptors defined in midgard.xml we can use
pan_pack() to emit them.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9827>

panfrost: Define the Surface and Surface-with-stride descriptors

Right now the code manipulates mali_ptr, but having surface descriptors
properly defined will allow us to use the descriptors allocator when
allocating a midgard texture.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9827>

panfrost: Provide various helpers to simplify descriptor allocation

Got the alignment wrong a few times, so I figured it would be good to
have helpers that take care of the alignment requirements based on
the midgard.xml definitions.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9827>

panfrost: Specify descriptor alignment requirements

Once we have that in place, we can provide macros to simplify descriptor
allocation.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9827>

pan/gen_pack: Parse alignment requirements

This will help us simplify descriptor allocation.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9827>

broadcom/compiler: try to fill up delay slots after a thrsw

The way we handle thrsw instructions is that we try to merge them
back into previously scheduled instructions to fill up its delay
slots. This is generally safe, because the thrsw won't happen until
after the delay slots, so we are not really changing the execution
order of the instructions and we just need to make sure we don't
violate a few specific restrictions.

If we have not managed to fill up all delay slots after doing this,
then we emit as many NOPs as needed to fill them. This is to ensure
that we don't schedule an instruction that needs to execute after the
thread switch before the thread switch happens. However, doing this
can lead to inefficient code, since some times the instructions we
schedule after a thrsw are indepdent of the thrsw and could be safely
executed in its delay slots.

This change removes the fixed NOP emission after a thrsw to fill
delay slots and instead adds code to ensure that our instruction
scheduling is aware of when it is scheduling instructions in the
delay slots of a previous thrsw to avoid selecting conflicting
instructions.

The only case were we still emit fixed NOPs is for the thread end that
we emit to terminate the program after scheduling all instructions
because we can't end the instruction stream before the thread end
is properly executed.

total instructions in shared programs: 13691004 -> 13648140 (-0.31%)
instructions in affected programs: 4345951 -> 4303087 (-0.99%)
helped: 19645
HURT: 652
Instructions are helped.

total max-temps in shared programs: 2319317 -> 2318687 (-0.03%)
max-temps in affected programs: 10510 -> 9880 (-5.99%)
helped: 532
HURT: 9
Max-temps are helped.

total sfu-stalls in shared programs: 31752 -> 32354 (1.90%)
sfu-stalls in affected programs: 840 -> 1442 (71.67%)
helped: 7
HURT: 467
Sfu-stalls are HURT.

total inst-and-stalls in shared programs: 13722756 -> 13680494 (-0.31%)
inst-and-stalls in affected programs: 4335590 -> 4293328 (-0.97%)
helped: 19453
HURT: 758
Inst-and-stalls are helped.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9825>

broadcom/compiler: add a v3d_qpu_writes_accum helper

We have helpers to check if an instruction writes to specific
accumulators. This one will check if it writes any of the general
purpose accumulators, which will come in handy in a follow-up
patch.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9825>

Half-revert "gallium/dri2: Pass the resource that corresponds to the plane"

This reverts the resource_get_param changes from Tomeu's commit
ab7744b280184d623cf5a67a50880bf871d8c6db.  It breaks every single
program run on iris (such as wflinfo -a gl -p glx).

iris's I915_FORMAT_MOD_Y_TILED_CCS modifier reports two planes - one for
the main surface, and a second one for the CCS surface.  However, there
is only one underlying pipe_resource.  We only use pipe_resource::next
for modifier information when importing buffers from elsewhere; there is
no res->next for internally allocated resources created with modifiers.

resource_get_param() is not supposed to chase res->next pointers.  The
hook is intended to take the base image, and the plane, as parameters.
The driver can then walk its own data structures however it sees fit
in order to find the appropriate plane, rather than enforcing a linked
list of resources.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9847>

amd: update addrlib

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9668>

amd/addrlib: define endianess differently

This removes a Mesa-specific change.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9668>

amd/addrlib: prevent defining regparm differently

Define it in meson, so addrlib won't define it.
This is adding back the addrlib original code.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9668>

amd/addrlib: add back the incorrect original DCC checking

This reduces Mesa-specific changes.

is_dcc_supported_by_CB() should protect against getting there.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9668>

anv: use helper function to get the buffer size

This ensures we get a properly aligned size for the buffer so we don't
trip over HW limits for push constants.

Closes #3703
Fixes dEQP-VK.robustness.image_robustness.push.* on HSW

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9699>

anv: move buffer size alignment into helper function

And use ANV_UBO_ALIGNMENT for it instead of a magic number.
This increases the alignment to 64B, but that ought to be good for
everyone.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9699>

lima: compute nir_sha1 for shader key even if disk cache is disabled

We're using it for in-memory cache as well, so it needs to be computed
unconditionally.

Fixes: bf09ba538595 ("lima: implement shader disk cache")
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9838>

intel: Add null hw layer

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2832>

meson: switch vulkan layer to list of choices

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2832>

anv: Align inline uniform data to ANV_UBO_ALIGNMENT

If we're going to have a #define for UBO alignments, it's probably a
good idea to make sure everything is aligned to that.  This increases
the alignment from 32B to 64B but that shouldn't hurt anyone.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9837>

intel: Fix release build breakage

We missed changing one instance of debug_flag to debug_enabled in a
release-only ifdef branch.

Fixes: 758eb18c6f2 ("intel/compiler: Make vec4 generator take debug_enabled as a parameter")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9839>

turnip: clamp to zero negative upper left corner of viewport

We cannot send negative viewport coordinates to the hardware,
so clamp them since negative min.x/y is valid per spec.
The negative origin still counts in calculations of guardband.

Fixes crash in 3DMark's "Sling Shot Extreme" test.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9629>

ci: Use CI_PROJECT_ROOT_NAMESPACE

Currently, the template in e.g. .gitlab-ci/deqp-runner.sh containing

    See https://$CI_PROJECT_NAMESPACE.pages.freedesktop.org/-/...

will print an invalid URL. Copied from .gitlab-ci/piglit/run.sh which
already uses CI_PROJECT_ROOT_NAMESPACE in its template.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9821>

docs: Add 21.0.0 hashes

This was missed from the normal 21.0.0 release MR, so here's the hash
added retroactively.

Acked-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9826>

ci/freedreno: Mark a630 as flaky on arb_draw_indirect-transform-feedback

This looks like a new one.  Unclear cause -- appeared in a large branch
with potential impact, but I had also been doing TF work around that time.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9819>

aco/ra: remove exec handling for phis

These are not temporaries anymore.

Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9763>

aco/ra: allow m0 in get_reg_specified()

Totals from 1 (0.00% of 136546) affected shaders (Navi10):
CodeSize: 12788 -> 12776 (-0.09%)
Instrs: 2441 -> 2438 (-0.12%)
Latency: 29713 -> 29731 (+0.06%)
InvThroughput: 14857 -> 14866 (+0.06%)
Copies: 354 -> 353 (-0.28%)
Branches: 66 -> 65 (-1.52%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9763>

aco/ra: iterate backwards when coalescing phis

Aligning the phi definition with the operand from
the else- block can reduce the number of branches
if the else- block is otherwise empty.

Totals from 16 (0.01% of 136546) affected shaders (Navi10:
CodeSize: 707848 -> 707312 (-0.08%); split: -0.09%, +0.01%
Instrs: 126534 -> 126400 (-0.11%); split: -0.13%, +0.02%
Latency: 6399306 -> 6395082 (-0.07%)
InvThroughput: 6134374 -> 6132119 (-0.04%); split: -0.04%, +0.00%
SClause: 1879 -> 1871 (-0.43%)
Copies: 36316 -> 36219 (-0.27%); split: -0.37%, +0.10%
Branches: 4154 -> 4127 (-0.65%); split: -0.67%, +0.02%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9763>

aco/ra: refactor SSA repairing during register allocation

The previous approach attempted to construct phi nodes
on-demand and on-the-fly. Due to several bugs, it became
necessary to always create incomplete phis for all live-in
variables on loop headers, which is highly inefficient.

The new approach assumes that live-in variables on loop-
headers don't get renamed, and afterwards does one renaming
pass per loop nest. This greatly simplifies the code and
reduces the memory footprint.

Totals from 37 (0.03% of 136546) affected shaders (Navi10):
CodeSize: 588148 -> 588020 (-0.02%); split: -0.03%, +0.01%
Instrs: 111793 -> 111761 (-0.03%); split: -0.04%, +0.01%
Latency: 4546013 -> 4545611 (-0.01%); split: -0.02%, +0.01%
InvThroughput: 2806217 -> 2805730 (-0.02%); split: -0.03%, +0.01%
VClause: 2044 -> 2046 (+0.10%)
SClause: 3889 -> 3884 (-0.13%)
Copies: 17730 -> 17700 (-0.17%); split: -0.23%, +0.06%
Branches: 3282 -> 3280 (-0.06%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9763>

aco/ra: split register_file initialization into separate function

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9763>

aco/ra: split affinity creation into separate function

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9763>

zink: follow spir-v 1.0 spec

OpEntryPoint is only supposed to include the Input and Output storage
classes prior to SPIR-V 1.4.

Since we're always emitting SPIR-V 1.0, we should simply omit these from
OpEntryPoint for now. If we start emitting SPIR-V 1.4 or later, we
should add these back in.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9828>

lima/ppir: rework liveness data structures to bitset

The liveness code in ppir can be a bottleneck in complicated shaders
with multiple spills, and the use of the mesa set data structure is one
of the main reasons it is expensive to run.
With some changes, it can be adapted to using bitsets which makes it run
substantially faster.
ppir liveness can't run with a regular bitset for registers since we
need to track inviditual component masks for non-ssa registers, but we
can switch to using a separate packed bit array just for the masks,
rather than a full blown hash set. This also makes operations such as
liveness propagation much more straightforward.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9745>

lima/ppir: remove use of live_out

The live_out set was serving mostly as a temporary storage of data
propagated from the next instructions.
If we do an early copy to preserve the instruction live_in set and
propagate the liveness information directly to the live_in set, we can
skip having a live_out set entirely.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9745>

lima/ppir: remove liveness info from blocks

liveness information was stored in blocks so that the algorithm doesn't
have to find a valid instruction to inherit liveness information from.
It turns out this part of the code can be a performance bottleneck in
applications loading with complicated shaders, so skip the liveness
information in blocks to reduce the number of times we have to copy
liveness information.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9745>

turnip: implement VK_KHR_pipeline_executable_properties

Loosely based on ANV implementation.

For executable's internal representation we output:
- Initial NIR after spirv_to_nir
- Final optimized NIR
- IR3 disassembly

Note, that vkGetPipelineExecutablePropertiesKHR is required to
return executable properties even if pipeline was not created with
CAPTURE_STATISTICS or CAPTURE_INTERNAL_REPRESENTATIONS bits set.
So the executables array is unconditionally populated, however
NIR and IR3 disassemlies are filled only when
CAPTURE_INTERNAL_REPRESENTATIONS is set.

Passes dEQP-VK.pipeline.executable_properties.*
Works with RenderDoc.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8877>

nir: add nir_shader_as_str function

It would be later used by Turnip in implementation of
VK_KHR_pipeline_executable_properties.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8877>

pan/mdg: Use appropriate sizes for global loads/stores

When always using 128-bit operations, an access at the end of an SSBO
could spill over to the next page and cause a GPU fault. To avoid
this, pick the smallest instruction that fits.

The if ladder might need extending for sizes of less than 32 bits, but
those currently fail in other parts of the compiler so are untested.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9747>

pan/mdg: Rename load/store operations

Use the actual bit sizes the instructions deal with.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9747>

ac: invalidate metadata after hs_emit_write_tess_factors()

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9804>

broadcom/compiler: convert add to mul when possible to allow merge

Integer add/sub can be implemented as either an add or a mul instruction
but we always emit them as add instructions at VIR level. We can use this
flexibility to improve our QPU scheduling so we can be more effective
at instruction merging by converting these to mul instructions when we
are attempting to merge them with another add instruction.

total instructions in shared programs: 13721549 -> 13691004 (-0.22%)
instructions in affected programs: 3340493 -> 3309948 (-0.91%)
helped: 12805
HURT: 1656
Instructions are helped.

total max-temps in shared programs: 2319528 -> 2319317 (<.01%)
max-temps in affected programs: 5285 -> 5074 (-3.99%)
helped: 195
HURT: 3
Max-temps are helped.

total sfu-stalls in shared programs: 31616 -> 31752 (0.43%)
sfu-stalls in affected programs: 469 -> 605 (29.00%)
helped: 52
HURT: 161
Sfu-stalls are HURT.

total inst-and-stalls in shared programs: 13753165 -> 13722756 (-0.22%)
inst-and-stalls in affected programs: 3340383 -> 3309974 (-0.91%)
helped: 12782
HURT: 1666
Inst-and-stalls are helped.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9769>

v3dv/cmd_buffer: return early for draw commands if there is nothing to draw

So for example, on v3dv_CmdDrawIndexed we can return early if
instanceCount is 0.

This fixes failures when using the simulator with tests with the
following pattern:
dEQP-VK.draw.instanced.draw_indexed_vk_primitive_topology*

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9820>

v3dv/pipeline_cache: fix assert

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Fixes: e354c5280 ('3dv/pipeline: try to get the shader variant directly from the cache')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9824>

zink: do not open-code vector-compares

We already have code to lower away these to something we don't need so
much special-case code to handle.

The sad part here is that we generate slightly worse code; trees of
OpLogicalAnd / OpLogicalOr instead of OpAny OpAll. But I would imagine
that for any GPU where this matters, these would be easy to combine
back, so I'm not losing a lot of sleep over this.

But this makes things simpler. And if we *really* care about OpAny or
OpAll, we should add NIR ALU instructions for them so we can optimize
them on other places as well, not open-code all places where it could
improve things.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9797>

zink: drop bool attempt in float vector compares

There's no such thing as a 1-bit float, so remove the special-case. It's
not going to trigger.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9797>

zink: fix vector comparison

This should have been using unordered compares all along.

This fixes a dEQP failure.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9797>

lima: implement shader disk cache

Wire up disk cache routines and change fs and vs keys to use nir_sha1
instead of pointer to uncompiled shader to be able to reuse them for
disk cache.

Tested-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9672>

lima: rename lima_{fs,vs}_bind_state to lima_{fs,vs}_uncompiled_shader

Tested-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9672>

lima: rename *_shader_state to *_compiled_shader

Tested-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9672>

android: add some more stub functions for cross compilation

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9796>

gbm: add gbm_bo_get_fd_for_plane

This commit adds a new gbm_bo_get_fd_for_plane function, which does the
same as gbm_bo_get_fd but allows specifying the plane.

v2: - Rename to gbm_bo_get_fd_for_plane (Emil)

Signed-off-by: Simon Ser <contact@emersion.fr>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5442>

gallium/dri2: Pass the resource that corresponds to the plane

Previously, we were calling resource_get_handle for the first plane in
the image, regardless of what plane was being requested.

v2: - Add assert (Simon)

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5442>

anv/android: fix image creation with external format

This fixes crashes seen with following group of tests:
   android.graphics.cts.BasicVulkanGpuTest

Fixes: 6fa56273be7 ("anv/image: Drop duplicate 'format' in anv_image_create()")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9799>

glcpp: Fix undefined behaviour in glcpp

Specifically, fix this error (which is covered in existing tests):

    ../src/compiler/glsl/glcpp/pp.c:198:28: runtime error: applying non-zero offset 1 to null pointer
    SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior ../src/compiler/glsl/glcpp/pp.c:198:28 in

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9669>

docs: update calendar and link releases notes for 21.0.1

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9818>

docs: Add 21.0.1 hashes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9818>

docs: add release notes for 21.0.1

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9818>

docs: update calendar and link releases notes for 20.3.5

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9818>

docs: Add hashes for 20.3.5

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9818>

docs: add release notes for 20.3.5

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9818>

lavapipe: use the passed offset for CmdCopyQueryPoolResults

this avoids overwriting buffer[0] on every copy

Fixes: b38879f8c5f ("vallium: initial import of the vulkan frontend")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9813>

lavapipe: fix CmdCopyQueryPoolResults for partial pipeline statistics queries

if this isn't a query for all pipeline statistics, the bits that are
set need to be individually copied in increasing order

Fixes: b38879f8c5f ("vallium: initial import of the vulkan frontend")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9813>

util/set: stop leaking u32 key sets which pass a mem ctx

Fixes: 10a76824137 ("util: add _mesa_set_create_u32_keys where keys are not pointers")

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9810>

intel/compiler: Use a struct for brw_compile_cs parameters

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>

intel/compiler: Use INTEL_DEBUG=blorp to dump blorp shaders

Make INTEL_DEBUG=blorp dump the blorp shaders instead using the
general INTEL_DEBUG=fs,vs, which is now reserved to the actual FS and
VS shaders used by the pipeline.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>

intel/compiler: Make visitors take debug_enabled as a parameter

The callers already have this value, and we would like to make it
follow different rules other than stage that might not be visible to
the helper function, so just pass explicitly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>

intel/compiler: Make vec4 generator take debug_enabled as a parameter

The callers already have this value, and we would like to make it
follow different rules other than stage that might not be visible to
the helper function, so just pass explicitly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>

intel/compiler: Make brw_postprocess_nir take debug_enabled as a parameter

The callers already have this value, and we would like to make it
follow different rules other than stage that might not be visible to
the helper function, so just pass explicitly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>

intel/compiler: Refactor the shader INTEL_DEBUG checks

Make the check once in a variable, that can be reused for other parts.
Also add `unlikely` to the various conditionals depending on it

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>

intel/compiler: Use a struct for brw_compile_vs parameters

Makes calling code more explicit about what is being set, and allows
take advantage of zero initialization for the ones the callsite don't
care.

Besides moving to the struct, two extra "ergonomic" changes were done:

- Add a new shader_time boolean, so shader_time_index is ignored when
  unused -- this allow taking advantage of the zero initialization of
  unset fields.

- Since we have a struct, provide space for the error_str pointer.
  Both iris and i965 were using it, and the extra rstrdup in case of
  failure shouldn't be a burden for the others.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>

intel/compiler: Use a struct for brw_compile_fs parameters

Makes calling code more explicit about what is being set, and allows
take advantage of zero initialization for the ones the callsite don't
care.

Besides moving to the struct, two extra "ergonomic" changes were done:

- Add a new shader_time boolean, so shader_time_index is ignored when
  unused -- this allow taking advantage of the zero initialization of
  unset fields.

- Since we have a struct, provide space for the error_str pointer.
  Both iris and i965 were using it, and the extra rstrdup in case of
  failure shouldn't be a burden for the others.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>

intel/compiler: Make vue_map parameter const for brw_compile_fs

Just a documentation hint that the VUE map is not modified.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>

aco/ra: Avoid unnecessary copying of std::vectors

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9801>

freedreno: Clamp TF prims written to buffer size pre-a6xx.

I thought based on some previous debug this was going to fix a pile of
dEQPs, but no luck.  Still, one less TODO in the driver.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9687>

freedreno: Don't count SW TF queries on a6xx.

On a6xx, since we have GS and tess, we do this counting in hardware.  The
next fix is going to use some functions that don't work with GS prims.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9687>

freedreno: Move the primitives generated/written updates after the draw.

If we're going to clamp the written value, we need the max vtx update from
the draw's state emit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9687>

freedreno: Move max-tf-vtx calculation to just the HW that needs it.

a3xx-a4xx use it in in-shader TF code, and all of a3xx-a5xx will need it
shortly for fixing the SW TF queries.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9687>

freedreno/ir3: Move max-tf-vtx calculation to a .c file

This much code should probably be a function.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9687>

freedreno: Assert that TF prims generated can ignore active_queries.

We won't ever be in a meta path with transform feedback enabled, so we
don't need to pay attention to the flag here.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9687>

zink: check for mirror-clamp extension

This cap depends on a device extension.

Fixes: b59d98ae5f2 ("zink: enable PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9803>

zink: add missing required feature

We check for this feature in zink_is_format_supported, so VK drivers
need to expose it to get BC textures working. Let's document the
reality.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9803>

zink: check for stores and atomics features

These limits depens on feature-bits.

Fixes: 322a3d4fb0c ("zink: partially enable SSBO pipe cap")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9803>

zink: check for depth-bias-clamp feature

This cap depends on a feature-bit.

Fixes: 3d7d55c2cf4 ("zink: enable PIPE_CAP_POLYGON_OFFSET_CLAMP")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9803>

zink: check for pipeline statistics feature

This cap depends on a feature-bit.

Fixes: cb5957e13d1 ("zink: enable pipeline statistics cap")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9803>

ci/fdo: Use trimmed traces for Valve games

Now that we have trimmed versions of them, we can run them in a more
reasonable amount of time.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9771>

iris: Flag for resolves when stencil enable changes, too.

The watcher of this dirty flag looks at this state, so it sure seems like
it needs it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9768>

zink: don't generate sampled image type for non-sampled images

this creates validation errors

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9802>

compiler/spirv: use undefs when extending image coords

we need 4 components for the nir ops, but swizzling one value to multiple
channels like this gets confusing when trying to debug image ops that don't
require 4 channels

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9723>

ci/android: Build the v3dv driver.

We want to make sure that this keeps working on Android.

Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9764>

ci/android: Make sure we don't detect system libexpat.

There may be some more elegant way to do things, but the important thing
is that android builds don't have any .pc files we should be using, other
than what our CI generated for zlib.

Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9764>

broadcom: Disbale CLIF dumping when libexpat isn't available.

Given what a niche developer tool CLIF dumps are, no sense requiring
libexpat just for that.

Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9764>

turnip: Fix KGSL build since common dispatch rework.

Fixes: 59d70c47c774 ("turnip: Use the common dispatch framework")
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9764>

zink: add more rp cache asserts

ensure that any discrepencies are immediately detected

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9784>

zink: remove unnecessary flush during image maps

Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9786>

zink: remove handling for resource flushing between compute/gfx batches

this is no longer a thing

Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9786>

zink: avoid unnecessary resource refs during descriptor update

this was necessary if resources could be on both gfx and compute batches,
but now there's only one type of batch

Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9786>