Krzysztof Parzyszek [Mon, 30 Apr 2018 19:38:47 +0000 (19:38 +0000)]
[LivePhysRegs] Remove registers clobbered by regmasks from the live set
Dead defs were being removed from the live set (in stepForward), but
registers clobbered by regmasks weren't (more specifically, they were
actually removed by removeRegsInMask, but then they were added back in).
llvm-svn: 331219
Nirav Dave [Mon, 30 Apr 2018 19:22:40 +0000 (19:22 +0000)]
[MC] Change AsmParser to leverage Assembler during evaluation
Teach AsmParser to check with Assembler for when evaluating constant
expressions. This improves the handing of preprocessor expressions
that must be resolved at parse time. This idiom can be found as
assembling-time assertion checks in source-level assemblers. Note that
this relies on the MCStreamer to keep sufficient tabs on Section /
Fragment information which the MCAsmStreamer does not. As a result the
textual output may fail where the equivalent object generation would
pass. This can most easily be resolved by folding the MCAsmStreamer
and MCObjectStreamer together which is planned for in a separate
patch.
Currently, this feature is only enabled for assembly input, keeping IR
compilation consistent between assembly and object generation.
Reviewers: echristo, rnk, probinson, espindola, peter.smith
Reviewed By: peter.smith
Subscribers: eraman, peter.smith, arichardson, jyknight, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D45164
llvm-svn: 331218
Florian Hahn [Mon, 30 Apr 2018 19:19:36 +0000 (19:19 +0000)]
[LoopSimplify] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).
This patch updates some code responsible the skip debug info to use
BasicBlock::instructionsWithoutDebug. I think this makes things slightly
simpler and more direct.
Reviewers: aprantl, vsk, chandlerc
Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D46253
llvm-svn: 331217
Matt Arsenault [Mon, 30 Apr 2018 19:08:27 +0000 (19:08 +0000)]
AMDGPU: Add Vega12 and Vega20
Changes by
Matt Arsenault
Konstantin Zhuravlyov
llvm-svn: 331216
Matt Arsenault [Mon, 30 Apr 2018 19:08:16 +0000 (19:08 +0000)]
AMDGPU: Add Vega12 and Vega20
Changes by
Matt Arsenault
Konstantin Zhuravlyov
llvm-svn: 331215
Hans Wennborg [Mon, 30 Apr 2018 19:04:04 +0000 (19:04 +0000)]
clang-cl: Expose -fmerge-all-constants
Now that constant merging is off by default, we'd like a way to enable
it on Windows.
llvm-svn: 331214
Roman Tereshin [Mon, 30 Apr 2018 18:58:57 +0000 (18:58 +0000)]
[MIR] Reset unique MBB numbering in MachineFunction::reset()
No need to waste space nor number MBBs differently if MF gets recreated.
Reviewers: qcolombet, stoklund, t.p.northover, bogner, javed.absar
Reviewed By: qcolombet
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46078
llvm-svn: 331213
Jonathan Peyton [Mon, 30 Apr 2018 18:46:31 +0000 (18:46 +0000)]
[OpenMP][OMPT] Fix api_calls_from_other_thread.cpp
Removed environment setting in RUN: line that was being ignored anyways.
Changed a few specific checks to "any number"
llvm-svn: 331212
Alexey Bataev [Mon, 30 Apr 2018 18:28:08 +0000 (18:28 +0000)]
[OPENMP] Do not emit warning about non-declared target function params.
We should not emit warning that the parameters are not marked as declare
target, these declaration are local and cannot be marked as declare
target.
llvm-svn: 331211
Sanjay Patel [Mon, 30 Apr 2018 18:20:33 +0000 (18:20 +0000)]
[DAGCombiner] rename function attribute for disabling ftrunc transform
This is the matching name change for the Clang patch at:
D46236
rL331209
Differential Revision: https://reviews.llvm.org/D46237
llvm-svn: 331210
Sanjay Patel [Mon, 30 Apr 2018 18:19:03 +0000 (18:19 +0000)]
[Driver, CodeGen] rename options to disable an FP cast optimization
As suggested in the post-commit thread for rL331056, we should match these
clang options with the established vocabulary of the corresponding sanitizer
option. Also, the use of 'strict' is well-known for these kinds of knobs,
and we can improve the descriptive text in the docs.
So this intends to match the logic of D46135 but only change the words.
Matching LLVM commit to match this spelling of the attribute to follow shortly.
Differential Revision: https://reviews.llvm.org/D46236
llvm-svn: 331209
Simon Pilgrim [Mon, 30 Apr 2018 18:18:38 +0000 (18:18 +0000)]
[X86] Introduce X86SchedWriteWidths schedule wrapper for different vector widths.
We need to split most of the scheduler classes by vector width to remove more of the InstRW overrides, this patch should make this easier/tidier by allowing us to pass the X86SchedWriteWidths wrapper to multi-width multiclasses and then split as required.
I've included fields for Scl (scalar float/double), MMX (MMX integer), XMM, YMM and ZMM widths. These fields mostly share the same classes but it should give us the flexibility that we may need in the future.
This patch has replaced a set of example SSE/AVX512 instruction cases but isn't exhaustive as it gets very noisy before we really need the functionality.
Differential Revision: https://reviews.llvm.org/D46266
llvm-svn: 331208
Alexander Kornienko [Mon, 30 Apr 2018 18:12:15 +0000 (18:12 +0000)]
Regenerated AST Matchers doc.
Backported a minor fix to the comment in the header.
llvm-svn: 331207
Alexey Bataev [Mon, 30 Apr 2018 18:09:40 +0000 (18:09 +0000)]
[OPENMP] Do not crash on codegen for CXX member functions.
Non-static member functions should not be emitted as a standalone
functions, this leads to compiler crash.
llvm-svn: 331206
Roman Lebedev [Mon, 30 Apr 2018 17:59:33 +0000 (17:59 +0000)]
[InstCombine] Unfold masked merge with constant mask
Summary:
As discussed in D45733, we want to do this in InstCombine.
https://rise4fun.com/Alive/LGk
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: chandlerc, xbolva00, llvm-commits
Differential Revision: https://reviews.llvm.org/D45867
llvm-svn: 331205
Roman Lebedev [Mon, 30 Apr 2018 17:59:26 +0000 (17:59 +0000)]
[InstCombine][NFC] Add tests for unfolding masked merge with constant mask
Summary: As discussed in D45733, we want to do this in InstCombine.
Differential Revision: https://reviews.llvm.org/D45866
llvm-svn: 331204
Ulrich Weigand [Mon, 30 Apr 2018 17:54:28 +0000 (17:54 +0000)]
[SystemZ] Handle SADDO et.al. and ADD/SUBCARRY
This provides an optimized implementation of SADDO/SSUBO/UADDO/USUBO
as well as ADDCARRY/SUBCARRY on top of the new CC implementation.
In particular, multi-word arithmetic now uses UADDO/ADDCARRY instead
of the old ADDC/ADDE logic, which means we no longer need to use
"glue" links for those instructions. This also allows making full
use of the memory-based instructions like ALSI, which couldn't be
recognized due to limitations in the DAG matcher previously.
Also, the llvm.sadd.with.overflow et.al. intrinsincs now expand to
directly using the ADD instructions and checking for a CC 3 result.
llvm-svn: 331203
Ulrich Weigand [Mon, 30 Apr 2018 17:52:32 +0000 (17:52 +0000)]
[SystemZ] Do not use glue to represent condition code dependencies
Currently, an instruction setting the condition code is linked to
the instruction using the condition code via a "glue" link in the
SelectionDAG. This has a number of drawbacks; in particular, it
means the same CC cannot be used by multiple users. It also makes
it more difficult to efficiently implement SADDO et. al.
This patch changes the back-end to represent CC dependencies as
normal values during SelectionDAG matching, along the lines of
how this is handled in the X86 back-end already.
In addition to the core mechanics of updating all relevant patterns,
this requires a number of additional changes:
- We now need to be able to spill/restore a CC value into a GPR
if necessary. This means providing a copyPhysReg implementation
for moves involving CC, and defining getCrossCopyRegClass.
- Since we still prefer to avoid such spills, we provide an override
for IsProfitableToFold to avoid creating a merged LOAD / ICMP if
this would result in multiple users of the CC.
- combineCCMask no longer requires a single CC user, and no longer
need to be careful about preventing invalid glue/chain cycles.
- emitSelect needs to be more careful in marking CC live-in to
the basic block it generates. Also, we can now optimize the
case of multiple subsequent selects with the same condition
just like X86 does.
llvm-svn: 331202
Daniel Sanders [Mon, 30 Apr 2018 17:20:01 +0000 (17:20 +0000)]
Fix infinite loop after r331115
There are two separate fixes here:
* The lowering code for non-extending loads should report UnableToLegalize instead of emitting the same instruction.
* The target should not be requesting lowering of non-extending loads.
llvm-svn: 331201
Jonas Devlieghere [Mon, 30 Apr 2018 17:02:41 +0000 (17:02 +0000)]
[DebugInfo] Prevent infinite recursion for malformed DWARF
This prevents infinite recursion in DWARFDie::findRecursively for
malformed DWARF where a DIE references itself.
This fixes PR36257.
Differential revision: https://reviews.llvm.org/D43092
llvm-svn: 331200
Davide Italiano [Mon, 30 Apr 2018 16:57:33 +0000 (16:57 +0000)]
[SLPVectorizer] Debug info shouldn't impact spill cost computation.
<rdar://problem/
39794738>
(Also, PR32761).
Differential Revision: https://reviews.llvm.org/D46199
llvm-svn: 331199
Simon Pilgrim [Mon, 30 Apr 2018 16:51:13 +0000 (16:51 +0000)]
[X86][Atom] Remove unnecessary x87 load/move instrw overrides.
llvm-svn: 331198
Adrian Prantl [Mon, 30 Apr 2018 16:49:04 +0000 (16:49 +0000)]
Reflow paragraphs in comments.
This is intended as a clean up after the big clang-format commit
(r280751), which unfortunately resulted in many of the comment
paragraphs in LLDB being very hard to read.
FYI, the script I used was:
import textwrap
import commands
import os
import sys
import re
tmp = "%s.tmp"%sys.argv[1]
out = open(tmp, "w+")
with open(sys.argv[1], "r") as f:
header = ""
text = ""
comment = re.compile(r'^( *//) ([^ ].*)$')
special = re.compile(r'^((([A-Z]+[: ])|([0-9]+ )).*)|(.*;)$')
for line in f:
match = comment.match(line)
if match and not special.match(match.group(2)):
# skip intentionally short comments.
if not text and len(match.group(2)) < 40:
out.write(line)
continue
if text:
text += " " + match.group(2)
else:
header = match.group(1)
text = match.group(2)
continue
if text:
filled = textwrap.wrap(text, width=(78-len(header)),
break_long_words=False)
for l in filled:
out.write(header+" "+l+'\n')
text = ""
out.write(line)
os.rename(tmp, sys.argv[1])
Differential Revision: https://reviews.llvm.org/D46144
llvm-svn: 331197
Tom Stellard [Mon, 30 Apr 2018 16:28:02 +0000 (16:28 +0000)]
AMDGPU: Remove some dead code
llvm-svn: 331196
Alexey Bataev [Mon, 30 Apr 2018 16:26:57 +0000 (16:26 +0000)]
[OPENMP] Do not crash on incorrect input data.
Emit error messages instead of compiler crashing when the target region
does not exist in the device code + fix crash when the location comes
from macros.
llvm-svn: 331195
Jan Kratochvil [Mon, 30 Apr 2018 16:04:32 +0000 (16:04 +0000)]
Match also DW_TAG_partial_unit when DW_TAG_compile_unit is matched
Code commonly checks if the parent DIE is DW_TAG_compile_unit.
But DW_TAG_partial_unit also acts as DW_TAG_compile_unit for DWZ
as DWZ is using DW_TAG_imported_unit only at the top unit level.
Differential revision: https://reviews.llvm.org/D40469
llvm-svn: 331194
Andrea Di Biagio [Mon, 30 Apr 2018 15:55:04 +0000 (15:55 +0000)]
[llvm-mca] Correctly handle zero-latency stores that consume pipeline resources.
This fixes PR37293.
We can have scheduling classes with no write latency entries, that still consume
processor resources. We don't want to treat those instructions as zero-latency
instructions; they still have to be issued to the underlying pipelines, so they
still consume resource cycles.
This is likely to be a regression which I have accidentally introduced at
revision 330807. Now, if an instruction has a non-empty set of write processor
resources, we conservatively treat it as a normal (i.e. non zero-latency)
instruction.
llvm-svn: 331193
Ulrich Weigand [Mon, 30 Apr 2018 15:52:28 +0000 (15:52 +0000)]
[SystemZ] Refactor some VT casts in DAG match patterns
In patterns where we need to specify a result VT, prefer
[(set (tr.vt tr.op:$V1), (operator ...))]
over
[(set tr.op:$V1, (tr.vt (operator ...)))]
This is NFC now, but simplifies some future changes.
llvm-svn: 331192
Ulrich Weigand [Mon, 30 Apr 2018 15:49:27 +0000 (15:49 +0000)]
[SystemZ] Improve handling of Select pseudo-instructions
If we have LOCR instructions, select them directly from SelectionDAG
instead of first going through a pseudo instruction and then using
the custom inserter to emit the LOCR.
Provide Select pseudo-instructions for VR32/VR64 if we have vector
instructions, to avoid having to go through the first 16 FPRs
unnecessarily.
If we do not have LOCFHR, prefer using LOCR followed by a move
over a conditional branch.
llvm-svn: 331191
Nico Weber [Mon, 30 Apr 2018 15:26:01 +0000 (15:26 +0000)]
IWYU for llvm-config.h, removals. Also see r331184.
llvm-svn: 331190
Haojian Wu [Mon, 30 Apr 2018 15:24:17 +0000 (15:24 +0000)]
[clangd] Using index for GoToDefinition.
Summary:
This patch adds index support for GoToDefinition -- when we don't get the
definition from local AST, we query our index (Static&Dynamic) index to
get it.
Since we currently collect top-level symbol in the index, it doesn't support all
cases (e.g. class members), we will extend the index to include more symbols in
the future.
Reviewers: sammccall
Subscribers: klimek, ilya-biryukov, jkorous-apple, ioeric, MaskRay, cfe-commits
Differential Revision: https://reviews.llvm.org/D45717
llvm-svn: 331189
Simon Pilgrim [Mon, 30 Apr 2018 15:18:33 +0000 (15:18 +0000)]
[X86] Drop unnecessary VPORrm InstrRW override in SkylakeServer.
llvm-svn: 331188
Simon Pilgrim [Mon, 30 Apr 2018 15:17:16 +0000 (15:17 +0000)]
[X86] Fix SkylakeServer typo in WritePSADBW class - it only uses 1 resource.
llvm-svn: 331187
Tom Stellard [Mon, 30 Apr 2018 15:15:23 +0000 (15:15 +0000)]
AMDGPU/GlobalISel: Don't try to lower geometry shaders
Summary: The AMDGPU_GS calling convention is not supported yet.
Reviewers: arsenm, nhaehnle
Reviewed By: nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D46041
llvm-svn: 331186
Nico Weber [Mon, 30 Apr 2018 14:59:11 +0000 (14:59 +0000)]
IWYU for llvm-config.h in llvm, additions.
See r331124 for how I made a list of files missing the include.
I then ran this Python script:
for f in open('filelist.txt'):
f = f.strip()
fl = open(f).readlines()
found = False
for i in xrange(len(fl)):
p = '#include "llvm/'
if not fl[i].startswith(p):
continue
if fl[i][len(p):] > 'Config':
fl.insert(i, '#include "llvm/Config/llvm-config.h"\n')
found = True
break
if not found:
print 'not found', f
else:
open(f, 'w').write(''.join(fl))
and then looked through everything with `svn diff | diffstat -l | xargs -n 1000 gvim -p`
and tried to fix include ordering and whatnot.
No intended behavior change.
llvm-svn: 331184
Bjorn Pettersson [Mon, 30 Apr 2018 14:37:46 +0000 (14:37 +0000)]
[BranchFolding] Salvage DBG_VALUE instructions from empty blocks
Summary:
This patch will introduce copying of DBG_VALUE instructions
from an otherwise empty basic block to predecessor/successor
blocks in case the empty block is eliminated/bypassed. It
is currently only done in one identified situation in the
BranchFolding pass, before optimizing on empty block.
It can be seen as a light variant of the propagation done
by the LiveDebugValues pass, which unfortunately is executed
after the BranchFolding pass.
We only propagate (copy) DBG_VALUE instructions in a limited
number of situations:
a) If the empty BB is the only predecessor of a successor
we can copy the DBG_VALUE instruction to the beginning of
the successor (because the DBG_VALUE instruction is always
part of the flow between the blocks).
b) If the empty BB is the only successor of a predecessor
we can copy the DBG_VALUE instruction to the end of the
predecessor (because the DBG_VALUE instruction is always
part of the flow between the blocks). In this case we add
the DBG_VALUE just before the first terminator (assuming
that the terminators do not impact the DBG_VALUE).
A future solution, to handle more situations, could perhaps
be to run the LiveDebugValues pass before branch folding?
This fix is related to PR37234. It is expected to resolve
the problem seen, when applied together with the fix in
SelectionDAG from here: https://reviews.llvm.org/D46129
Reviewers: #debug-info, aprantl, rnk
Reviewed By: #debug-info, aprantl
Subscribers: ormris, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D46184
llvm-svn: 331183
Bjorn Pettersson [Mon, 30 Apr 2018 14:37:39 +0000 (14:37 +0000)]
[SelectionDAG] Improve selection of DBG_VALUE using a PHI node result
Summary:
When building the selection DAG at ISel all PHI nodes are
selected and lowered to Machine Instruction PHI nodes before
we start to create any SDNodes. So there are no SDNodes for
values produced by the PHI nodes.
In the past when selecting a dbg.value intrinsic that uses
the value produced by a PHI node we have been handling such
dbg.value intrinsics as "dangling debug info". I.e. we have
not created a SDDbgValue node directly, because there is
no existing SDNode for the PHI result, instead we deferred
the creationg of a SDDbgValue until we found the first use
of the PHI result.
The old solution had a couple of flaws. The position of the
selected DBG_VALUE instruction would end up quite late in a
basic block, and for example not directly after the PHI node
as in the LLVM IR input. And in case there were no use at all
in the basic block the dbg.value could be dropped completely.
This patch introduces a new VREG kind of SDDbgValue nodes.
It is similar to a SDNODE kind of node, but it refers directly
to a virtual register and not a SDNode. When we do selection
for a dbg.value that is using the result of a PHI node we
can do a lookup of the virtual register directly (as it already
is determined for the PHI node) and create a SDDbgValue node
immediately instead of delaying the selection until we find a
use.
This should fix a problem with losing debug info at ISel
as seen in PR37234 (https://bugs.llvm.org/show_bug.cgi?id=37234).
It does not resolve PR37234 completely, because the debug info
is dropped later on in the BranchFolder (see D46184).
Reviewers: #debug-info, aprantl
Reviewed By: #debug-info, aprantl
Subscribers: rnk, gbedwell, aprantl, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D46129
llvm-svn: 331182
Zaara Syeda [Mon, 30 Apr 2018 14:37:28 +0000 (14:37 +0000)]
Fix warning: result of 32-bit shift implicitly converted to 64 bits - NFC
Fix warning caused by rL331046.
Differential Revision: https://reviews.llvm.org/D45729
llvm-svn: 331181
Pavel Labath [Mon, 30 Apr 2018 14:30:02 +0000 (14:30 +0000)]
llgs tests: Use noack-mode for communication to avoid pr37294
llvm-svn: 331180
Gabor Buella [Mon, 30 Apr 2018 14:21:28 +0000 (14:21 +0000)]
NFC, Avoid a warning on pointer casting in PassPlugin.cpp
llvm-svn: 331179
Simon Dardis [Mon, 30 Apr 2018 14:03:35 +0000 (14:03 +0000)]
Revert "[mips] Fix the predicates of jump and branch and link instructions"
That commit broke one of the LLD builders, reverting while I investigate.
This patch reverts r331175.
llvm-svn: 331178
Nico Weber [Mon, 30 Apr 2018 13:52:15 +0000 (13:52 +0000)]
IWYU for llvm-config.h in clang. See r331124 for details.
llvm-svn: 331177
Nico Weber [Mon, 30 Apr 2018 13:47:04 +0000 (13:47 +0000)]
Remove unnecessary indirection. No behavior change.
llvm-svn: 331176
Simon Dardis [Mon, 30 Apr 2018 13:37:42 +0000 (13:37 +0000)]
[mips] Fix the predicates of jump and branch and link instructions
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D46114
llvm-svn: 331175
Florian Hahn [Mon, 30 Apr 2018 13:28:08 +0000 (13:28 +0000)]
[LV] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).
This patch updates some code responsible the skip debug info to use
BasicBlock::instructionsWithoutDebug. I think this makes things
slightly simpler and more direct.
Reviewers: mkuper, rengolin, dcaballe, aprantl, vsk
Reviewed By: rengolin
Differential Revision: https://reviews.llvm.org/D46254
llvm-svn: 331174
Pavel Labath [Mon, 30 Apr 2018 13:23:47 +0000 (13:23 +0000)]
ObjectFileELF: Add support for arbitrarily named code sections
ObjectFileELF assumes that code section has ".text" name. There is an
exception for kalimba toolchain that can use arbitrary names, but other
toolchains also could use arbitrary names for code sections. For
example, corert uses separate section for compiled managed code. As lldb
doesn't recognize such section it leads to problem with breakpoints on
arm, because debugger cannot determine instruction set (arm/thumb) and
uses incorrect breakpoint opcode that breaks program execution.
This change allows debugger to correctly handle such code sections. We
assume that section is a code section if it has SHF_EXECINSTR flag set
and has SHT_PROGBITS type.
Patch by Konstantin Baladurin <k.baladurin@partner.samsung.com>.
Differential Revision: https://reviews.llvm.org/D44998
llvm-svn: 331173
Pavel Labath [Mon, 30 Apr 2018 12:59:14 +0000 (12:59 +0000)]
Fixup r331049 (FileSpec auto-normalization)
A typo in the patch (using syntax instead of m_syntax) resulted in the
normalization not working properly for windows filespecs when the syntax
was passed as host-native. This did not affect the unit tests, as all of
those pass an explicity syntax, but failed gloriously when running the
full test suite.
I also fix an expectation in an lldb-mi test, which was now failing
because it was expecting a path to be echoed verbatim, but we were now
normalizing it.
As a drive-by, this also fixes the default-in-fully-covered-switch
warning and removes an unused argument from the NeedsNormalization
function.
llvm-svn: 331172
Benjamin Kramer [Mon, 30 Apr 2018 12:48:45 +0000 (12:48 +0000)]
[bindings] Fix dibuilder go bindings after r331114.
llvm-svn: 331171
Andrea Di Biagio [Mon, 30 Apr 2018 12:13:04 +0000 (12:13 +0000)]
[llvm-mca] Regenerate test Atom/resources-sse3.s. NFC
Before this change, it wrongly specified -mcpu=slm instead of -mcpu=atom.
llvm-svn: 331170
Andrea Di Biagio [Mon, 30 Apr 2018 12:05:34 +0000 (12:05 +0000)]
[llvm-mca] Support for in-order CPU for -instruction-tables testing.
Added Intel Atom tests to verify that the tool correctly generates instruction
tables even if the CPU is in-order.
Fixes PR37282.
llvm-svn: 331169
Haojian Wu [Mon, 30 Apr 2018 11:40:02 +0000 (11:40 +0000)]
[clangd] Also use UTF-16 in index position.
Reviewers: sammccall
Subscribers: klimek, ilya-biryukov, ioeric, MaskRay, jkorous, cfe-commits
Differential Revision: https://reviews.llvm.org/D46258
llvm-svn: 331168
Simon Pilgrim [Mon, 30 Apr 2018 10:46:35 +0000 (10:46 +0000)]
[X86] Fix typo in skylake-avx512 model for PMAXSD/PMINSD instructions
The PMAXSD/PMINSD instregexs had been written as PMAX(C?)SD - looks like this was a search+replace error when matching float MAXSD/MINSD commutative instructions.
llvm-svn: 331167
Gabor Buella [Mon, 30 Apr 2018 10:18:11 +0000 (10:18 +0000)]
NFC - Typo fixes lib/VMCore -> lib/IR
llvm-svn: 331166
Simon Dardis [Mon, 30 Apr 2018 09:44:44 +0000 (09:44 +0000)]
[mips] Fix microMIPS loads and stores.
Previously these instructions were unselectable and instead were generated
through the instruction mapping tables.
Reviewers: atanasyan, smaksimovic, abeserminji
Differential Revision: https://reviews.llvm.org/D46055
llvm-svn: 331165
Mikhail Maltsev [Mon, 30 Apr 2018 09:11:08 +0000 (09:11 +0000)]
[Targets] Implement getConstraintRegister for ARM and AArch64
Summary:
The getConstraintRegister method is used by semantic checking of
inline assembly statements in order to diagnose conflicts between
clobber list and input/output lists. Currently ARM and AArch64 don't
override getConstraintRegister, so conflicts between registers
assigned to variables in asm labels and clobber lists are not
diagnosed. Such conflicts can cause assertion failures in the back end
and even miscompilations.
This patch implements getConstraintRegister for ARM and AArch64
targets. Since these targets don't have single-register constraints,
the implementation is trivial and just returns the register specified
in an asm label (if any).
Reviewers: eli.friedman, javed.absar, thopre
Reviewed By: thopre
Subscribers: rengolin, eraman, rogfer01, myatsina, kristof.beyls, cfe-commits, chrib
Differential Revision: https://reviews.llvm.org/D45965
llvm-svn: 331164
Dmitry Vyukov [Mon, 30 Apr 2018 07:28:45 +0000 (07:28 +0000)]
tsan: disable trace switching after multithreaded fork
The problem is reported in:
https://github.com/google/sanitizers/issues/945
We already disable as much as possible after multithreaded fork,
trace switching is last place that can hang due to basic
operations (memory accesses, function calls).
Disable it too.
llvm-svn: 331163
Sander de Smalen [Mon, 30 Apr 2018 07:24:38 +0000 (07:24 +0000)]
[AArch64][SVE] Asm: Improve diagnostics for gather loads.
This patch extends the 'isSVEVectorRegWithShiftExtend' function to
improve diagnostics for SVE's gather load (scalar + vector) addressing
modes. Instead of always suggesting the 'unscaled' addressing mode,
the use of DiagnosticPredicate enables a more specific error message
in the context where the scaling is incorrect. For example:
ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
^
shift amount should be '1'
Instead of suggesting the packed, unscaled addressing mode:
expected 'z[0..31].d, (uxtw|sxtw)'
the assembler now suggests using the proper scaling:
expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D46124
llvm-svn: 331162
Craig Topper [Mon, 30 Apr 2018 06:21:24 +0000 (06:21 +0000)]
[X86] Add a Requires<[In64BitMode]> to FARJMP64
Otherwise we can try to assemble it in 32-bit mode and throw an assert in the encoder.
llvm-svn: 331161
Craig Topper [Mon, 30 Apr 2018 06:21:23 +0000 (06:21 +0000)]
[X86] Hide another instruction from the assembly matcher table to avoid a duplicate entry. NFC
llvm-svn: 331160
Craig Topper [Mon, 30 Apr 2018 06:21:22 +0000 (06:21 +0000)]
[X86] Remove some InstAliases aren't needed because a MnemonicAlias makes them unreachable.
llvm-svn: 331159
Craig Topper [Mon, 30 Apr 2018 06:21:21 +0000 (06:21 +0000)]
[X86] Remove some instructions from the Intel assembly matcher table as there are equivalent mode aware InstAliases that conflict.
The instructions have predicates of Not64BitMode, but there are identical strings in InstAliases that have Mode32Bit and Mode16Bit. But the ordering is uncontrolled and the less specific Not64BitMode was ordered first.
This patch hides the Not64BitMode from the table so there is no conflict anymore.
llvm-svn: 331158
Craig Topper [Mon, 30 Apr 2018 06:21:19 +0000 (06:21 +0000)]
[X86] Use a MnemonicAlias instead of an InstAlias.
llvm-svn: 331157
Richard Smith [Mon, 30 Apr 2018 05:26:07 +0000 (05:26 +0000)]
Fix up after clang r331155.
llvm-svn: 331156
Richard Smith [Mon, 30 Apr 2018 05:25:48 +0000 (05:25 +0000)]
PR37189 Fix incorrect end source location and spelling for a split '>>' token.
When a '>>' token is split into two '>' tokens (in C++11 onwards), or (as an
extension) when we do the same for other tokens starting with a '>', we can't
just use a location pointing to the first '>' as the location of the split
token, because that would result in our miscomputing the length and spelling
for the token. As a consequence, for example, a refactoring replacing 'A<X>'
with something else would sometimes replace one character too many, and
similarly diagnostics highlighting a template-id source range would highlight
one character too many.
Fix this by creating an expansion range covering the first character of the
'>>' token, whose spelling is '>'. For this to work, we generalize the
expansion range of a macro FileID to be either a token range (the common case)
or a character range (used in this new case).
llvm-svn: 331155
Craig Topper [Mon, 30 Apr 2018 01:53:12 +0000 (01:53 +0000)]
[X86] Remove support for accepting 'fnstsw %eax' and 'fnstsw %al'.
I assume this was done because gas accepted it at one point, but current versions of gas don't.
llvm-svn: 331154
Craig Topper [Mon, 30 Apr 2018 01:53:10 +0000 (01:53 +0000)]
[X86] Mark some more InstAliases as 'att' syntax only.
These aliases are used to default the memory forms of call and jmp to the size of the operating mode. This doesn't work for Intel syntax. We have a different hack in the AsmParser code itself to force a size on unsized memory operands.
llvm-svn: 331153
Fangrui Song [Mon, 30 Apr 2018 00:34:09 +0000 (00:34 +0000)]
Rename DiagnosticClient to DiagnosticConsumer as per issue 5397.
llvm-svn: 331152
Nico Weber [Mon, 30 Apr 2018 00:08:06 +0000 (00:08 +0000)]
Remove a dead #ifdef.
Unix/Threading.inc should never be included on _WIN32. See also
https://reviews.llvm.org/D30526#1082292
llvm-svn: 331151
Nico Weber [Sun, 29 Apr 2018 23:05:11 +0000 (23:05 +0000)]
Move _LIBCPP_ENABLE_CXX17_REMOVED_UNEXPECTED_FUNCTIONS macro to build system
_LIBCPP_ENABLE_CXX17_REMOVED_UNEXPECTED_FUNCTIONS is currently used to
bring back std::unexpected, which is removed in C++17, but still needed
for libc++abi for backward compatibility.
This macro used to define in cxa_exception.cpp only, but actually
needed for all sources that touches exceptions.
So, a build-system-level macro is better fit to define this macro.
https://reviews.llvm.org/D46056
Patch from Taiju Tsuiku <tzik@chromium.org>!
llvm-svn: 331150
Craig Topper [Sun, 29 Apr 2018 22:55:54 +0000 (22:55 +0000)]
[X86] Make 64-bit sysret/sysexit not ambiguous in Intel assembly syntax.
This also makes it default to the 32-bit non REX.W version in 64-bit mode. This seems to be more consistent with gas.
llvm-svn: 331149
Jan Kratochvil [Sun, 29 Apr 2018 19:47:48 +0000 (19:47 +0000)]
Support reading section ".gnu_debugaltlink"
Differential revision: https://reviews.llvm.org/D40468
llvm-svn: 331148
Simon Pilgrim [Sun, 29 Apr 2018 18:18:51 +0000 (18:18 +0000)]
[X86] Remove unnecessary BT InstRW overrides.
llvm-svn: 331147
Sander de Smalen [Sun, 29 Apr 2018 18:18:21 +0000 (18:18 +0000)]
[AArch64][AsmParser] NFC: Cleanup of addOperands functions
Most of the add<operandname>Operands() functions are the same
and can be replaced by using a single 'RenderMethod' in
the AArch64InstrFormats.td file. Since many of the scaled
immediates (with different scaling/bits) are the same, most of
these can reuse the same AsmOperandClass.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: samparker
Differential Revision: https://reviews.llvm.org/D46122
llvm-svn: 331146
Sander de Smalen [Sun, 29 Apr 2018 17:33:38 +0000 (17:33 +0000)]
[AArch64][SVE] Asm: Support for gather LD1/LDFF1 (vector + imm) load instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46120
llvm-svn: 331145
Simon Pilgrim [Sun, 29 Apr 2018 15:45:31 +0000 (15:45 +0000)]
[llvm-mca][X86] Add BT resource tests to all models
llvm-svn: 331144
Simon Pilgrim [Sun, 29 Apr 2018 15:33:15 +0000 (15:33 +0000)]
[X86] Merge more instregex single matches to reduce InstrRW compile time.
llvm-svn: 331143
Simon Pilgrim [Sun, 29 Apr 2018 14:16:17 +0000 (14:16 +0000)]
[X86] Remove unnecessary add/adc+sub/sbb InstRW overrides.
llvm-svn: 331142
Dean Michael Berris [Sun, 29 Apr 2018 13:46:30 +0000 (13:46 +0000)]
[XRay][profiler] Part 1: XRay Allocator and Array Implementations
Summary:
This change is part of the larger XRay Profiling Mode effort.
Here we implement an arena allocator, for fixed sized buffers used in a
segmented array implementation. This change adds the segmented array
data structure, which relies on the allocator to provide and maintain
the storage for the segmented array.
Key features of the `Allocator` type:
* It uses cache-aligned blocks, intended to host the actual data. These
blocks are cache-line-size multiples of contiguous bytes.
* The `Allocator` has a maximum memory budget, set at construction
time. This allows us to cap the amount of data each specific
`Allocator` instance is responsible for.
* Upon destruction, the `Allocator` will clean up the storage it's
used, handing it back to the internal allocator used in
sanitizer_common.
Key features of the `Array` type:
* Each segmented array is always backed by an `Allocator`, which is
either user-provided or uses a global allocator.
* When an `Array` grows, it grows by appending a segment that's
fixed-sized. The size of each segment is computed by the number of
elements of type `T` that can fit into cache line multiples.
* An `Array` does not return memory to the `Allocator`, but it can keep
track of the current number of "live" objects it stores.
* When an `Array` is destroyed, it will not return memory to the
`Allocator`. Users should clean up the `Allocator` independently of
the `Array`.
* The `Array` type keeps a freelist of the chunks it's used before, so
that trimming and growing will re-use previously allocated chunks.
These basic data structures are used by the XRay Profiling Mode
implementation to implement efficient and cache-aware storage for data
that's typically read-and-write heavy for tracking latency information.
We're relying on the cache line characteristics of the architecture to
provide us good data isolation and cache friendliness, when we're
performing operations like searching for elements and/or updating data
hosted in these cache lines.
Reviewers: echristo, pelikan, kpw
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D45756
llvm-svn: 331141
Simon Pilgrim [Sun, 29 Apr 2018 11:03:25 +0000 (11:03 +0000)]
[llvm-mca][X86] Add add/adc + sub/sbb resource tests to all models
llvm-svn: 331140
Hideki Saito [Sun, 29 Apr 2018 07:26:18 +0000 (07:26 +0000)]
[NFC][LV][LoopUtil] Move LoopVectorizationLegality to its own file
Summary:
This is a follow up to D45420 (included here since it is still under review and this change is dependent on that) and D45072 (committed).
Actual change for this patch is LoopVectorize* and cmakefile. All others are all from D45420.
LoopVectorizationLegality is an analysis and thus really belongs to Analysis tree. It is modular enough and it is reusable enough ---- we can further improve those aspects once uses outside of LV picks up.
Hopefully, this will make it easier for people familiar with vectorization theory, but not necessarily LV itself to contribute, by lowering the volume of code they should deal with. We probably should start adding some code in LV to check its own capability (i.e., vectorization is legal but LV is not ready to handle it) and then bail out.
Reviewers: rengolin, fhahn, hfinkel, mkuper, aemerson, mssimpso, dcaballe, sguggill
Reviewed By: rengolin, dcaballe
Subscribers: egarcia, rogfer01, mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D45552
llvm-svn: 331139
Craig Topper [Sun, 29 Apr 2018 06:24:09 +0000 (06:24 +0000)]
[X86] Add suffixes to the LGDT/LIDT/SGDT/SIDT mnemonics in Intel syntax. Add aliases based on 16/32-bit mode to choose the default.
This allows the instruction selection to follow mode in Intel syntax. And allows a suffix to be used to change size.
This matches gas behavior from what I could tell.
llvm-svn: 331138
Richard Smith [Sun, 29 Apr 2018 05:33:38 +0000 (05:33 +0000)]
Fix printing of reference-to-reference types.
Previously we would sometimes print these as 'T &&&' or even 'T &&&&'.
llvm-svn: 331137
Richard Smith [Sun, 29 Apr 2018 04:55:46 +0000 (04:55 +0000)]
PR37275 packed attribute should not apply to base classes
Clang incorrectly applied the packed attribute to base classes. Per GCC's
documentation and as can be observed from its behavior, packed only applies to
members, not base classes.
This change is conditioned behind -fclang-abi-compat so that an ABI break can
be avoided by users if desired.
Differential Revision: https://reviews.llvm.org/D46218
llvm-svn: 331136
Craig Topper [Sun, 29 Apr 2018 04:50:53 +0000 (04:50 +0000)]
[X86] Remove SLDT64m instruction.
It doesn't really exist. The instruction always writes 16-bits of memory. Putting a REX.w on it won't change anything.
While I was touching the encoding tests to remove it, I added some other missing register form test cases.
llvm-svn: 331135
Craig Topper [Sun, 29 Apr 2018 04:06:02 +0000 (04:06 +0000)]
[X86] Remove unnecessary InstAliases. NFCI
These used to disambiguate MOV16ms/MOV16sm from other size instructions that no longer exist.
llvm-svn: 331134
Ed Maste [Sun, 29 Apr 2018 02:18:48 +0000 (02:18 +0000)]
Add -warn-backrefs (r329636) to lld's man page
llvm-svn: 331133
whitequark [Sun, 29 Apr 2018 02:01:34 +0000 (02:01 +0000)]
[LLVM-C] Eliminate an unused variable in a test.
This was introduced in r331123 and broke -Werror bots.
llvm-svn: 331132
Rafael Espindola [Sun, 29 Apr 2018 01:13:57 +0000 (01:13 +0000)]
Update my email address and description.
llvm-svn: 331131
Tobias Grosser [Sun, 29 Apr 2018 00:57:43 +0000 (00:57 +0000)]
Remove keep/take/give from isl C++ bindings
These functions have been legacy leftovers which we used before the
official C++ bindings existed. As all uses of these legacy functions
have been removed, this polly-specific extension can also be dropped.
llvm-svn: 331130
Tobias Grosser [Sun, 29 Apr 2018 00:57:38 +0000 (00:57 +0000)]
Remove another set or release() calls
llvm-svn: 331129
Craig Topper [Sun, 29 Apr 2018 00:53:10 +0000 (00:53 +0000)]
[X86] Use getX86SubSuperRegister in addGR32orGR64Operands in the AsmParser instead of duplicating its functionality. NFC
llvm-svn: 331128
Nico Weber [Sun, 29 Apr 2018 00:45:03 +0000 (00:45 +0000)]
s/LLVM_ON_WIN32/_WIN32/, llvm
LLVM_ON_WIN32 is set exactly with MSVC and MinGW (but not Cygwin) in
HandleLLVMOptions.cmake, which is where _WIN32 defined too. Just use the
default macro instead of a reinvented one.
See thread "Replacing LLVM_ON_WIN32 with just _WIN32" on llvm-dev and cfe-dev.
No intended behavior change.
This moves over all uses of the macro, but doesn't remove the definition
of it in (llvm-)config.h yet.
llvm-svn: 331127
Tobias Grosser [Sun, 29 Apr 2018 00:28:26 +0000 (00:28 +0000)]
Remove the last uses of isl::give and isl::take
llvm-svn: 331126
Tobias Grosser [Sun, 29 Apr 2018 00:28:14 +0000 (00:28 +0000)]
Fix one unit test
llvm-svn: 331125
Nico Weber [Sat, 28 Apr 2018 23:48:36 +0000 (23:48 +0000)]
Remove unused includes of clang/Config/config.h
Found by opening config.h.cmake in vim, finding all defined macros with
/define\(01\)\? \zs[A-Za-z0-9_]*<cr>
:%s//\=setreg('A', submatch(0), 'V')/gn<cr>
:put A<cr>
and then joining them all with |, and passing that to
git grep -E that_pattern 'clang/*.h' 'clang/*.cpp' 'clang/*.c'
and diffing that output with the result of
git grep Config/config.h 'clang/*.h' 'clang/*.cpp' 'clang/*.c'
No intended behavior change.
llvm-svn: 331124
Robert Widmann [Sat, 28 Apr 2018 22:32:07 +0000 (22:32 +0000)]
[LLVM-C] Add DIBuilder bindings to create import declarations
Summary: Add bindings to create import declarations for modules, functions, types, and other entities. This wraps the conveniences available in the existing DIBuilder API, but these seem C++-specific.
Reviewers: whitequark, harlanhaskins, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46167
llvm-svn: 331123
Tobias Grosser [Sat, 28 Apr 2018 22:11:55 +0000 (22:11 +0000)]
[DeLICM] Remove uses of isl::give
llvm-svn: 331122
Tobias Grosser [Sat, 28 Apr 2018 22:11:48 +0000 (22:11 +0000)]
[ZoneAlgo] Remove uses of isl::give - II
llvm-svn: 331121
Tobias Grosser [Sat, 28 Apr 2018 21:22:17 +0000 (21:22 +0000)]
[ZoneAlgo] Remove uses of isl::give
This moves more of Polly to islpp.
llvm-svn: 331120
Tobias Grosser [Sat, 28 Apr 2018 21:06:14 +0000 (21:06 +0000)]
[islpp] Remove use of isl::give from unittests
We do this mostly by just moving directly to pure C++ code.
llvm-svn: 331119