Wolfgang Denk [Mon, 18 Jul 2011 19:03:08 +0000 (21:03 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/p2041rdb: Add p2041rdb board support
powerpc/85xx: Fix detection of P1017E
powerpc/mpc8548cds: Remove incorrect DDR_MSYNC_IN erratum define
Mingkai Hu [Thu, 7 Jul 2011 04:29:15 +0000 (12:29 +0800)]
powerpc/p2041rdb: Add p2041rdb board support
P2041RDB Specification:
-----------------------
Memory subsystem:
* 4Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus)
* 128 Mbyte NOR flash single-chip memory
* 256 Kbit M24256 I2C EEPROM
* 16 Mbyte SPI memory
* SD connector to interface with the SD memory card
Ethernet:
* dTSEC1: connected to the Vitesse SGMII PHY (VSC8221)
* dTSEC2: connected to the Vitesse SGMII PHY (VSC8221)
* dTSEC3: connected to the Vitesse SGMII PHY (VSC8221)
* dTSEC4: connected to the Vitesse RGMII PHY (VSC8641)
* dTSEC5: connected to the Vitesse RGMII PHY (VSC8641)
PCIe:
* Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1
* Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2
SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors
USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces
I2C:
* I2C1: Real time clock, Temperature sensor, Memory module
* I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM, PCIe slot1/2
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 15 Jul 2011 15:11:44 +0000 (10:11 -0500)]
powerpc/85xx: Fix detection of P1017E
Had a typo such that P1017E would not be detected correctly.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
David A. Long [Sat, 9 Jul 2011 20:40:19 +0000 (16:40 -0400)]
Add uboot "fdt_high" enviroment variable
Add a new "fdt_high" enviroment variable. This can be used to control (or prevent) the
relocation of the flattened device tree on boot. It can be used to prevent relocation
of the fdt into highmem. The variable behaves similarly to the existing "initrd_high"
variable.
Signed-off-by: David A. Long <dave.long@linaro.org>
Gerald Van Baren [Fri, 15 Jul 2011 01:40:10 +0000 (21:40 -0400)]
fdt: introduce fdt_create_phandle()
The ePAPR specification says that phandle properties should be called
"phandle", and not "linux,phandle". To facilitate the migration from
"linux,phandle" to "phandle", introduce function fdt_create_phandle(),
which creates a phandle in a given node. For now, we create both the
"phandle" and "linux,phandle" properties. A later version of this
function will remove support for "linux,phandle".
Signed-off-by: Timur Tabi <timur@freescale.com>
Timur Tabi [Tue, 3 May 2011 18:35:10 +0000 (13:35 -0500)]
fdt: add prototype for fdt_increase_size()
Add a prototype for fdt_increase_size() so that anyone can call it.
Signed-off-by: Timur Tabi <timur@freescale.com>
Timur Tabi [Tue, 3 May 2011 18:24:07 +0000 (13:24 -0500)]
fdt: introduce fdt_verify_alias_address() and fdt_get_base_address()
Introduce two functions, fdt_verify_alias_address() and
fdt_get_base_address(), which can be used to verify the physical address
of a device in a device tree.
fdt_get_base_address() returns the base address of an SOC or PCI node.
fdt_verify_alias_address() prints a message if the address of a node
specified by an alias does not match the given physical address.
Signed-off-by: Timur Tabi <timur@freescale.com>
David Gibson [Tue, 9 Mar 2010 06:39:14 +0000 (17:39 +1100)]
libfdt: Implement property iteration functions
For ages, we've been talking about adding functions to libfdt to allow
iteration through properties. So, finally, here are some.
I got bogged down on this for a long time because I didn't want to
expose offsets directly to properties to the callers. But without
that, attempting to make reasonable iteration functions just became
horrible. So eventually, I settled on an interface which does now
expose property offsets. fdt_first_property_offset() and
fdt_next_property_offset() are used to step through the offsets of the
properties starting from a particularly node offset. The details of
the property at each offset can then be retrieved with either
fdt_get_property_by_offset() or fdt_getprop_by_offset() which have
interfaces similar to fdt_get_property() and fdt_getprop()
respectively.
No explicit testcases are included, but we do use the new functions to
reimplement the existing fdt_get_property() function.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This was extracted from the DTC commit:
73dca9ae0b9abe6924ba640164ecce9f8df69c5a Mon Sep 17 00:00:00 2001
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
David Gibson [Thu, 26 Nov 2009 04:37:13 +0000 (15:37 +1100)]
Support ePAPR compliant phandle properties
Currently, the Linux kernel, libfdt and dtc, when using flattened
device trees encode a node's phandle into a property named
"linux,phandle". The ePAPR specification, however - aiming as it is
to not be a Linux specific spec - requires that phandles be encoded in
a property named simply "phandle".
This patch adds support for this newer approach to dtc and libfdt.
Specifically:
- fdt_get_phandle() will now return the correct phandle if it
is supplied in either of these properties
- fdt_node_offset_by_phandle() will correctly find a node with
the given phandle encoded in either property.
- By default, when auto-generating phandles, dtc will encode
it into both properties for maximum compatibility. A new -H
option allows either only old-style or only new-style
properties to be generated.
- If phandle properties are explicitly supplied in the dts
file, dtc will not auto-generate ones in the alternate format.
- If both properties are supplied, dtc will check that they
have the same value.
- Some existing testcases are updated to use a mix of old and
new-style phandles, partially testing the changes.
- A new phandle_format test further tests the libfdt support,
and the -H option.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This was extracted from the DTC commit:
d75b33af676d0beac8398651a7f09037555a550b Mon Sep 17 00:00:00 2001
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
Becky Bruce [Wed, 13 Jul 2011 22:11:57 +0000 (17:11 -0500)]
powerpc/mpc8548cds: Remove incorrect DDR_MSYNC_IN erratum define
This erratum doesn't exist on this processor, and the workaround
spins on a non-existent register, causing boot to hang.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Ramneek Mehresh [Tue, 7 Jun 2011 10:10:43 +0000 (10:10 +0000)]
powerpc/85xx: Add default usb mode and phy type to hwconfig
Move to use hwconfig for usb mode & phy type instead of magic
'usb_phy_type' environment variable on the following platforms:
MPC8536DS, P1020RDB, P1020RDB-PC, P1010RDB, P2020RDB, P2020RDB-PC,
P2020RDB, P3041DS, P4080DS, & P5020DS.
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Thu, 30 Jun 2011 18:00:56 +0000 (11:00 -0700)]
powerpc/corenet_ds: add back buffer write for NOR flash
Enable buffer write for better performance. This platform uses a NOR flash
chip which supports write buffer programming. CFI driver can query the
buffer size and use it to program the flash for best performance.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Timur Tabi [Fri, 29 Apr 2011 16:37:43 +0000 (11:37 -0500)]
powerpc/85xx: remove SERDES4 soft-reset work-around
Some P4080 rev1 errata work-arounds, notably erratum SERDES4, required a
bank soft-reset after the bank was configured and enabled, even though
enabling a bank causes it to reset. Because the reset was required for
multiple errata, it was not properly enclosed in an #ifdef, and so was
not removed with all the other rev1 errata work-arounds.
Erratum SERDES-8 says that the clocks for bank 3 needs to be enabled if
bank 2 is enabled, but this was not being done for SERDES protocols 0xF
and 0x10. The bank reset also happened to enable bank 3 (apparently an
undocumented feature). Simply removing the reset breaks these two
protocols.
It turns out that every time we call enable_bank(), we do want at least
one lane of the bank enabled, either because the bank is supposed to be
enabled, or because we need the clock from that bank enabled.
For erratum SERDES-A001, we don't want to modify srds_lpd_b[] when we
call enable_bank(), because that array is used elsewhere to determine if
the bank is available.
Note that the side effect of these changes is that the work-arounds for
these two errata are now linked. Specifically, if SERDES-A001 is
enabled, then we need SERDES-8 enabled as well.
Because this was the only SERDES bank soft-reset, there is no need to
implement a work-around for erratum SERDES-A003.
Also fix an off-by-one error in a printf().
Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Ed Swarthout <swarthou@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Fri, 27 May 2011 05:44:28 +0000 (13:44 +0800)]
powerpc/mpc8xxx: Allow override DDR read-to-write turnaround time
Add this option to allow boards to override the default read-to-write
turnaround time for better performance.
Signed-off-by: York Sun <yorksun@freescale.com>
Ramneek Mehresh [Thu, 12 May 2011 14:00:36 +0000 (19:30 +0530)]
qoriq/p1_p2_rdb: USB device-tree fixups for P1020
Resolve P1020 second USB controller multiplexing with eLBC
- mandatory to mention USB2 in hwconfig string to select it
over eLBC, otherwise USB2 node is removed
- works only for SPI and SD boot
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Ramneek Mehresh [Mon, 7 Mar 2011 04:17:28 +0000 (22:17 -0600)]
powerpc/85xx: Specify hwconfig usage for USB controller
Specify hwconfig usage for USB mode and phy change
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Ramneek Mehresh [Wed, 8 Jun 2011 11:44:20 +0000 (17:14 +0530)]
powerpc/8xxx: Update USB mode device tree fixup
Modify support for USB mode fixup:
- Add common support for USB mode and phy type
device tree fix-up for all USB controllers
mentioned in hwconfig string
- Fetch USB mode and phy type via hwconfig; if not
defined in hwconfig, then fetch them from env
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Roy Zang [Thu, 9 Jun 2011 03:30:52 +0000 (11:30 +0800)]
powerpc/85xx: Add basic support for P1023RDS board
The P1023RDS board is the reference board for the P1023 SoC.
Add support for booting it from NOR or NAND, with fixed 2G of DDR, PCIe,
UART, I2C, etc.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Signed-off-by: Lei Xu <B33228@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Mon, 27 Jun 2011 20:30:55 +0000 (13:30 -0700)]
powerpc/mpc85xx: Display a warning for unsupported DDR data rates
If DDR initialziation uses a speed table and the speed is not matched,
print a warning message instead of silently ignoring.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Mon, 27 Jun 2011 20:39:15 +0000 (13:39 -0700)]
powerpc/corenet_ds: Fix RCW overriding for RDIMM
Allow overriding RCW for all RDIMM, not only quad-rank ones.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Mon, 27 Jun 2011 20:35:25 +0000 (13:35 -0700)]
powerpc/mpc8xxx: fix DDR data width checking
Checking width before setting DDR controller. SPD for DDR1 and DDR2 has
data width and primary sdram width. The latter one has different meaning
for DDR3.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Tue, 7 Jun 2011 01:42:17 +0000 (09:42 +0800)]
powerpc/mpc8xxx: Adding fallback to raw timing on supported boards
In case of empty SPD or checksum error, fallback to raw timing on
supported boards.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Tue, 7 Jun 2011 01:42:16 +0000 (09:42 +0800)]
powerpc/mpc8xxx: Enable calculation for fixed DDR chips
We used to have fixed parameters for soldered DDR chips. This patch
introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing
data from DDR chip datasheet, implemneted in board-specific files or header
files.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Felix Radensky [Mon, 27 Jun 2011 06:39:29 +0000 (09:39 +0300)]
powerpc/85xx: Fix pin muxing for second USB controller
On P1022/P1013 second USB controller is muxed with second
Ethernet controller. The current code to enable second USB
fails to properly clear pinmux bits used by ethernet. As a
result, Linux freezes when this controller is used. This
patch fixes the problem.
Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Thu, 26 May 2011 23:32:50 +0000 (07:32 +0800)]
Adding more SPD registers
Adding byte 32 and 33
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Thu, 26 May 2011 23:25:51 +0000 (07:25 +0800)]
powerpc/mpc8xxx: Add 16-bit support for DDR3
Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit
DDR devices.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Thu, 26 May 2011 23:25:50 +0000 (07:25 +0800)]
powerpc/mpc8xxx: check SPD length before using part number
Only use DDR DIMM part number if SPD has valid length, to prevent from
display garbage in case SPD doesn't cover these fields.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Thu, 26 May 2011 23:25:48 +0000 (07:25 +0800)]
powerpc/mpc8xxx: adjust DDR burst length and chop accroding to sdram width
If the bus width is 32-bit, burst chop should be disabled and burst length
should be 8. Read from SPD or other source to determine the width.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Timur Tabi [Thu, 28 Apr 2011 18:41:20 +0000 (13:41 -0500)]
powerpc/86xx: display boot device and bank on the MPC8610 HPCD
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Shaohui Xie [Mon, 9 May 2011 08:53:51 +0000 (16:53 +0800)]
powerpc/85xx: Add NAND boot support for P3041/P5020DS
When booting from NAND we get the environment and FMan ucode from NAND.
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 13 May 2011 06:16:07 +0000 (01:16 -0500)]
powerpc/85xx: Add P2041 processor support
The P2041 is similar to P2040, however has a 10G port and backside L2
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Mingkai Hu [Fri, 15 Apr 2011 07:18:03 +0000 (15:18 +0800)]
powerpc/p2040: Add various p2040 specific information
Add P2040 SoC specific information:
* LIODN setup
* Portal configuration
* etc
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Thu, 19 May 2011 21:15:11 +0000 (16:15 -0500)]
powerpc/85xx: Fix compile errors if CONFIG_SYS_DPAA_QBMAN isn't set
Add ifdef protection for qp_info and liodn associated with Q/BMan. Also
rearrange setting of _tbl_sz variables to utilize existing ifdef
protection for things like FMAN.
Also add protection around setup_portals() call in corenet_ds board
code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Ramneek Mehresh [Thu, 12 May 2011 14:01:42 +0000 (19:31 +0530)]
qoriq/p1_p2_rdb: Add Dual Role USB support macro for P1020RDB
Add CONFIG_HAS_FSL_DR_USB macro for P1020RDB
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 20 May 2011 05:54:39 +0000 (00:54 -0500)]
powerpc/85xx: Fix compile errors if CONFIG_SYS_{BR,OR}0_PRELIM aren't set
Add ifdef protection in LBC code to handle the case in which
CONFIG_SYS_BR0_PRELIM and CONFIG_SYS_OR0_PRELIM arent defined for a
build.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 20 May 2011 05:51:55 +0000 (00:51 -0500)]
powerpc/85xx: Fix compile errors if CONFIG_SYS_{B,Q}MAN_MEM_PHYS aren't set
Add ifdef protection in LAW & TLB code to handle the case in which
CONFIG_SYS_BMAN_MEM_PHYS or CONFIG_SYS_QMAN_MEM_PHYS arent defined for a
build.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Bill Cook [Wed, 25 May 2011 19:51:07 +0000 (15:51 -0400)]
MPC83XX: Fix PCI express clock setup
On a 8308 based board it was found that the PEX_GLK_RATIO register
(programmed in arch/powerpc/cpu/mpc83xx/pcie.c) was getting set to 0, This
was tracked to the fact that the pci express clock frequency was not being
assigned to the pciexp1_clk entry in the global data structure in file
arch/powerpc/cpu/mpc83xx/speed.c. Fix this and a similiar issue in
'do_clocks' command.
Signed-off-by: Bill Cook <cook@isgchips.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Timur Tabi [Thu, 28 Apr 2011 20:01:29 +0000 (15:01 -0500)]
powerpc/83xx: remove empty board_early_init_f()
Remove an empty board_early_init_f() from the MPC8323ERD and MPC360ERDK boards.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Andre Schwarz [Thu, 14 Apr 2011 13:11:44 +0000 (15:11 +0200)]
mpc83xx: Add support for MergerBox board
Includes board config file, documentation, maintainer and boards.cfg
entries, and board specific files in vendor dir.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Andre Schwarz [Thu, 14 Apr 2011 12:54:05 +0000 (14:54 +0200)]
MPC83xx: add config options for memory setup.
CPO value and driver strength settings are board specifc.
Also allow SPD data fetch from any accessible I2C EEPROM.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Andre Schwarz [Thu, 14 Apr 2011 12:53:37 +0000 (14:53 +0200)]
MPC83xx: add define for global half-strength enable (HSE)
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Andre Schwarz [Thu, 14 Apr 2011 12:57:40 +0000 (14:57 +0200)]
MPC837x: set i2c1_clk
Running on mpc837x without CONFIG_FSL_ESDHC leads to
i2c1_clk not being set at all. It is bound to clock
of encryption module. fix this.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Ira W. Snyder [Tue, 1 Mar 2011 22:40:55 +0000 (14:40 -0800)]
fsl_dma: fix support for 83xx DMA engine
Commit
359ec4931944adb885882deb9b781e4095eabc94 broke support for the
Freescale DMA engine on the 83xx parts. This is due to using registers
which do not exist on 83xx. Remove the attribute register accesses from
the 83xx build.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Cc: York Sun <yorksun@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Simon Guinot [Fri, 17 Jun 2011 14:11:33 +0000 (19:41 +0530)]
Add support for Network Space v2 and parents
This patch add support for the Network Space v2 board and parents, based
on the Marvell Kirkwood 6281 SoC. This include Network Space (Max) v2
and Internet Space v2.
Additional information is available at:
http://lacie-nas.org/doku.php?id=network_space_v2
Signed-off-by: Simon Guinot <sguinot@lacie.com>
Valentin Longchamp [Thu, 16 Jun 2011 12:41:15 +0000 (18:11 +0530)]
arm/km: add support for portl2 board
This adds support for the keymile Kirkwood BEC portl2 board. This board
relies on the km_arm (km_kirkwood) BEC.
The egiga driver is configured for a 100M full-duplex, A/N off connnection
to the backplane. This board has always ethernet present, because it is
connected to the marvell switch similar to mgcoge3un. The reset_phy
functionality is also the same to mgcoge3un.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>
Holger Brunck [Thu, 16 Jun 2011 12:41:15 +0000 (18:11 +0530)]
arm/km: replace suenx targets with km_kirkwood
suen3 and suen8 were in first HW version quite different, but
now they are from a u-boot point of view similar. So these
two boards can use the same header file. Other keymile boards
differ only in the usage of the PCI interface. Therefore
a target km_kirkwood_pci was introduced. All targets use
the same header file.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>
Valentin Longchamp [Thu, 16 Jun 2011 12:41:15 +0000 (18:11 +0530)]
arm/km: ethernet support for mgcoge3un
The phy is also configured with "RGMII clock transitions when data
stable" and "Class A driver for the direct backplane connection".
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>
Valentin Longchamp [Thu, 16 Jun 2011 12:41:15 +0000 (18:11 +0530)]
arm/km: use board KM_ENV_BUS for CONFIG_I2C_ENV_EEPROM_BUS
This is defined for all km_kirkwood boards and was not used up to now.
This value was the same for all boards but it could be changed for some
boards (and thus needs to be defined for every board).
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>
Holger Brunck [Thu, 16 Jun 2011 12:41:15 +0000 (18:11 +0530)]
arm/km: remove unneeded define
CONFIG_ENV_SIZE for NAND was later in this file overwritten
because we have the environment in i2c eeprom, so remove
this define.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>
Holger Brunck [Thu, 16 Jun 2011 12:41:15 +0000 (18:11 +0530)]
arm/km: fix u-boot.kwb build breakage
commit
010a958b
(arm/km: remove CONFIG_SYS_KWD_CONFIG from keymile-common.h)
breaks building keymile arm targets, when u-boot.kwb tries to
generate the binary with mkimage. A simple make <board> or MAKEALL
succeeded because it don't try to build the kirwood binary at the end.
Due this commit we use the CONFIG_SYS_KWD_CONFIG from the
arch-kirkwood/config.h and it was removed from the board config.
But it was forgotten to include the header. Now the header is included
in km_arm.h. Some other defines were obsolete due to this include,
these are also removed in this commit.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>
Holger Brunck [Thu, 16 Jun 2011 12:41:15 +0000 (18:11 +0530)]
arm/kirkwood: if CONFIG_SOFT_I2C is set don't set CONFIG_I2C_MVTWSI
Some boards e.g. keymile arm boards have CONFIG_CMD_I2C switched on
but they use soft i2c on kirkwood. So don't switch CONFIG_I2C_MVTWSI
on in this case.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
cc: Heiko Schocher <hs@denx.de>
Jens Scharsig [Tue, 28 Jun 2011 23:40:07 +0000 (23:40 +0000)]
Fix compiler error for cpu at91sam9, if lowlevel init is enabled
* Fix compiler error for cpu at91sam9, if lowlevel init is enabled
* use correct ATMEL_ name scheme to define ATMEL_BASE_SDRAMC
Signed-off-by: Jens Scharsig
Andreas Bießmann [Tue, 28 Jun 2011 04:15:58 +0000 (04:15 +0000)]
atstk100x: switch to common cfi driver
This patch removes the board implemenatation for flash driver which can now
safely switched to the common cfi driver.
Compile tested for all atstk100x boards, runtime tested on atstk1002.
Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
Andreas Bießmann [Sun, 12 Jun 2011 01:49:17 +0000 (01:49 +0000)]
driver/serial: delete at91rm9200_usart
The at91rm9200_usart driver could be fully replaced by atmel_usart driver.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Andreas Bießmann [Sun, 12 Jun 2011 01:49:16 +0000 (01:49 +0000)]
cpuat91: use atmel_usart
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Eric Bénard <eric@eukrea.com>
Andreas Bießmann [Sun, 12 Jun 2011 01:49:15 +0000 (01:49 +0000)]
eb_cpux9k2: use atmel_usart
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
CC: Jens Scharsig <js_at_ng@scharsoft.de>
Acked-by: Jens Scharsig<js_at_ng@scharsoft.de>
Tested-by: Jens Scharsig<js_at_ng@scharsoft.de> (for eb_cpux9k2 board)
Andreas Bießmann [Sun, 12 Jun 2011 01:49:14 +0000 (01:49 +0000)]
at91rm9200ek: use atmel_usart
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Andreas Bießmann [Sun, 12 Jun 2011 01:49:13 +0000 (01:49 +0000)]
arm920t/at91: add at91rm9200_devices.c
This is a copy of arm926ejs/at91 api for perpherial initialisation.
At the moment we just need the usart part of the api.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Andreas Bießmann [Sun, 12 Jun 2011 01:49:12 +0000 (01:49 +0000)]
arm920t/at91: use new clock.c features
This patch enables the new clock features from arm920t/at91/clock.c. This
is an required step to get at91rm9200_usart replaced by atmel_usart driver.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Jens Scharsig <js_at_ng@scharsoft.de>
Cc: Eric Bénard <eric@eukrea.com>
Andreas Bießmann [Sun, 12 Jun 2011 01:49:11 +0000 (01:49 +0000)]
arm920t/at91: add clock.c
This patch adds an copy of arm926ejs/at91/clock.c to arm920t/at91. The
arm926ejs specialities are removed from arm920t version and vice versa.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Andreas Bießmann [Sun, 12 Jun 2011 01:25:16 +0000 (01:25 +0000)]
at91rm9200.h: fix ATMEL_PMX_AA_TXD2
This patch sets the ATMEL_PMX_AA_TXD2 to the correct value.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
CC: Jens Scharsig <js_at_ng@scharsoft.de>
CC: eric@eukrea.com
Acked-by: Eric Bénard <eric@eukrea.com>
Fabio Estevam [Sat, 11 Jun 2011 17:41:53 +0000 (17:41 +0000)]
vision2: Fix build due to WEIM registers name change
commit
0015de1a (MX5: Make the weim structure complete) fixed the name for
the WEIM registers in order to match with the MX51/MX53 manuals.
Fix the WEIM register for vision2 board so that it can build again.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Tue, 7 Jun 2011 07:02:53 +0000 (07:02 +0000)]
MX53: Add initial support for MX53ARD
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Tue, 7 Jun 2011 07:02:52 +0000 (07:02 +0000)]
MX5: Introduce a function for setting the chip select size
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Tue, 7 Jun 2011 07:02:51 +0000 (07:02 +0000)]
MX5: Add iomux structure
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Tue, 7 Jun 2011 07:02:50 +0000 (07:02 +0000)]
MX5: Make the weim structure complete
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Matthias Weisser [Wed, 29 Jun 2011 02:08:07 +0000 (02:08 +0000)]
arm: Update jadecpu board
Enable dcache and arch memset/memcpy for speed reasons
Remove of config.mk and some environment overwrites
Some generic cleanup
Signed-off-by: Matthias Weisser <weisserm@arcor.de>
Igor Grinberg [Fri, 24 Jun 2011 09:34:38 +0000 (09:34 +0000)]
arm: omap2: apollon: fix broken build
Define CONFIG_SYS_SDRAM_BASE to physical SDRAM address
and CONFIG_SYS_INIT_SP_ADDR to physical SRAM address
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
John Rigby [Mon, 27 Dec 2010 14:33:10 +0000 (14:33 +0000)]
OMAP[34]: fix broken timer
As implemented now the timer used to implement __udelay counts
to 0xffffffff and then gets stuck there because the the programmed
reload value is 0xffffffff. This value is not only wrong but
illegal according to the reference manual.
One can reproduce the bug by leaving a board at the u-boot prompt
for sometime then issuing a sleep command. The sleep will hang
forever.
The timer is a count up timer that reloads as it rolls over
from 0xffffffff so the correct load value is 0.
Change TIMER_LOAD_VAL from 0xffffffff to 0 and introduce
a new constant called TIMER_OVERFLOW_VAL set to 0xffffffff.
Signed-off-by: John Rigby <john.rigby@linaro.org>
Tested-by: Igor Grinberg <grinberg@compulab.co.il>
Tom Warren [Fri, 17 Jun 2011 06:27:29 +0000 (06:27 +0000)]
arm: Tegra2: GPIO: enable GPIO for Tegra2 boards
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tom Warren [Fri, 17 Jun 2011 06:27:28 +0000 (06:27 +0000)]
GPIO: Tegra2: add GPIO driver for Tegra2
Signed-off-by: Tom Warren <twarren@nvidia.com>
David Müller (ELSOFT AG) [Sun, 1 May 2011 21:52:51 +0000 (21:52 +0000)]
VCMA9: various cleanups/code style fixes
Signed-off-by: David Müller <d.mueller@elsoft.ch>
David Müller (ELSOFT AG) [Sun, 1 May 2011 21:52:50 +0000 (21:52 +0000)]
VCMA9: use CFI driver (and remove the old one)
Signed-off-by: David Müller <d.mueller@elsoft.ch>
David Müller (ELSOFT AG) [Sun, 1 May 2011 21:52:49 +0000 (21:52 +0000)]
VCMA9: remove unneeded config.mk
Signed-off-by: David Müller <d.mueller@elsoft.ch>
Aneesh V [Thu, 16 Jun 2011 23:30:54 +0000 (23:30 +0000)]
armv7: adapt s5pc1xx to the new cache maintenance framework
adapt s5pc1xx to the new layered cache maintenance framework
Signed-off-by: Aneesh V <aneesh@ti.com>
Aneesh V [Thu, 16 Jun 2011 23:30:53 +0000 (23:30 +0000)]
armv7: adapt omap3 to the new cache maintenance framework
adapt omap3 to the new layered cache maintenance framework
Signed-off-by: Aneesh V <aneesh@ti.com>
Aneesh V [Thu, 16 Jun 2011 23:30:52 +0000 (23:30 +0000)]
armv7: adapt omap4 to the new cache maintenance framework
adapt omap4 to the new layered cache maintenance framework
Signed-off-by: Aneesh V <aneesh@ti.com>
Aneesh V [Thu, 16 Jun 2011 23:30:51 +0000 (23:30 +0000)]
armv7: add PL310 support to u-boot
PL310 is the L2$ controller from ARM used in many SoCs
including the Cortex-A9 based OMAP4430
Add support for some of the key PL310 operations
- Invalidate all
- Invalidate range
- Flush(clean & invalidate) all
- Flush range
Signed-off-by: Aneesh V <aneesh@ti.com>
Aneesh V [Thu, 16 Jun 2011 23:30:50 +0000 (23:30 +0000)]
arm: minor fixes for cache and mmu handling
1. make sure that page table setup is not done multiple times
2. flush_dcache_all() is more appropriate while disabling cache
than a range flush on the entire memory(flush_cache())
Provide a default implementation for flush_dcache_all()
for backward compatibility and to avoid build issues.
Signed-off-by: Aneesh V <aneesh@ti.com>
Aneesh V [Thu, 16 Jun 2011 23:30:49 +0000 (23:30 +0000)]
armv7: integrate cache maintenance support
- Enable I-cache on bootup
- Enable MMU and D-cache immediately after relocation
- Do necessary initialization before enabling d-cache and MMU
- Changes to cleanup_before_linux()
- Make changes according to the new framework
Signed-off-by: Aneesh V <aneesh@ti.com>
Aneesh V [Thu, 16 Jun 2011 23:30:48 +0000 (23:30 +0000)]
armv7: rename cache related CONFIG flags
Replace the cache related CONFIG flags with more meaningful
names. Following are the changes:
CONFIG_L2_OFF -> CONFIG_SYS_L2CACHE_OFF
CONFIG_SYS_NO_ICACHE -> CONFIG_SYS_ICACHE_OFF
CONFIG_SYS_NO_DCACHE -> CONFIG_SYS_DCACHE_OFF
Signed-off-by: Aneesh V <aneesh@ti.com>
V2:
* Changed CONFIG_L2_OFF -> CONFIG_SYS_NO_L2CACHE
V4:
* Changed all three flags to the final names suggested as above
and accordingly changed the commit message
Aneesh V [Thu, 16 Jun 2011 23:30:47 +0000 (23:30 +0000)]
armv7: cache maintenance operations for armv7
- Add a framework for layered cache maintenance
- separate out SOC specific outer cache maintenance from
maintenance of caches known to CPU
- Add generic ARMv7 cache maintenance operations that affect all
caches known to ARMv7 CPUs. For instance in Cortex-A8 these
opertions will affect both L1 and L2 caches. In Cortex-A9
these will affect only L1 cache
- D-cache operations supported:
- Invalidate entire D-cache
- Invalidate D-cache range
- Flush(clean & invalidate) entire D-cache
- Flush D-cache range
- I-cache operations supported:
- Invalidate entire I-cache
- Add maintenance functions for TLB, branch predictor array etc.
- Enable -march=armv7-a so that armv7 assembly instructions can be
used
Signed-off-by: Aneesh V <aneesh@ti.com>
Aneesh V [Thu, 16 Jun 2011 23:30:46 +0000 (23:30 +0000)]
arm: make default implementation of cache_flush() weakly linked
make default implementation of cache_flush() weakly linked so that
sub-architectures can override it
Signed-off-by: Aneesh V <aneesh@ti.com>
Kumar Gala [Thu, 30 Jun 2011 06:17:02 +0000 (01:17 -0500)]
Makefile: need to remove generated u-boot-nand_spl.lds
On MPC85xx based NAND_SPL builds we generate a u-boot-nand_spl.lds based
on output from preprocessor. We where never removed it.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Alex Waterman [Thu, 19 May 2011 19:08:36 +0000 (15:08 -0400)]
NAND: Add 16bit NAND support for the NDFC
This patch adds support for 16 bit NAND devices attached to the
NDFC on ppc4xx processors. Two config entries were added:
CONFIG_SYS_NDFC_16 - Setting this tells the NDFC that a
16 bit device is attached.
CONFIG_SYS_NDFC_EBC0_CFG - This is for the External Bus
Controller configuration register.
Also, a new ndfc_read_byte() function was added which does not
first convert the data to little endian.
The NAND SPL was also modified to do 16bit bad block testing
when a 16 bit chip is being used.
Signed-off-by: Alex Waterman <awaterman@dawning.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Ben Gardiner [Tue, 14 Jun 2011 20:35:07 +0000 (16:35 -0400)]
cmd_nand: add nand write.trimffs command
Add another nand write. variant, trimffs. This command will request of
nand_write_skip_bad() that all trailing all-0xff pages will be
dropped from eraseblocks when they are written to flash as-per the
reccommended behaviour of the UBI FAQ [1].
The function that implements this timming is the drop_ffs() function
by Artem Bityutskiy, ported from the mtd-utils tree.
[1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo
Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
CC: Artem Bityutskiy <dedekind1@gmail.com>
CC: Detlev Zundel <dzu@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Ben Gardiner [Tue, 14 Jun 2011 20:35:06 +0000 (16:35 -0400)]
nand_util: drop trailing all-0xff pages if requested
Add a flag to nand_read_skip_bad() such that if true, any trailing
pages in an eraseblock whose contents are entirely 0xff will be
dropped.
The implementation is via a new drop_ffs() function which is
based on the function of the same name from the ubiformat
utility by Artem Bityutskiy.
This is as-per the reccomendations of the UBI FAQ [1]
[1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo
Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
CC: Artem Bityutskiy <dedekind1@gmail.com>
Acked-by: Detlev Zundel <dzu@denx.de>
CC: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Ben Gardiner [Tue, 14 Jun 2011 20:35:05 +0000 (16:35 -0400)]
nand_util: treat WITH_YAFFS_OOB as a mode
When specified in the flags argument of nand_write, WITH_YAFFS_OOB causes an
operation which is mutually exclusive with the 'usual' way of writing.
Add a check that client code does not specify WITH_YAFFS_OOB along with any
other flags and add a comment indicating that the WITH_YAFFS_OOB flag should
not be mixed with other flags.
Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
CC: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Ben Gardiner [Tue, 24 May 2011 14:18:35 +0000 (10:18 -0400)]
nand_util: convert nand_write_skip_bad() to flags
In a future commit the behaviour of nand_write_skip_bad()
will be further extended.
Convert the only flag currently passed to the nand_write_
skip_bad() function to a bitfield of only one allocated
member. This should avoid an explosion of int's at the
end of the parameter list or the ambiguous calls like
nand_write_skip_bad(info, offset, len, buf, 0, 1, 1);
nand_write_skip_bad(info, offset, len, buf, 0, 1, 0);
Instead there will be:
nand_write_skip_bad(info, offset, len, buf, WITH_YAFFS_OOB |
WITH_OTHER);
Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Acked-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Ben Gardiner [Tue, 24 May 2011 14:18:34 +0000 (10:18 -0400)]
nand_base: trivial: fix comment read/write comment
Replace an incorrect 'read' with 'write' in a comment.
Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Acked-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Wolfgang Denk [Fri, 1 Jul 2011 07:42:25 +0000 (09:42 +0200)]
Merge branch 'next' of git://git.denx.de/u-boot-nios
* 'next' of git://git.denx.de/u-boot-nios:
nios2: move generic config to boards.cfg
Mike Frysinger [Mon, 27 Jun 2011 03:00:19 +0000 (23:00 -0400)]
nios2: move generic config to boards.cfg
I can't build test this, but just looking at the config files written
and it seems OK ...
Tested-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
Mike Frysinger [Mon, 9 May 2011 22:33:36 +0000 (18:33 -0400)]
cfi_flash: reverse geometry for newer STM parts
For newer STM parts where CFI >= 1.1, there is a byte in the extended
structure that declares the flash layout type (just like the AMD parts),
so key off of that to find out when we need to reverse the geometry.
This can be seen with M29W640 parts where U-Boot does:
Bank # 1: CFI conformant FLASH (16 x 16) Size: 8 MB in 135 Sectors
AMD Standard command set, Manufacturer ID: 0x20, Device ID: 0x22ED
Erase timeout: 8192 ms, write timeout: 1 ms
Buffer write timeout: 1 ms, buffer size: 16 bytes
Sector Start Addresses:
20000000 RO
20002000 RO
20004000 RO
20006000 RO
20008000 RO
2000A000 RO
2000C000 RO
2000E000 RO
20010000 RO
20020000 RO
...
But Linux does:
physmap platform flash device:
00800000 at
20000000
physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank.
Manufacturer ID 0x000020 Chip ID 0x0022ed
physmap-flash.0: Swapping erase regions for top-boot CFI table.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Stefan Roese <sr@denx.de>
Wolfgang Denk [Mon, 27 Jun 2011 20:22:42 +0000 (22:22 +0200)]
Prepare v2011.06
Signed-off-by: Wolfgang Denk <wd@denx.de>
Wolfgang Denk [Mon, 27 Jun 2011 20:20:37 +0000 (22:20 +0200)]
Minor coding style fixes.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Mike Frysinger [Sat, 25 Jun 2011 01:12:36 +0000 (21:12 -0400)]
usb: convert to partial linking
Looks like this was missed during the conversion to partial linking.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Zhao Chenhui [Tue, 19 Apr 2011 02:47:05 +0000 (10:47 +0800)]
ehci-pci: Fix PCI EHCI driver for 36-bit
Convert the PCI base address into a virtual address.
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Cliff Cai [Thu, 21 Apr 2011 16:42:10 +0000 (12:42 -0400)]
musb: process control messages after roothub accepted it
When dealing with non-multipoint devices, if the software root hub code
accepted the message, then we still need to process it normally. So only
return quickly when the root hub skipped the message or is otherwise in
an error state.
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Wolfgang Denk [Thu, 23 Jun 2011 13:37:33 +0000 (15:37 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
run arm_pci_init after relocation
IXP42x PCI rewrite
update/fix PDNB3 board
update/fix IXDP425 / IXDPG425 boards
add dvlhost (dLAN 200 AV Wireless G) board
IXP NPE: add support for fixed-speed MII ports
update/fix AcTux4 board
update/fix AcTux3 board
update/fix AcTux2 board
update/fix AcTux1 board
use -ffunction-sections / --gc-sections on IXP42x
support CONFIG_SYS_LDSCRIPT on ARM
fix "depend" target in npe directory
Fix IXP code to work after relocation was added
trigger hardware watchdog in IXP42x serial driver
add support for IXP42x Rev. B1 and newer
add XScale sub architecture (IXP/PXA) to maintainer list
Conflicts:
arch/arm/lib/board.c
Signed-off-by: Wolfgang Denk <wd@denx.de>
Michael Schwingen [Sun, 22 May 2011 22:00:13 +0000 (00:00 +0200)]
run arm_pci_init after relocation
Signed-off-by: Michael Schwingen <michael@schwingen.org>
projects / platform / kernel / u-boot.git / log