iris: Fix the constant data address calculation

In 536727c46517, we switched iris to patching the constant data address
into the shader but, thanks to my lack of understanding how iris works,
I got the calculation wrong.  I didn't realize, we needed to call
iris_bo_offset_from_base_address to get the BO offset from the start of
instruction state base address.

Fixes: 536727c465170c "iris: Patch constant data pointers into shaders"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3596
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6992>

nv50/ir: Initialize Source members.

Fix defects reported by Coverity Scan.

uninit_member: Non-static class member insns is not initialized in this
constructor nor in any functions that it calls.
uninit_member: Non-static class member clipVertexOutput is not
initialized in this constructor nor in any functions that it calls.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6769>

radv: Fix asserts using assign instead of compare.

Fix defects reported by Coverity Scan.

Assign instead of compare (PW.ASSIGN_WHERE_COMPARE_MEANT)
assign_where_compare_meant: use of "=" where "==" may have been
intended

Fixes: d8cdcd4adf7a ("radv: use syncobj for wsi fence")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6902>

lima: Print usage if --help is any of the arguments.

Fix defect reported by Coverity Scan.

Structurally dead code (UNREACHABLE)
unreachable: Since the loop increment n++; is unreachable, the loop body
will never execute more than once.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6906>

android: Disable the user XML config parsing.

The android platform is not interested in this feature of Mesa.  There are
currently workarounds for apps on Android, and no support for it in the
xmlconfig code.  Even if there we do need workarounds eventually, we'll
want to bake them in as structs rather than have this awkward external
dependency for parsing user-readable data installed by Mesa for
Mesa-internal details.

This gets rid of the expat dependency in the turnip driver.

Note that rather than have more #ifdefs in the file, I've opted to move
the code to have more logical locations since the structs refactor had
left less-used helpers scattered across the file.

Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6916>

util/xmlconfig: Drop use of XML_Char in parsing.

We don't define the use-16-bit-unicode defines (and our strings are plain
utf8), so it's just char.  This will let me use some of this code in the
absence of expat.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6916>

driconf: Stop quoting true/false in boolean option definitions.

Now that we're not trying to evade preprocessor macro expansion in
preprocessor string concatenation, we can use plain old bools in option
setup.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6916>

driconf: Make the driver's declarations be structs instead of XML.

We can generate the XML if anybody actually queries it, but this reduces
the amount of work in driver setup and means that we'll be able to support
driconf option queries on Android without libexpat.

This updates the driconf interface struct version for i965, i915, and
radeon to use the new getXml entrypoint to call the on-demand xml
generation.  Note that our loaders (egl, glx) implement the v2 function
interface and don't use .xml when that's set, and the X server doesn't use
this interface at all.

XML generation tested on iris and i965 using adriconf

Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6916>

driconf: Use DRI_CONF_OPT_I for remaining int options

Now that we have a single range in the option and start==end means "no
range", we can switch over these non-ranged int options.  This will ease
later refactors.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6916>

driconf: Delete disjoint range support.

The only user was radeon/r200, which was using it to have something that
looks a lot like an enum value return a float from the config option.
Just convert that option to a plain float value (for compat with existing
driconfs) with the min and max of its disjoint range as the range.  The
driver's option handling code already correctly deals with other values in
the range.

The disjoint range support was a bunch of extra parsing for this dead
driver, and made turning driconf into static structs difficult.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6916>

util/xmlconfig: Indent to Mesa style.

I'm heavily editing this code, and having Mesa's style not apply sucks.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6916>

util/xmlconfig: Drop silly open-coded strdup.

The comment about using "malloc"?  The strdup man page says 'Memory for
the new string is obtained with malloc(3), and can be freed with free(3)'

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6916>

driconf: Make a DRI_CONF_OPT_S() for string options.

This gets rid of most of the remaining special case option definitions.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6916>

r200: Reuse DRI_CONF_OPT_F for texture_blend_quality.

I missed this one in the nested macros conversion.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6916>

driconf: Fix extra quoting on "Jimenez'".

We're in a "" C string, no need to add extra '\'.  Fixes an extra '\' in
adriconf's interface.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6916>

driconf: Eliminate the DRI_CONF_OPT_BEGIN_B macro.

Since the nested-sections rework, this use in the testcase was the only
remaining one.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6916>

intel/fs: Don't use NoDDClk/NoDDClr for split SHUFFLEs

When I copied and pasted the code from MOV_INDIRECT for handling the
dependency controls, I missed a subtle difference between MOV_INDIRECT
and SHUFFLE.  Specifically, MOV_INDIRECT gets lowered to a narrow
instruction on Gen7 by the SIMD width lowering whereas SHUFFLE has to
split it in the generator.  Therefore, the check safety check for
whether or not we can use dependency control has to be based on the
lowered width rather than the width of the original instruction.

Fixes: a8ac61b0ee2fd "intel/fs: NoMask initialize the address..."
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3593
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6989>

android: util: add log.c to Makefile.sources

Fixes the following building errors:

external/mesa/src/intel/vulkan/anv_android.c:627: error: undefined reference to 'mesa_log'
...
external/mesa/src/intel/vulkan/anv_device.c:164: error: undefined reference to 'mesa_log'

Fixes: 13ea7db76 ("mesa: Promote Intel's simple logging façade for Android to util/")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6972>

panfrost: decode: Flag pandecode_log_typed() as PRINTFLIKE

This way we can catch mismatch between the format string and the
arguments.

Suggested-by: Kristian H. Kristensen <hoegsberg@google.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6886>

panfrost: decode: Fix decode_bifrost_constant() prototype

We expect a float, not an integer.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6886>

radv: Use atomics to read query results.

The volatile pattern gives me flaky results for 32-bit builds on
ChromeOS Android. This is because on 32-bit the volatile 64-bit
loads gets split into 2 32-bit loads each.

So if we read the lower dword first and then the upper dword, it
can happen that the upper dword is already changed but the lower
dword isn't yet. In particular for occlusion queries this gives
false readings, as the upper dword commonly only constains the
ready bit.

With the GCC atomic intrinsics we get a call to __atomic_load_8
in libatomic.so which does the right thing.

An alternative fix would be to  explicitly split the 32-bit loads
in the right order and do a bunch of retries if things change, though
that gets messy quickly and for 32-bit builds only doesn't feel worth
it that much.

CC: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6933>

pan/bi: Fix assert when writing vertex outputs

Varying stores require us to generate a LEA_ATTR_IMM instruction, which
is a load.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: 0aa08ae2f67 ("nir: Split NIR_INTRINSIC_TYPE into separate src/dest indices")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6985>

zink: use sizeof(vec4) multiplier for nir_lower_uniforms_to_ubo

we do everything ubo-related padded out to the size of a vec4, so ensure
that we're getting load offsets using the same alignment

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6981>

zink: correctly set up ubo bindings and buffer indices

var->data.binding is only set for vulkan drivers (though it also will
get incremented after nir_lower_uniforms_to_ubo), so we have to generate
our own values here.

to do this, we iterate backwards over the ubos to account for the
"first" ubos being at the end of the list, and we must also ensure that we
remap the buffer index correctly based on whether we're running our
nir_lower_uniforms_to_ubo pass

note that running nir_lower_uniforms_to_ubo unconditionally would require
us to add a number of checks in this patch for !shader->num_uniforms in
order to properly adjust to the altered instructions which become 1-indexed
instead of 0-indexed when this pass is run with no uniforms present

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6981>

zink: don't emit ubos or bindings for ubo variables

we want to only emit the full ubo block here to be used in the binding
table, not each ubo member variable, the likes of which are denoted by
having var->data.location != 0

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6981>

zink: emit ubo variables sized based on the overall ubo block size

if we're creating a block containing multiple variables, we want to create
the whole block at once, not just each individual variable, as we have no
way to reference individual variables in vulkan due to the requirement
for VkDescriptorSetLayoutBinding members to have different binding values

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6981>

zink: always emit descriptor set 0 in ntv

the nir_variable value is only set for vulkan drivers and will always
be 0 here

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6981>

zink: fix shader buffer size caps to use 65536

using max(Uniform|Storage)BufferRange yields some insane values that aren't
consistent with reality

affects PIPE_CAP_MAX_SHADER_BUFFER_SIZE and PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6981>

zink: run nir_lower_uniforms_to_ubo conditionally

if a shader has no uniforms then this pass just messes with the instructions
pointlessly and forces us to need workarounds later on in ntv

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6981>

zink: correctly handle ARB_arrays_of_arrays in ntv for samplers

this extension allows for array nesting with no clear limitations, so we need
to ensure that we use the "unrolled" array size in a couple places in order to
correctly bind and access these types of arrays in shaders

fixes spec@arb_separate_shader_objects@active sampler conflict and others

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6981>

aco/tests: add disassembler tests to reproduce the add3+clamp crash

Like some other v_add instructions, LLVM fails to disassemble
v_add3_u32 + clamp.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6961>

aco: apply the clamped integer addition disassembly workaround for v_add3

LLVM fails to disassemble v_add3 + clamp.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3563
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6961>

pan/mdg: map uabs_i/usub to i/uabsdiff

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6823>

pan/mdg: remove unused arg from ALU_CHECK_CMP and ALU_CASE_CMP

Since commit eb28a366 there's no need for the sext parameter.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6837>

aco: fix get_buffer_resource_flags()

Looks like a rebase error. After switching to derefs, we have to look
through a nir_op_mov.

fossil-db (Navi):
Totals from 846 (0.62% of 137413) affected shaders:
SGPRs: 36856 -> 44144 (+19.77%); split: -0.20%, +19.97%
VGPRs: 35968 -> 27852 (-22.56%); split: -22.64%, +0.08%
SpillSGPRs: 1366 -> 1662 (+21.67%); split: -0.95%, +22.62%
SpillVGPRs: 1909 -> 1893 (-0.84%)
CodeSize: 5209588 -> 5146536 (-1.21%); split: -1.89%, +0.68%
Scratch: 221184 -> 217088 (-1.85%)
MaxWaves: 11488 -> 14266 (+24.18%); split: +24.20%, -0.02%
Instrs: 994831 -> 974318 (-2.06%); split: -2.53%, +0.47%
Cycles: 45719692 -> 45843260 (+0.27%); split: -0.99%, +1.26%
VMEM: 147562 -> 94468 (-35.98%); split: +9.75%, -45.74%
SMEM: 32122 -> 66023 (+105.54%); split: +120.34%, -14.80%
VClause: 41051 -> 20565 (-49.90%); split: -50.00%, +0.09%
SClause: 18076 -> 40142 (+122.07%)
Copies: 100092 -> 103521 (+3.43%); split: -0.98%, +4.40%
Branches: 51244 -> 51533 (+0.56%); split: -0.02%, +0.58%
PreSGPRs: 32290 -> 34267 (+6.12%)
PreVGPRs: 27458 -> 25290 (-7.90%); split: -7.91%, +0.01%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: 05b6612b4ec ('radv: do not lower UBO/SSBO access to offsets')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6966>

nir: Add a pass to lower vec3s to vec4s

LLVM loves take advantage of the fact that vec3s in OpenCL are 16B
aligned and so it can just read/write them as vec4s.  This results in a
LOT of vec4->vec3 casts on loads and stores.  One solution to this
problem is to get rid of all vec3 variables.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6871>

nir/opt_deref: Add an optimization for bitcasts

LLVM loves take advantage of the fact that vec3s in OpenCL are 16B
aligned so it can just read/write them as vec4s.  This is questionably
legal except that it uses a xyz write-mask when it does it.  The result
is a LOT of vec4->vec3 casts on loads and stores.  This optimization
detects this case as well as other bit-cast cases and rewrites them to
get rid of the cast.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6871>

nir/opt_deref: Add an instruction type switch

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6871>

nir: Add component mask re-interpret helpers

These are based on the ones which already existed in the load/store
vectorization pass but I made some improvements while moving them.  In
particular,

 1. They're both faster if the bit sizes are equal
 2. The check is faster if old_bit_size > new_bit_size
 3. The check now fails if it would use more than NIR_MAX_VEC_COMPONENTS

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6871>

nir/opt_load_store_vectorize: Use bit sizes when checking mask compatibility

Without this, it was checking bit size compatibility with bit sizes such
as 96 which is clearly invalid.

No shader-db changes on Ice Lake

Fixes: ce9205c03bd20d "nir: add a load/store vectorization pass"
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6871>

nir: Add a memcpy optimization pass

This pass attempts to optimize three broad categories of memcpy:

 1. Self-copies: These we can discard out-of-hand.

 2. Vector copies: It doesn't matter what the vector size is or if the
    source and destination have different vector types, it's still easy
    enough to emit a load/store pair.

 3. Tightly packed copies:  In the case where a type is tightly packed
    (no padding bits), we can replace the memcpy with a copy_deref
    instruction which the optimizer is far better at handling.

This has proven capable of getting rid of many of the memcpy instances
in some rather gnarly OpenCL C kernels I've been looking at, even after
coming out of LLVM's optimizer.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6871>

nir: Handle memcpy in copy_prop_vars and combine_stores

Fixes: b2899f72657 "nir: Add a new memcpy intrinsic"
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6871>

nir/find_array_copies: Properly discard copies for casts

In 9f3c595dfc4cd, we attempted to handle casts in opt_find_array_copies
but missed a critical case.  In particular, in the case where we begin
finding a copy but then encounter a cast, we need to discard everything
which might alias that cast.

Fixes: 9f3c595dfc4cd "nir/find_array_copies: Handle cast derefs"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6871>

gallium/util: allow scissored blits for stencil-fallback

It's also useful to be able to use scissor-testing for fallback-blits,
as an CTS test-case does just that.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6960>

gallium/util: fix memory-leak

When I originally wrote this code, I forgot to release the views the
code creates, leaking a bit of memory that never gets cleaned up. That's
not great, so let's plug it.

Fixes: e8a40715a8b ("gallium/util: add blitter-support for stencil-fallback")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6960>

meson: fix power8 option

Do not throw a deprecation warning if the power8 option is set to the
new 'disabled' value. Instead, warn if it is still set to the legacy
value 'false'.

Fixes: 138c003d2273 ("meson: deprecated 'true' and 'false' in combo options for 'enabled' and 'disabled'")
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6370>

turnip: don't initialize GRAS_LRZ_CNTL/RB_LRZ_CNTL tu6_init_hw()

They will be initialized when emitting the draw state.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5146>

turnip: enable LRZ

v2:

* Use sub_cs when creating the IB in tu6_build_lrz(). (Jonathan Marek)
* Emit tu6_build_lrz() only when pipeline state changes or there is a
clear. (Jonathan Marek)

v3:

* Don't modify tu_pipeline object, track the changes in command buffer
state.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5146>

turnip: disable LRZ on vkCmdClearattachments() 3D fallback path

Partial clears are not supported and we may end up having LRZ enabled
from past commands.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5146>

turnip: disable LRZ on vkCmdClearAttachments()

We don't support partial clears on LRZ. Blob disables them too.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5146>

turnip: emit correct LRZ fast clear setup

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5146>

turnip: add support to clear LRZ

v2:

* Don't emit tu6_clear_lrz() using a IB but in the command stream
provided. (Jonathan Marek)
* Valid_clear_ib is always false if TU_DEBUG_NOLRZ is set. Remove the
useless condition. (Jonathan Marek)
* Added more comments.
* Use r2d function for blitting LRZ. (Jonathan Marek)

v3:
* Do LRZ tracking in the command buffer state (Connor).

v4:

* Simplify the emission of source setup (Jonathan Marek)

v5:

* Separate LRZ setup in a different function.
* Not hide LRZ setup inside GMEM path (Jonathan Marek)
* Fix iova address emission in tu6_clear_lrz() (Jonathan Marek)
* Add CCU sysmem flushes (Jonathan Marek)

v6:

* Fixed bug related to storing a VkClearValue pointer that could be
  out-of-scope when we access to it for emitting LRZ clear.

v7:

* Merge tu6_clear_lrz() and tu6_clear_lrz_setup() into the same
function and emit LRZ clear at the beginning of the renderpass.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5146>

turnip: add LRZ valid tracking for secondary command buffers

After a secondary command buffer is executed, LRZ is not valid
until it is cleared again.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5146>

turnip: add LRZ tracking to command buffer state

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5146>

turnip: disable LRZ depending on fragment changes

Disable LRZ write if the fragment shader discard the fragments, modify
its position or if early-Z is disabled.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5146>

turnip: disable LRZ writes when blend is enabled

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5146>

turnip: disable LRZ on specific cases

There are depth compare op modes that are not supported by LRZ in the
HW. Also, it is not supported when blend or stencil are enabled.

v2:

* Set pipeline->lrz.write to the same value than depthWriteEnable.
* Improve comment on disabling LRZ write on blend.
* Remove pipeline's lrz invalidation when there is no clear mask in
render pass. It is confusing. (Jonathan Marek)
* Mark the pipeline state as changed.
* Add comment on not using GREATER flag.

v3:

* Replace {rb,gras}_lrz_cntl by flags in struct tu_pipeline.
* Added z_test_enable flag.

v4:

* Created struct tu_lrz_pipeline to avoid modifying immutable objects.

v5:

* Fixed crashes when pDepthStencilState pointer is NULL.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5146>

turnip: create LRZ buffer

v2:
- Add missing vulkan subpass support. (Jonathan Marek)
- When creating the BO, mark it as not valid until it is cleared.
- Move LRZ struct to tu_image. (Jonathan Marek)
- Destroy BO when we destroy the image. (Jonathan Marek)

v3:
- Allocate the buffer as part of the image's BO (Connor)
- Moved image's LRZ values to its layout.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5146>

turnip: add environment variable to disable LRZ

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5146>

ci/bare-metal: Move the "POWER_GOOD not seen in time" check to the right time.

The poweron failure happens before we get to the bootloader
("load_archive: loading locale_en.bin") not after we're trying to boot the
kernel and we're waiting for the deqp run to complete.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6970>

nir: Fix a misspelling

Fixes: cb95065dd122a "nir: Add lowering from regular ALU conversions..."
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6975>

glsl: don't duplicate state vars as uniforms in the NIR linker

The linker was adding all state vars as uniforms, doubling the storage size
for shaders using only builtin uniforms, which increased CPU overhead for
constant buffer uploads.

When this code was originally ported from the GLSL IR linker we forgot
to exclude builtins because the check was not done in the
add_uniform_to_shader class but rather a check was done when passing
variables to this class for processing.

Fixes: 664e4a610dc8 ("glsl/nir: Fill in the Parameters in NIR linker")

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Tested-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6958>

freedreno/cffdec: fix decoding of bindless descriptors

Add ADDR suffix so that regbase() doesn't fail and return 0.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6968>

intel/fs: NoMask initialize the address register for shuffles

Cc: mesa-stable@lists.freedesktop.org
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2979
Tested-by: Iván Briano <ivan.briano@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6825>

virgl: fix stride + layer_stride inconsistency

With blob resources, stride doesn't necesarily have to
equal width * bpp.  The use case for this a minigbm blob
resource with blob mem BLOB_MEM_HOST3D_GUEST imported into
guest Mesa.  In addition, for BLOB_MEM_HOST we can repurpose
the transfer ioctls to also flush caches if need be, so this
seems a good time to fix this issue.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4821>

virgl: query blob mem

Resource blob also modifies resource info.  Let's use this
functionality.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4821>

virgl: support PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT

We should have GL4.5 with this.  Piglit tests should now pass.
In terms of performance, we're between 70% to 80% of host
performance on Iris, based on a apitrace of a 2013 GL4.5
game:

11.204 FPS (guest)
15.947 FPS (host)

This is still better than the status quo, when said game was unplayable
with Virgl due to an inefficient GL4.3 fallback.

TEST=piglit -t arb_buffer_storage all results/ passes

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4821>

virgl/drm: add resource create blob function

A blob resource is a container for:
  - VIRTGPU_BLOB_MEM_GUEST: a guest memory allocation
    (referred to as a "guest-only blob resource")

  - VIRTGPU_BLOB_MEM_HOST3D: a host3d memory allocation
    (referred to as a "host-only blob resource")

  - VIRTGPU_BLOB_MEM_HOST3D_GUEST: a guest + host3d memory allocation
    (referred to as a "default blob resource").

Blob resources can be used to implement new features and fix shortcomings
with the current resource create path.  The subsequent patches how
blob resources may be leveraged to implement GL_ARB_buffer_storage
and get GL4.5.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4821>

virgl/drm: query for resource blob and host visible memory region

Check for these features.

v2: refactor querying params in general (@shadeslayer)

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4821>

drm-uapi: virtgpu_drm.h: resource create blob + host visible memory region

Matches current API at virgl/resource_blob. Of course, don't
submit until this lands in drm.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4821>

virgl: add flags to (*resource_create) callback

We never seemed to use these. But for ARB_buffer_storage we'll
need it.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4821>

Revert F16C series (MR 6774)

This reverts commit 4fb2eddfdf9adafde2e6f94de23202ee44123d59.
This reverts commit 7a1deb16f8af4e0ae4ed64511cbfcc606087f0ee.
This reverts commit 2b6a17234376817e75d1f81edf5bd1b28eefb374.
This reverts commit 5af81393e419eaf086e4de2a1d149af78cd1f54d.
This reverts commit 87900afe5bbe90c5f3ad0921b28ae1c889029ada.

A couple of problems were discovered after this series was merged that
cause breakage in different configurations:

   (1) It seems that using -mf16c also enables AVX, leading to SIGILL on
   platforms that do not support AVX.
   (2) Since clang only warns about unknown flags, and as I understand
   it Meson's handling in cc.has_argument() is broken, the F16C code is
   wrongly enabled when clang is used, even for example on ARM, leading
   to a compilation error.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3583
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6969>

android: gallium/virgl: cleanup virgl_driinfo.h gen rules

Android.mk and Makefile.sources are still defining virgl_driinfo.h target
This patch removes the remaining gen rules

Fixes the following building error:

FAILED: out/target/product/x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_virgl_intermediates/virgl/virgl_driinfo.h
...
cp: bad 'out/target/product/x86_64/gen/STATIC_LIBRARIES/libmesa_pipe_virgl_intermediates/virgl/virgl_driinfo.h': No such file or directory

Fixes: 974981c4e6b9 ("gallium/drm: Make the pipe loader handle the driconf merging.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6880>

android: gallium/radeonsi: cleanup si_driinfo.h gen rules

Android.mk and Makefile.sources are still defining si_driinfo.h target
This patch removes the remaining gen rules

Fixes the following building error:

FAILED: out/target/product/x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_radeonsi_intermediates/radeonsi/si_driinfo.h
...
cp: bad 'out/target/product/x86_64/gen/STATIC_LIBRARIES/libmesa_pipe_radeonsi_intermediates/radeonsi/si_driinfo.h': No such file or directory

Fixes: 974981c4e6b9 ("gallium/drm: Make the pipe loader handle the driconf merging.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6880>

android: gallium/iris: cleanup iris_driinfo.h gen rules

Android.mk and Makefile.sources are still defining iris_driinfo.h target
This patch removes the remaining gen rules

Fixes the following building error:

FAILED: out/target/product/x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_iris_intermediates/iris/iris_driinfo.h
...
cp: bad 'out/target/product/x86_64/gen/STATIC_LIBRARIES/libmesa_pipe_iris_intermediates/iris/iris_driinfo.h': No such file or directory

Fixes: 974981c4e6b9 ("gallium/drm: Make the pipe loader handle the driconf merging.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6880>

nir: Add lowering from regular ALU conversions to the intrinsic

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6945>

clover/nir: Call nir_lower_convert_alu_types

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6945>

spirv: Implement vload[a]_half[n] and vstore[a]_half[n][_r]

Note, the aligned versions aren't handled specially yet.

The float16buffer capability is now at least partially supported after
this patch, so move it to be supported when kernels are supported.

v2 (Jason Ekstrand):
 - A few cosmetic cleanups around type/base_type
 - Rebased on top of the big SPIR-V SSA value rework
 - Use the new version of the conversion helpers

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6945>

spirv/opencl: Drop dest_type from handle_v_load_store

At that point in the function, we don't know if it's a load or a store
so calling it dest_type isn't really helpful.  Also, we don't really
want the glsl_type; we want the base_type.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6945>

spirv: Handle all OpenCL conversion ops with full rounding

This is done for kernels via the new convert_alu_types intrinsic.  For
Vulkan and OpenGL, we maintain the old path so that drivers don't have
to add that lowering pass.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6945>

spirv: Add some conversion handling helpers

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6945>

nir: Add a passes for nir_intrinsic_convert_alu_types

This adds primarily two passes:  One is a lowering pass which turns
these conversion intrinsics into a series of ALU ops.  The other is an
optimization pass which attempt to simplify the conversion whenever
possible in the hopes that we can turn it into a "normal" conversion op
which doesn't need special treatment.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6945>

nir: Add builder helpers for OpenCL type conversions

Most of these were originally written by Daniel Stone in the Microsoft
ClOn12 branch, reworked by Jesse Natalie, fixed by Boris Brezillon, and
possibly touched by others along the way.  Unfortunately, none of that
is in the commit history thanks to living in the CLOn12 branch.

I ported them to mesa master and further reworked things for better
cosmetics.  In particular,

 1. They now live in a builder helper rather than in vtn_alu.c.

 2. Instead of looping inside each builder helper, we just trust NIR
    vector instructions to handle vectors.

 3. Lots of re-arranging of the helpers for clarity, better asserting,
    and better re-use with the upcoming lowering pass.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6945>

nir: Add a conversion and rounding intrinsic

This new intrinsic is capable of handling the full range of conversions
from OpenCL including rounding modes and possible saturation.  The
intention is that we'll emit this intrinsic directly from spirv_to_nir
and then lower it to ALU ops later.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6945>

nir: Split NIR_INTRINSIC_TYPE into separate src/dest indices

We're about to introduce conversion ops which are going to want two
different types.  We may as well just split the one we have rather than
end up with three.  There are a couple places where this is mildly
inconvenient but most of the time I find it to actually be nicer.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6945>

gallivm/nir: fix non-32 bit find lsb/msb

fixes piglit cl get-global-id

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6954>

llvmpipe/cs: add in shader shared size.

(can remove lavapipe setting this later).

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6954>

gallivm/nir: make sure to mask global reads.

Make the driver only read values for the active lanes,
otherwise it can cause unwanted oob accesses that aren't
the apps fault.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6954>

intel/gen9: Enable MSC RAW Hazard Avoidance

Workaround # 22011374674
Applied to i965, iris and anv drivers
No performance impact is observed with WA.

Cc: mesa-stable
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radeonsi: restructure si_pipe_set_constant_buffer

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6948>

radeonsi: call nir_lower_bool_to_int32 last because it breaks nir_opt_if

The new place is where shader variants are generated.

This is a prerequisite for inlinable uniforms.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6948>

radeonsi: use staging buffer uploads for most VRAM buffers

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6948>

radeonsi: move si_set_active_descriptors_for_shader into si_update_common_shader_state

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6948>

radeonsi: kill disabled clip distances and planes at per-channel granularity

Apps often enable only 1 plane for gl_ClipVertex, which means 1 scalar
clip distance.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6948>

radeonsi: simplify NGG culling enablement and add radeonsi_shader_culling option

Add a vertex count threshold into si_shader_selector to simplify
the draw_vbo code.

The new option is supposed to be used in 00-mesa-defaults.conf and should be
tweaked for best performance unlike the AMD_DEBUG experimental options.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6948>

intel/blorp: Conditionally clear full surface depth and stencil

We should set "Full Surface Depth and Stencil Clear" field of WM_HZ_OP
3DSTATE packet, only when application requires the entire depth surface
to be cleared.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6549>

anv: Skip HiZ and CCS ambiguates which preceed fast-clears

This gets rid of multiple HiZ ambiguate operations per frame in
Witcher 3.

v2:
- Fix typo (Tapani)

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6549>

anv: Use more temp vars in cmd_buffer_begin_subpass

This is a mostly cosmetic change but there is one subtle functional
issue:  If we ever render to a 3D depth image, we are now handling the
base layer and number of layers correctly.  I'm not sure rendering to 3D
depth is even allowed but we can theoretically handle it now.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6549>

anv: Allow HiZ clears for multi-view

Now that we're enabling HiZ on multi-layer images, there's no reason why
we can't enable HiZ clears for multi-view.  The only reason I can think
of why we didn't before was because no one thought to and the old code
didn't.  Enabling this means that an attachment will get HiZ cleared if
and only if att_state->fast_clear.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6549>

radeonsi: support for external buffers (ext_external_objects)

So far, the callback to create a resource from a memory object had code
for importing textures only. Modified it to allow importing buffers too.

Fixes the following piglit tests:
- ext_external_objects/vk-buf-exchange
- ext_external_objects/vk-pix-buf-update-errors
- ext_external_objects/vk-vert-buf-update-errors
- ext_external_objects/vk-vert-buf-reuse

v2: Used si_alloc_buffer_struct instead of CALLOC
v3: Fixed indentation issue, removed free in case of unsuccessful
allocation, joined two if conditions together

Signed-off-by: Eleni Maria Stea <estea@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6364>