radeonsi: eliminate redundant TCS user data and RSRC2 register changes

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: move the only tcs_out_lds_offsets field to vs_state_bits

This removes 1 user data SGPR.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: replace tcs_out_lds_layout with nearly identical tes_offchip_addr

tcs_out_lds_layout is basically renamed to tes_offchip_addr in TCS, using
the same variable as TES and also using the same bit layout. The only
difference in the bit layout was that TCS had to mask out the low bits,
which this also removes.

The enums are renamed to *_SGPR_TCS_OFFCHIP_ADDR so as not to conflict
with *_SGPR_TES_OFFCHIP_ADDR, which are in different user data SGPRs.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: move TCS.gl_PatchVerticesIn into the tcs_offchip_layout SGPR

we'll be able to remove 1 TCS user data SGPR thanks to this

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

zink/ci: remove 3 tests from the fails list

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23789>

amd/ci: temporarily disable some manual jobs that take a long time to run

We are trying to re-enable the valve CI... but doing so runs all the
jobs, including the manual ones.

Since some can take over an hour to run, let's disable them, and
re-enable them in another MR by reverting this commit.

Sorry for the noise!

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23789>

Revert "ci: mark the valve farm as down"

Fixed by rebooting the gateway. A post-mortem analysis will be
performed to figure out what happened!

This reverts commit 2089fc8188635ed0ee72e2ddc009e7a775210bb7.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23789>

nir_opt_algebraic: don't use i32csel without native integer support

Otherwise nir_lower_int_to_float (or specifically nir_gather_ssa_types)
will fail to recognize we already have float constants and converts them
again.

Example from spec/glsl-1.10/execution/vs-loop-array-index-unroll.shader_test
with r300 driver (after enabling has_fused_comp_and_csel).

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = load_const (0x00000000 = 0.000000)
        vec4 32 ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32, io location=VERT_ATTRIB_POS slots=1)      /* gl_Vertex */
        vec3 32 ssa_2 = load_const (0x00000000, 0x3e800000, 0x3f800000) = (0.000000, 0.250000, 1.000000)
        vec3 32 ssa_3 = load_const (0x00000000, 0x3f000000, 0x3f800000) = (0.000000, 0.500000, 1.000000)
        vec3 32 ssa_4 = load_const (0x00000000, 0x3f400000, 0x3f800000) = (0.000000, 0.750000, 1.000000)
        vec2 32 ssa_5 = load_const (0x00000000, 0x3f800000) = (0.000000, 1.000000)
        vec1 32 ssa_6 = load_const (0x3f800000 = 1.000000)
        vec1 32 ssa_7 = intrinsic load_ubo_vec4 (ssa_0, ssa_0) (access=0, base=0, component=0)
        vec4 32 ssa_8 = load_const (0x00000000, 0x00000001, 0x00000002, 0x00000003) = (0.000000, 0.000000, 0.000000, 0.000000)
        vec4  1 ssa_9 = ilt ssa_8, ssa_7.xxxx
        vec3 32 ssa_10 = bcsel ssa_9.www, ssa_5.xyy, ssa_4
        vec3 32 ssa_11 = bcsel ssa_9.zzz, ssa_10, ssa_3
        vec3 32 ssa_12 = bcsel ssa_9.yyy, ssa_11, ssa_2
        vec3 32 ssa_15 = i32csel_gt ssa_7.xxx, ssa_12, ssa_6.xxx
        vec4 32 ssa_14 = fsat ssa_15.xyxz
        intrinsic store_output (ssa_14, ssa_0) (base=1, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_COL0 slots=1, xfb(), xfb2())       /* gl_FrontColor */
        intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_POS slots=1, xfb(), xfb2()) /* gl_Position */
        /* succs: block_1 */
        block block_1:
}

and after nir_lower_int_to_float

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = load_const (0x00000000 = 0.000000)
        vec4 32 ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32, io location=VERT_ATTRIB_POS slots=1)      /* gl_Vertex */
        vec3 32 ssa_2 = load_const (0x00000000, 0x4e7a0000, 0x4e7e0000) = (0.000000, 1048576000.000000, 1065353216.000000)
        vec3 32 ssa_3 = load_const (0x00000000, 0x4e7c0000, 0x4e7e0000) = (0.000000, 1056964608.000000, 1065353216.000000)
        vec3 32 ssa_4 = load_const (0x00000000, 0x4e7d0000, 0x4e7e0000) = (0.000000, 1061158912.000000, 1065353216.000000)
        vec2 32 ssa_5 = load_const (0x00000000, 0x4e7e0000) = (0.000000, 1065353216.000000)
        vec1 32 ssa_6 = load_const (0x4e7e0000 = 1065353216.000000)
        vec1 32 ssa_7 = intrinsic load_ubo_vec4 (ssa_0, ssa_0) (access=0, base=0, component=0)
        vec4 32 ssa_8 = load_const (0x00000000, 0x3f800000, 0x40000000, 0x40400000) = (0.000000, 1.000000, 2.000000, 3.000000)
        vec4  1 ssa_9 = flt ssa_8, ssa_7.xxxx
        vec3 32 ssa_10 = bcsel ssa_9.www, ssa_5.xyy, ssa_4
        vec3 32 ssa_11 = bcsel ssa_9.zzz, ssa_10, ssa_3
        vec3 32 ssa_12 = bcsel ssa_9.yyy, ssa_11, ssa_2
        vec3 32 ssa_13 = fcsel_gt ssa_7.xxx, ssa_12, ssa_6.xxx
        vec4 32 ssa_14 = fsat ssa_13.xyxz
        intrinsic store_output (ssa_14, ssa_0) (base=1, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_COL0 slots=1, xfb(), xfb2())       /* gl_FrontColor */
        intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_POS slots=1, xfb(), xfb2()) /* gl_Position */
        /* succs: block_1 */
        block block_1:
}

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23704>

docs/ci: fix command to disable/re-enable farms

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23780>

r600/sfn: Add source mod propagation also to fp64 ops

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23754>

r600/sfn: Implement fsat for 64 bit ops

Because a plain mov with the fsat modifier doesn't do a proper 64 bit fsat
we either have to propagate the op as modifier to the instruction that
creates the value, or we add a fake op that applies the fsat op, i.e. we
implement the mov as an add_64 with zero as the second value.

Fixes:  0ff3c4bef21e6768a53610337c39d1e306b3869e
    r600/sfn: drop use of nir source mods

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23754>

anv: update conformanceVersion

The Vulkan CTS started generating the list of valid versions the driver
can report as conformant against based on the active branches, and the
1.3.0 branch we were reporting up to now is no longer valid.

Fixes dEQP-VK.api.driver_properties.conformance_version

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23784>

dzn: Align placed footprints used when copying linear <-> optimal for BC formats

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23662>

ci: move .microsoft-farm-container-rules to test-source-dep.yml

farm rules are placed on test-source-dep.yml, so move it there.

This is also useful when trying to re-use the container/gitlab-ci.yml to
other workflows without running the jobs.

Signed-off-by: Helen Koike <helen.koike@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23731>

nir/lower_tex: ignore saturate for txf ops

saturate is used for GL_CLAMP emulation, and GL_CLAMP cannot be used
with txf

ref #9226

cc: mesa-stable

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23750>

zink: add fastpaths for no-op sampler/view rebinds

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

zink: check sampler views pointer before loop

this doesn't need to be checked in every loop iteration

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

zink: don't update tc info directly from cso binds

this somehow becomes expensive at extremely high fps, so defer
until rp begin to check layout change state

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

zink: track and apply ds3 states only on change

drivers don't do their own state tracking, so ensure the calls are only
made when necessary

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

zink: use local screen var in blend state bind

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

zink: clean up rp update tracking on dsa bind

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

zink: specialize invalidate_descriptor_state hook for compact mode

the constant flag check here has perf implications at high fps,
so avoid it when possible

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

zink: make invalidate_descriptor_state a ctx hook

this will allow for specialization

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

zink: force inlining for a bunch of functions

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

zink: no-op redundant samplemask changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

dzn: Fix multisample counts in device limits

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23658>

dzn: Remove dynamic check for block-compressed support

None of this is optional in D3D

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23658>

dzn: Use common GetPhysicalDeviceFeatures2

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23658>

dzn: Inline D3D12 device creation in physical device creation

This was effectively happening *anyway* because WSI init was calling
functions that needed a D3D12 device around to be able to answer.
Just remove the whole song and dance of maybe not having a device.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23658>

util: reinstate ENUM_PACKED

gets rid of warning: 'gcc_struct' attribute ignored [-Wattributes] introduced by !23338

Fixes: 86532fa21de ("util: Use the gcc_struct attribute for packed structures in mingw")
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23478>

egl/haiku: Fix potential crash if double buffering is disabled

* Don't assume the existence of the back buffer in swap_buffers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23556>

ci: mark the valve farm as down

docker daemon is down on mupuf-gfx10-vangogh-{1..3}

Signed-off-by: Eric Engestrom <eric@igalia.com>

intel/fs: Add missing newline

Emacs will add a newline to the end of this file whether I've edited
that line or not. It was driving me up the wall, so... yeah.

Trivial.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23777>

radv: inline radv_can_enable_dual_src()

this is unexpectedly heavy

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23601>

radv: remove redundant intermediate variable in radv_is_mrt0_dual_src()

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23601>

dzn: Ignore export access parameters

D3D requires these to just be GENERIC_ALL. Fixes some sharing tests.

Fixes: c64f1b66 ("dzn: Hook up win32 semaphore import/export")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23772>

asahi: drop unnecessary DRM_FORMAT_MOD_{LINEAR,INVALID} fallbacks

Since afe134a49c ("asahi: Drop macOS backend"), `drm_fourcc.h` is
unconditionally included, meaning these defines are now dead code.

Fixes: afe134a49c5ef79ca612 ("asahi: Drop macOS backend")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23773>

aco: don't set exec_hi for wave32 scan reductions

fossil-db (wave32):
Totals from 21 (0.02% of 133428) affected shaders:
Instrs: 10778 -> 10712 (-0.61%)
CodeSize: 56604 -> 56208 (-0.70%)
Latency: 168293 -> 168251 (-0.02%)
InvThroughput: 25256 -> 25253 (-0.01%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23745>

pvr: Fix csb control stream extension

Previously we reserved space for a stream link and whenever we ran
out of space in the current bo, allocated a new one, and emitted a
link to it. This is problematic as stream links can only be emitted
at state update boundaries so the handling could have produced a
corrupted control stream.

That's fixed by using a `relocation_mark` set by the driver to
indicate where a state update was last started, so csb can relocate
the whole update into the new bo and link to it.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23520>

intel/fs: Constant propagate into SHADER_OPCODE_SHUFFLE

Code already exists to convert SHADER_OPCODE_SHUFFLE into a simple MOV
when either source is constant. However... the constants have to
actually get into those sources!

On a shader that I'm working on that multiplies very large matrices using
lots of subgroup operations,

-SIMD8 shader: 1378 instructions. 3 loops. 793896 cycles. 0:0 spills:fills, 23 sends, scheduled with mode non-lifo. Promoted 0 constants. Compacted 22048 to 21664 bytes (2%)
+SIMD8 shader: 346 instructions. 3 loops. 61742 cycles. 0:0 spills:fills, 23 sends, scheduled with mode top-down. Promoted 0 constants. Compacted 5536 to 5216 bytes (6%)

No changes in shader-db or fossil-db on any Intel platform.

v2: Merge a bunch of identical cases. Suggested by Ken.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> [v1]
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23609>

pvr: Fix dynamic offset patching

Previously the set of dynamic offsets were being reused per each
binding. That's now fixed, by using an offset to determine where
each binding's dynamic offsets reside.

Tests fixed:
  dEQP-VK.binding_model.descriptor_copy.{compute,graphics}
    .{uniform,storage}_buffer_dynamic_0

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Fixes: aa791961a82e ("pvr: Add support for dynamic buffers descriptors")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23587>

pvr: Fix barrier insertion on merged subpasses

The driver can merge subpasses within a render pass into a single
hw render. While doing so it makes the assumption that the subpasses
in an hw render will all be submitted in a single job.

On vkCmdPipelineBarrier() the driver was previously incorrectly
inserting an event sub-cmd on a merged subpass, breaking that
assumption leading to incorrect values for input attachments.

Signed-off-by: Soroush Kashani <soroush.kashani@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Fixes: 6d672e033683 ("pvr: Add initial vkCmdPipelineBarrier skeleton.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23693>

pvr: Fix seg fault on empty descriptor set

Vulkan allows empty descriptor sets to be created. When we setup
the descriptor set addresses table we fill in the address of the
`bo` for each valid/currently bound desc set. For empty desc sets
there is no `bo` which was causing a seg fault. Now skip them,
leaving their address set to `~0`.

Reported-by: Simon Perretta <simon.perretta@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Fixes: ce67f5ac944 ("pvr: Write descriptor set addrs table dev addr into shareds")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23692>

radv: Move most of DB_SHADER_CONTROL to PS, more precise GFX11 blend WA

Move most of the DB_SHADER_CONTROL fields from the pipeline to the pixel
shader for preparation for shader objects.

Also, the GFX11 export conflict bug workaround doesn't need to be enabled
for non-1x sample counts or if blending is not enabled, so make the
application of DB_SHADER_CONTROL consider the current sample count and
blending state even if they're dynamic.

Having access to the exact sample count in DB_SHADER_CONTROL setup is also
necessary for good performance in SampleInterlock execution modes of
fragment shader interlock, for configuration of POPS_OVERLAP_NUM_SAMPLES
(GFX9-10.3) or OVERRIDE_INTRINSIC_RATE (GFX11), as PixelInterlock is
massively slower with multisampling due to overlap between adjacent
polygons sharing covered pixels among the common edge.

The name of the dynamic state controlling DB_SHADER_CONTROL is now
unambiguous - previously line rasterization mode had effect on attachment
feedback loop state emission.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23474>

isl: add surface creation reporting mechanism

We have a number of users reporting surface creation issues with
modifiers etc...

This makes Anv & Iris printout the reason of the failure with
INTEL_DEBUG=isl Failure example in Iris :

MESA: debug: ISL surface failed: ../src/intel/isl/isl.c:1729: requested row pitch (42B) less than minimum alignment requirement (1024B) extent=160x160x1 dim=2d msaa=1x levels=1 rpitch=42 fmt=B8G8R8X8_UNORM usage=+rt+tex+disp

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14039>

isl: assert on gfx8 condition that should not be met

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14039>

isl: assert on gfx7 condition that should not be met

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14039>

isl: assert on gfx6 condition that should not be met

Those 2 cases should have been handled earlier.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14039>

zink: radv vangogh ci updates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23729>

zink: always clamp NUM_QUERIES to 500

this avoids ooming on some weaker GPUs with big query energy

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23729>

zink: recache present semaphores

this otherwise depletes the entire cache

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23729>

zink: acquire persistently bound swapchain descriptors before setting usage

if a swapchain image is bound as a sampler across batches then it needs
to be acquired again before it is used

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23729>

zink: fix ubo array sizing in ntv

there are only 2 ubos that can be emitted, except the emitted ubos
can start at an offset based on the first-used ubo, which means this
has to support the full range of ubo indices

fixes oob access in game Beyond All Reason

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23729>

vulkan/video: consider removed bits when calculating the size of comsumed data.

Closes: mesa/mesa#9170

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23688>

util/rbsp: keep track of removed bits for the emulation
 prevention three bytes.

This is needed for the next patch to fix a way to get how much data
is comsumed in rbsp by considering cases of removed bits for emulation
prevention three bytes.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23688>

vulkan/video: move parsing longterm rps in h265 slice parsing.

It was just by mistake.

Fixes: efdcacb230 ("vulkan/video: add to parse h265 slice.")

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23688>

vulkan/video: adds more conditions for setting loop_filter_across_slices_enable in h265 slice parsing.

Fixes: efdcacb230 ("vulkan/video: add to parse h265 slice.")

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23688>

radv/rt: Store the prolog outside the shaders array

Avoids including it in executable statistics queries.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23524>

radv: Use _mesa_shader_stage_to_string for executable name

We can not use it for all stages because RADV has some special stages
and shader-db doesn't handle all stages.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23524>

radv: Implement executable properties for ray tracing stages

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23524>

radv: Use get_shader_from_executable_index for executable properties

This will make handling ray tracing pipelines easier.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23524>

radv: Adjust the traversal shader description

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23524>

radv: Move the shader type to radv_shader_info

Since the default value is 0, this removes some boilerplate.
Moving it to the shader info also makes it accessible using
radv_shader.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23524>

intel/compiler: add more validation for acc register usage

This is described in Wa_14014617373 and a programming note has
been added to specification.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23682>

radv: enable NV_device_generated_commands on GFX6

Now that GFX6 supports IBs, DGC can also be enabled.
Pass all vkd3d-proton tests on Pitcairn.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23689>

radv: implement padding cmdbuffer for DGC on GFX6

GFX6 only supports PKT2_NOP_PAD.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23689>

util: Fixes prototype of threads_timespec_compare

using const struct timespec * is enough

Fixes: 45bd24708a9 ("c11: Improve mtx_timedlock to use timespec_get instead of time(NULL)")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9230

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Tested-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23753>

radv/video: drop incorrect defines for uapi ones.

I missed there's an off by one, and found the kernel defined
the correct bits, so just use that.

Fixes: 9477f117f4d4 ("radv/video: add initial frameworking.")
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23757>

intel/stub_gpu: Don't run program again after using GDB

Fixes: c56dd678e48 ("intel/stub_gpu: add an option to launch valgrind")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23736>

util/blitter: fix util_blitter_clear_buffer() refcnt imbalance

Indeed, the vertex state was restored using a specific
condition at the util_blitter_restore_vertex_states()
level. This change ensures that the condition is the
same when the vertex state is saved.

The function util_blitter_clear_buffer() is only called
by the r600 driver on pre-evergreen gpus.

This issue is triggered on a rv770 gpu with "piglit/bin/fbo-1d -auto -fbo"
or "piglit/bin/draw_buffers_gles2 -auto -fbo"
while setting GALLIUM_REFCNT_LOG=refcnt.log.

Fixes: 5f566faa4607 ("radeonsi: don't save and restore vertex buffers and elements for u_blitter")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23721>

zink: only retry bo allocation after reclaim if reclaims actually happened

this should cut down on allocation error spam

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23073>

aux/pipebuffer: add a return to pb_cache_release_all_buffers()

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23073>

aux/pipebuffer: add a return to pb_slabs_reclaim()

this lets drivers determine whether any reclaims have happened

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23073>

intel/compiler: Respect NIR_DEBUG_PRINT_INTERNAL flag

If flag is not set, don't print debugging
information for internal shaders.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23756>

nir/print: Print whether the shader is internal or not

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23756>

rusticl/memory: fix clippy errors

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23755>

aco/gfx11: schedule for VMEM store clauses

fossil-db (gfx1100):
Totals from 49486 (37.09% of 133428) affected shaders:
Instrs: 18376819 -> 18480712 (+0.57%); split: -0.00%, +0.57%
CodeSize: 91810836 -> 92227292 (+0.45%); split: -0.00%, +0.45%
VGPRs: 2031824 -> 2047784 (+0.79%); split: -0.02%, +0.81%
Latency: 104259318 -> 103804792 (-0.44%); split: -0.44%, +0.00%
InvThroughput: 16388760 -> 16399819 (+0.07%); split: -0.13%, +0.19%
VClause: 568844 -> 432401 (-23.99%)
Copies: 1197942 -> 1231202 (+2.78%); split: -0.08%, +2.86%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23505>

aco/gfx11: use s_clause with stores

fossil-db (gfx1100):
Totals from 3535 (2.65% of 133428) affected shaders:
Instrs: 1963996 -> 1968979 (+0.25%)
CodeSize: 10077784 -> 10097716 (+0.20%)
Latency: 13264216 -> 13264741 (+0.00%)
InvThroughput: 2995676 -> 3004083 (+0.28%); split: -0.00%, +0.28%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23505>

aco: don't try to form load+store clauses

fossil-db (gfx1100):
Totals from 79 (0.06% of 133428) affected shaders:
MaxWaves: 1484 -> 1408 (-5.12%)
Instrs: 216290 -> 216255 (-0.02%); split: -0.04%, +0.03%
CodeSize: 1149288 -> 1149148 (-0.01%); split: -0.03%, +0.02%
VGPRs: 7384 -> 7840 (+6.18%)
Latency: 3303521 -> 3305077 (+0.05%); split: -0.05%, +0.10%
InvThroughput: 2716621 -> 2719973 (+0.12%); split: -0.01%, +0.13%
VClause: 5605 -> 6170 (+10.08%)
SClause: 3005 -> 2983 (-0.73%); split: -0.77%, +0.03%
Copies: 33428 -> 33490 (+0.19%); split: -0.07%, +0.26%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23505>

zink: fix anv ci flake wildcarding

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23751>

zink: ZINK_HEAP_HOST_VISIBLE_CACHED -> ZINK_HEAP_HOST_VISIBLE_COHERENT_CACHED

all host-visible memory in zink is expected to be coherent, and this makes
that expectation more explicit

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23728>

zink: add COHERENT requirement for CACHED memory

zink doesn't handle non-coherent cached memory correctly, so ensure
that scenario is never hit

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23728>

compiler: Move spirv into a module of its own

For historical reasons, nir and vtn were compiled together,
and a bunch of vtn specific targets were defined in
src/compiler/meson.build.

Now that we can, make src/compiler/spirv produce an internal
library that depends on NIR, and is used by the drivers/tools.
Also move the vtn specific targets into that directory's
meson.build.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23668>

isl: Add and use size and alignment calculators

Instead of interleaving the code for the size and alignment
calculations, split them out into their own functions.

This should make the code easier to follow and avoid some uninitialized
variable warnings.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23699>

aco/gfx10+: use v_cndmask with literal for reduction identity

Totals from 10 (0.01% of 132657) affected shaders:
CodeSize: 171576 -> 171288 (-0.17%)
Instrs: 32127 -> 32055 (-0.22%)
Latency: 219145 -> 219027 (-0.05%)
InvThroughput: 130287 -> 130041 (-0.19%)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23695>

aco: combine scalar mul+pk_add to pk_fma

Foz-DB Navi21:
Totals from 12 (0.01% of 134913) affected shaders:
CodeSize: 37860 -> 37668 (-0.51%)
Instrs: 6757 -> 6733 (-0.36%)
Latency: 25632 -> 25589 (-0.17%)
InvThroughput: 2637 -> 2622 (-0.57%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21819>

aco: use uses helpers for pk_fma opt

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21819>

radv: use wave32 for small workgroups

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23555>

radv: refactor CS subgroup size determination

This is less convoluted.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23555>

radeonsi/vcn: update luma and chroma size

This patch will adjust aligned_height to enc_alignment  which
is helping to address some corner cases like 4096x64/64x<>.

Actually less dpb size causing PROTECTION_FAULT. This change is
fixing the issue.

Signed-off-by: SureshGuttula <suresh.guttula@amd.com>
Reviewed-by: Boyuan Zhang Boyuan.Zhang@amd.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23448>

radv: advertise VK_EXT_depth_bias_control

Pass new CTS on RDNA2.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23696>

radv: implement VK_EXT_depth_bias_control

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23696>

vulkan/runtime: call CmdSetDepthBias2EXT() from CmdSetDepthBias()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23696>

r600/sfn: Implement source mod optimization in backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23702>

r600/sfn: add source and dest mod info to opcode table

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23702>

r600/sfn: allow source mods for per source with multi-slot ops

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23702>

r600/sfn: drop use of nir source mods

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23702>

r600/sfn: Fix typo

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23702>

virgl: don't allow vertex input arrays on GLES hosts

v2: - use new HOST_IS_GLES flag (Corentin)
    - drop stray fprintf (Emma)
    - reorder cases to avoid code replication

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15550>

zink, drirc: Add Borderlands 2 workaround to fix spir-v 1.6 translated discard

The game expects HLSL discard behavour

But it fails only on Zink because GLSL discard translates to
nir_intrinsic_discard (BRW_PREDICATE_ALIGN1_ANY4H in native Intel asm)
but Zink replaces it with OpTerminateInvocation SPIR-V and it translates to
nir_intrinsic_terminate (BRW_PREDICATE_NORMAL in native Intel asm)

Bisected commit in ZINK: bd816084

On AMD it works because they enabled the
glsl_correct_derivatives_after_discard by default: !10522 (17861aff)

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9205
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23694>