Topi Pohjolainen [Tue, 19 Apr 2016 06:45:09 +0000 (09:45 +0300)]
i965/blorp: Do not resolve lossless compressed blit sources
Blorp blits use sampling engine which is capable of resolving
on the fly. Buffers are still resolved for blitter engine. Current
understanding is that blitter doesn't understand lossless compression.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Topi Pohjolainen [Mon, 18 Apr 2016 05:51:10 +0000 (08:51 +0300)]
i965/blorp: Prepare blits for lossless compression
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Topi Pohjolainen [Tue, 19 Apr 2016 06:01:10 +0000 (09:01 +0300)]
i965: Deferred allocation of mcs for lossless compressed
Until now mcs was associated to single sampled buffers only for
fast clear purposes and it was therefore the responsibility of the
clear logic to allocate the aux buffer when needed. Now that normal
3D render or blorp blit may render with mcs enabled also, they need
to prepare the mcs just as well.
v2: Do not enable for scanout buffers
v3 (Ben):
- Fix typo in commit message.
- Check for gen < 9 and return early in brw_predraw_set_aux_buffers()
- Check for gen < 9 and return early in intel_miptree_prepare_mcs()
v4: Check for msaa_layput and number of samples to determine if
lossless compression is to used. Otherwise one cannot distuingish
between fast clear with and without compression.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Topi Pohjolainen [Sun, 24 Apr 2016 07:45:48 +0000 (10:45 +0300)]
i965: Add flag telling if miptree is for client consumption
Consider later on adding specific disable flags such as
MIPTREE_LAYOUT_DISABLE_AUX_MCS = 1 << 3, /* CCS_D */
MIPTREE_LAYOUT_DISABLE_AUX_CCS_E = 1 << 4,
MIPTREE_LAYOUT_DISABLE_AUX = MIPTREE_LAYOUT_DISABLE_AUX_MCS |
MIPTREE_LAYOUT_DISABLE_AUX_CCS_E,
and equivalent boolean/enums into miptree.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Topi Pohjolainen [Mon, 8 Feb 2016 16:13:17 +0000 (18:13 +0200)]
i965: Add helper for lossless compression support
v2: Check explicitly against base type of GL_FLOAT instead of
using _mesa_is_format_integer_color(). Otherwise we miss
GL_UNSIGNED_NORMALIZED.
v3 (Ben): Also call intel_miptree_supports_non_msrt_fast_clear()
in order to really check everything.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Topi Pohjolainen [Wed, 9 Dec 2015 12:44:21 +0000 (14:44 +0200)]
i965/gen9: Prepare surface state setup for lossless compression
v2 (Ben): Use combination of msaa_layout and number of samples
instead of introducing explicit type for lossless
compression (intel_miptree_is_lossless_compressed()).
v3 (Ben): Do not set fast claer state in surface state setup.
Moved into brw_postdraw_set_buffers_need_resolve()
using a separate patch.
v4: Support for blorp
v5 (Ben): Re-use gen8_get_aux_mode()
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Topi Pohjolainen [Fri, 6 May 2016 07:35:17 +0000 (10:35 +0300)]
i965/gen8: Expose auxiliary mode resolver
Also use the opportunity to drop the unused surface type argument.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Topi Pohjolainen [Mon, 18 Apr 2016 15:43:40 +0000 (18:43 +0300)]
i965: Relax assertion of halign == 16 for lossless compressed aux
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Topi Pohjolainen [Sun, 17 Apr 2016 15:33:55 +0000 (18:33 +0300)]
i965/blorp: Set full resolve for lossless compressed
v2 (Ben): Introduce union for fast clear and resolve ops
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Topi Pohjolainen [Thu, 12 May 2016 04:47:59 +0000 (07:47 +0300)]
i965/blorp: Do not skip fast color clear with new color
This hasn't been visible before. It showed up with lossless
compression with:
dEQP-GLES3.functional.fbo.color.repeated_clear.sample.tex2d.rgb8
Current fast clear logic kicks color resolves even for gpu sampling.
In the test case this results into trashing of the fast color clear
state between two subsequent clears, and therefore each clear is
performed correctly.
With lossless compression the resolves are unnecessary and therefore
the clear state indicates that the buffer is already cleared. Without
considering if the previous color value was the same as the new,
clears that need to be performed are skipped and the buffer ends up
holding old pixel values.
v2 (Ken): Fix the comparison for gen < 9
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Kenneth Graunke [Tue, 10 May 2016 00:09:35 +0000 (17:09 -0700)]
i965: Enable scalar GS by default.
I'd originally left this off because Orbital Explorer was hanging the
GPU, but it seems to be working these days. There have been a bunch
of changes since then, so we probably fixed something.
On my Broadwell laptop, both Synmark/GSCloth and Orbital Explorer seem
to run at approximately the same framerate in either mode. This is
despite large reductions in instruction count for Synmark, and large
increases for Orbital Explorer. It apparently just doesn't matter.
Switching to scalar mode will gain us fp64 support in the next release,
as vec4-mode support isn't yet ready.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Tue, 10 May 2016 01:11:00 +0000 (18:11 -0700)]
i965: Reduce the SIMD8 GS push constant threshold from 32 to 24.
Three Shadow of Mordor geometry shaders increase by a single
instruction, but the number of spills/fills in Orbital Explorer
is reduced from 194:1279 -> 82:454. No other programs are affected.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Mon, 9 May 2016 04:23:18 +0000 (21:23 -0700)]
i965: Delete bogus assertion in emit_gs_input_load().
This looks like leftover cruft from an earlier attempt at writing
point size hacks. Each vertex has its own copy of gl_PointSize,
so accessing any vertex other than 0 would cause this to fail.
The tests seem to work fine without it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Sun, 8 May 2016 09:54:28 +0000 (02:54 -0700)]
i965: Support instanced GS inputs in the scalar backend.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Sun, 8 May 2016 12:22:13 +0000 (05:22 -0700)]
i965: Use an early return for the push case in emit_gs_input_load().
Just trying to keep things from getting too ugly in the next commit.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Wed, 11 May 2016 07:07:26 +0000 (00:07 -0700)]
i965: Drop BRW_NEW_BLORP from stipple and line parameter packets.
BLORP never touches these, and they're all non-pipelined. Some
are fairly large packets as well.
I haven't tried to benchmark this; the effect is likely to be small.
However, we may as well stop the pointless papercuts; maybe they'll
add up someday.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jakob Sinclair [Wed, 11 May 2016 12:10:19 +0000 (14:10 +0200)]
glsl: fixed uninitialized pointer
Class "ir_constant" had a bunch of constructors where the pointer member
"array_elements" had not been initialized. This could have lead to unsafe
code if something had tried to write anything to it. This patch fixes
this issue by initializing the pointer to NULL in all the constructors.
This issue was discovered by Coverity.
CID: 401603, 401604, 401605, 401610
Signed-off-by: Jakob Sinclair <sinclair.jakob@openmailbox.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Ilia Mirkin [Sat, 9 Apr 2016 16:00:54 +0000 (12:00 -0400)]
nvc0: fix gl_SampleMaskIn computation
The SAMPLEMASK semantic should only return the bits set covered by the
current invocation. However we were always retrieving the covmask, which
returns the covered samples of the whole pixel.
When not doing per-sample invocation, this is precisely what we want.
However when doing per-sample invocation, we have to select the
sampleid'th bit and only return that. Furthermore, this means that we
have to have a 1:1 correlation for invocations and samples.
This fixes most
dEQP-GLES31.functional.shaders.sample_variables.sample_mask_in.*
tests. A few failures remain due to disagreements about nr_samples==1
logic as well as what happens with MSAA x2 RTs when the shading fraction
is 0.5.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 7 May 2016 20:14:01 +0000 (16:14 -0400)]
nv50/ir: generalize interp fixups to be able to fixup anything
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Jason Ekstrand [Wed, 11 May 2016 19:32:14 +0000 (12:32 -0700)]
.mailmap: Update the e-mail addresses for Kristian Høgsberg
This changes it to use his personal e-mail and adds his @intel.com address
Acked-by: Kristian Høgsberg <krh@bitplanet.net>
Jason Ekstrand [Wed, 11 May 2016 19:27:15 +0000 (12:27 -0700)]
.mailmap: Use Connor Abbott's personal e-mail
Giuseppe Bilotta [Mon, 28 Dec 2015 09:50:42 +0000 (10:50 +0100)]
Add .mailmap
This adds a first tentative .mailmap file, to canonicize contributor
name/emails in shortlogs and other statistical endeavours.
Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Thu, 5 May 2016 23:38:25 +0000 (16:38 -0700)]
i965: Stop splitting fma() prior to optimization
According to the GLSL spec, if the user uses the fma() intrinsic to
generate a precise-consumed value, and you have it in your hardware, you
shouldn't split it. For a while now, we've been splitting all ffma's
up-front and then planned to fuse them later which isn't valid. Correctly
handling the GLSL behaviour fixes rendering corruptions in Tomb Raider.
The only reason why doing this possibly helped before was for ARB programs
which is handled by the previous commit.
Shader-db results on Haswell:
total instructions in shared programs: 7560300 -> 7561510 (0.02%)
instructions in affected programs: 56265 -> 57475 (2.15%)
helped: 86
HURT: 291
The only shaders in the database that are affected are from "Shadow of
Mordor" which is the first app in our database to use fma(). We could, at
some point in the future, split inexact ffma opcodes which would fix the
shader-db regressions since Shadow of Mordor doesn't ues precise. However,
this fixes a bug now and and the shader-db impact is fairly small.
Reported-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Fri, 6 May 2016 00:14:39 +0000 (17:14 -0700)]
ptn: Emit mul+add for MAD
Unlike fma() in GLSL, MAD in ARB programs is 100% splittable. Just emit
the split version and let the optimizer fuse them later.
Shader-db results on Haswell:
total instructions in shared programs: 7560379 -> 7560300 (-0.00%)
instructions in affected programs: 143928 -> 143849 (-0.05%)
helped: 443
HURT: 250
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Thu, 5 May 2016 23:58:44 +0000 (16:58 -0700)]
nir/algebraic: Separate ffma lowering from fusing
The i965 driver has its own pass for fusing mul+add combinations that's
much smarter than what nir_opt_algebraic can do so we don't want to get the
nir_opt_algebraic one just because we didn't set lower_ffma.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rob Clark [Wed, 11 May 2016 18:03:24 +0000 (14:03 -0400)]
anv: fix build break
Previous rename of lower-output-to-temps pass predated merging of anv,
and apparently vulkan wasn't enabled in my local builds so overlooked
this when rebasing.
Reported-by: Mark Janes <mark.a.janes@intel.com>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 24 Mar 2016 18:14:36 +0000 (14:14 -0400)]
mesa/st: split the type_size calculation into it's own file
We'll want to re-use this for NIR.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rob Clark [Fri, 29 Jan 2016 16:18:11 +0000 (11:18 -0500)]
glsl: export accessor for builtin-uniform descriptors
We'll need this for a nir pass to lower builtin-uniform access.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Fri, 25 Mar 2016 19:10:50 +0000 (15:10 -0400)]
nir/lower-io: add support for lowering inputs
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Fri, 25 Mar 2016 19:03:40 +0000 (15:03 -0400)]
nir/lower-io: split out some helper fxns
Prep work to reduce the noise in the next patch.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Fri, 25 Mar 2016 17:52:26 +0000 (13:52 -0400)]
nir: rename lower_outputs_to_temporaries -> lower_io_to_temporaries
Since it will gain support to lower inputs, give it a more generic name.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 25 Mar 2016 17:47:15 +0000 (13:47 -0400)]
nir: move callsite of lower_outputs_to_temporaries
Going to convert this pass to parameterized lower_io_to_temporaries, and
we want the user to be able to specify whether to lower outputs or
inputs or both. The restriction of running this pass before validate
to avoid output reads no longer applies.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Fri, 25 Mar 2016 19:15:44 +0000 (15:15 -0400)]
nir: lower-io-types pass
A pass to lower complex (struct/array/mat) inputs/outputs to primitive
types. This allows, for example, linking that removes unused components
of a larger type which is not indirectly accessed.
In the near term, it is needed for gallium (mesa/st) support for NIR,
since only used components of a type are assigned VBO slots, and we
otherwise have no way to represent that to the driver backend. But it
should be useful for doing shader linking in NIR.
v2: use glsl_count_attribute_slots() rather than passing a type_size
fxn pointer
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Mon, 1 Feb 2016 22:34:12 +0000 (17:34 -0500)]
nir: passthrough-edgeflags support
Handled by tgsi_emulate for glsl->tgsi case.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Tue, 22 Dec 2015 02:54:00 +0000 (21:54 -0500)]
nir: add lowering pass for glBitmap
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Tue, 22 Dec 2015 02:27:25 +0000 (21:27 -0500)]
nir: add lowering pass for glDrawPixels
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Sat, 7 Nov 2015 15:59:09 +0000 (10:59 -0500)]
nir: add lowering pass for y-transform
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Sat, 30 Jan 2016 18:11:47 +0000 (13:11 -0500)]
gallium: add NIR as a possible IR
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rob Clark [Sat, 17 Oct 2015 17:34:24 +0000 (13:34 -0400)]
gallium: refactor pipe_shader_state to support multiple IR's
The goal is to allow the pipe driver to request something other than
TGSI, but detect whether what is getting is TGSI vs what it requested.
The pipe drivers will always have to support TGSI (and convert that into
whatever it is that they prefer), but in some cases we should be able to
skip the TGSI intermediate step (such as glsl->nir vs glsl->tgsi->nir).
I think pipe_compute_state should get similar treatment. Currently,
afaict, it has one user and one consumer, which has allowed it to be
sloppy wrt. supporting alternative IR's.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rob Clark [Wed, 11 May 2016 15:28:13 +0000 (11:28 -0400)]
freedreno: fix multi-layer transfer_map's
The use of transfer_inline_write() in TexSubImage path (see
fb9fe352ea4)
exposed a bug for "layer_first" resources (ie. a4xx) not setting correct
layer_stride.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Juan A. Suarez Romero [Wed, 11 May 2016 11:48:18 +0000 (13:48 +0200)]
glsl: use var with initializer on global var validation
Currently, when cross validating global variables, all global variables
seen in the shaders that are part of a program are saved in a table.
When checking a variable this already exist in the table, we check both
are initialized to the same value. If the already saved variable does
not have an initializer, we copy it from the new variable.
Unfortunately this is wrong, as we are modifying something it is
constant. Also, if this modified variable is used in
another program, it will keep the initializer, when it should have none.
Instead of copying the initializer, this commit replaces the old
variable with the new one. So if we see again the same variable with an
initializer, we can compare if both are the same or not.
v2: convert tabs in whitespaces (Kenenth Graunke)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Tue, 10 May 2016 21:22:13 +0000 (14:22 -0700)]
util/ralloc: Remove double zero'ing of rzalloc buffers
Juha-Pekka found this back in May 2015:
<
1430915727-28677-1-git-send-email-juhapekka.heikkila@gmail.com>
From the discussion, obviously it would be preferable to make
ralloc_size no longer return zeroed memory, but Juha-Pekka found that
it would break Mesa.
In <
56AF1C57.2030904@gmail.com>, Juha-Pekka mentioned that patches
exist to fix i965 when ralloc_size is fixed to not zero memory, but
the patches have not made their way to mesa-dev yet.
For now, let's stop doing the double zeroing of rzalloc buffers.
v2:
* Move ralloc_size code to rzalloc_size, and add a comment as
suggested by Ken.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jonathan Gray [Tue, 3 May 2016 00:25:09 +0000 (10:25 +1000)]
genxml: avoid using a GNU make pattern rule
% pattern rules are a GNU extension. Convert the use of one to a
inference rule to allow this to build on OpenBSD.
v2: inference rules can't have additional prerequisites so add a target
rule to still depend on gen_pack_header.py
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Roland Scheidegger [Wed, 11 May 2016 02:42:51 +0000 (04:42 +0200)]
gallivm: improve dumping of bitcode
Use GALLIVM_DEBUG=dumpbc for dumping of modules as bitcode.
Instead of a fixed llvmpipe.bc name, use ir_<modulename>.bc so multiple
modules can be dumped (albeit it might still overwrite previous modules,
particularly the modules from draw tend to always have the same name).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Vinson Lee [Mon, 9 May 2016 23:02:12 +0000 (16:02 -0700)]
swr: [rasterizer] Include cmath for std::isnan and std::isinf.
This patch fixes this build error.
CXX rasterizer/memory/libswrAVX_la-ClearTile.lo
In file included from rasterizer/memory/ClearTile.cpp:34:0:
./rasterizer/memory/Convert.h: In function ‘uint16_t Convert32To16Float(float)’:
./rasterizer/memory/Convert.h:170:9: error: ‘__builtin_isnan’ is not a member of ‘std’
if (std::isnan(val))
^
./rasterizer/memory/Convert.h:170:9: note: suggested alternative:
<built-in>: note: ‘__builtin_isnan’
./rasterizer/memory/Convert.h:176:14: error: ‘__builtin_isinf_sign’ is not a member of ‘std’
else if (std::isinf(val))
^
./rasterizer/memory/Convert.h:176:14: note: suggested alternative:
<built-in>: note: ‘__builtin_isinf_sign’
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95180
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Jason Ekstrand [Wed, 4 May 2016 22:53:04 +0000 (15:53 -0700)]
i965/blorp: Don't blend integer values during MSAA resolves
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Wed, 4 May 2016 22:52:50 +0000 (15:52 -0700)]
meta/blit: Don't blend integer values during MSAA resolves
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Tue, 10 May 2016 20:54:58 +0000 (13:54 -0700)]
i965/fs: Default all constants to a location of -1
Otherwise constants which aren't live get an undefined constant location.
When we go to set up param and pull_param we end up assigning all unused
uniforms to slot 0. This cases the Vulkan driver to segfault because it
doesn't have pull_param.
This fixes bugs in the Vulkan driver introduced in
c3fab3d000.
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Dave Airlie [Tue, 10 May 2016 05:53:48 +0000 (15:53 +1000)]
st/glsl_to_tgsi: attach image to correct instruction for samples
This fixes a crash (but not the test):
GL45-CTS.shader_texture_image_samples_tests.functional_test
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 10 May 2016 04:56:02 +0000 (14:56 +1000)]
mesa: move MESA_MAP_NOWAIT_BIT up away from GL_MAP_PERSISTENT_BIT
This was colliding badly and making
GL45-CTS.buffer_storage.map_persistent_texture
fail on radeonsi.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 10 May 2016 05:41:46 +0000 (15:41 +1000)]
mesa/meta: check for signed/unsigned int conversion for pbo getteximage
When doing GetTexSubImage using a PBO, we should check if it involves
a signed/unsigned conversion and bail if it does, just like in the
other cases.
This fixes:
GL33-CTS.gtf32.GL3Tests.packed_pixels.packed_pixels_pbo
on Haswell at least.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95324
Reviewed-by: Matt Turer <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
Matt Turner [Mon, 9 May 2016 22:58:20 +0000 (15:58 -0700)]
i965: Handle BRW_OPCODE_DO on Gen6+ in brw_instruction_name().
This became a problem after the recent disassembler changes.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bas Nieuwenhuizen [Fri, 6 May 2016 19:06:14 +0000 (21:06 +0200)]
radeonsi: Set declared tessellation LDS size to hardware size.
The calculated limit gave problems on SI as it was > 32 KiB
and the hardware LDS size on SI is only 32 KiB. It isn't
correct anyway when processing multiple patches in a threadgroup.
As we potentially have any number of patches such that the
used LDS is at most the hardware LDS size, and exact size
per patch is not known at compile time, this seems like
the only valid bound.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rob Clark [Tue, 10 May 2016 15:46:11 +0000 (11:46 -0400)]
freedreno/ir3: size input/output arrays properly
We index into these based on var->data.driver_location, which might have
gaps (ie. two inputs, one w/ drvloc 0 and other 2). This shows up in
(for example) 'bin/copyteximage 1D', but was only noticed recently due
to additional asserts.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Ian Romanick [Wed, 13 Apr 2016 18:43:23 +0000 (11:43 -0700)]
ir_to_mesa: Emit smarter ir_binop_logic_or for vertex programs
Continue using ADD in the other case because a fragment shader backend
could fuse the ADD with a MUL to generate a MAD for ((x && y) || z).
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Wed, 13 Apr 2016 00:38:23 +0000 (17:38 -0700)]
prog: Delete all remains of OPCODE_SNE, OPCODE_SEQ, OPCODE_SGT, and OPCODE_SLE
There is nothing left that can generate them. These used to be
generated by ir_to_mesa or by the assembler for various NV extensions
that have been removed.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Wed, 13 Apr 2016 01:49:40 +0000 (18:49 -0700)]
ir_to_mesa: Do not emit OPCODE_SEQ or OPCODE_SNE
Nothing that consumes the output of this backend consumes them
navtively. This is *not* the way i915 has implemented these
instructions, but, as far as I am able to tell, this is the way both the
Cg compiler and the HLSL compiler implement these operations.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Wed, 13 Apr 2016 00:30:25 +0000 (17:30 -0700)]
ir_to_mesa: Do not emit OPCODE_SLE or OPCODE_SGT
Nothing that consumes the output of this backend consumes them
navtively. This is the way i915 has implemented these instructions
since it began consuming GLSL.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Samuel Pitoiset [Mon, 9 May 2016 22:22:35 +0000 (00:22 +0200)]
nvc0: enable compute support by default on GK110+
Compute support seems to be pretty stable now, and according to piglit
it doesn't seem to break 3D state.
As a side effect, this will expose ARB_compute_shader on GK110/GK208.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Marek Olšák [Thu, 28 Apr 2016 16:06:55 +0000 (18:06 +0200)]
gallium/radeon: don't flush the GFX IB if DMA doesn't depend on it
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 28 Apr 2016 15:51:43 +0000 (17:51 +0200)]
radeonsi: consolidate radeon_add_to_buffer_list calls for DMA
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 29 Apr 2016 23:21:22 +0000 (01:21 +0200)]
gallium/radeon: add a heuristic for better (S)DMA performance
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 28 Apr 2016 14:32:39 +0000 (16:32 +0200)]
gallium/radeon: flush if DMA IB memory usage is too high
This prevents IB rejections due to insane memory usage from
many concecutive texture uploads.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 21 Apr 2016 19:41:59 +0000 (21:41 +0200)]
radeonsi: add new SDMA texture copy code
This implements:
- Linear-to-linear partial copies. (unaligned)
- Tiled-to-linear and linear-to-tiled partial copies.
(unaligned except 1-2 Bpp)
- Tiled-to-tiled partial copies aligned to 8x8.
v2: Extend the SDMA L2T VM fault workaround to T2L.
- Same algorithm, just applied to T2L.
(and using a 0-based address and surface.bo_size instead of buf->size)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Apr 2016 17:29:55 +0000 (19:29 +0200)]
gallium/radeon: fix (S)DMA read-after-write hazards
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Apr 2016 17:10:43 +0000 (19:10 +0200)]
radeonsi: raise the max size for SDMA buffer copies
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Apr 2016 17:06:21 +0000 (19:06 +0200)]
radeonsi: remove SDMA texture copy code
Most of this has never worked according to the new test.
The new code will be radically different.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 22 Apr 2016 20:03:24 +0000 (22:03 +0200)]
radeonsi: only expose *_init_*dma_functions from (S)DMA files
just normalizing the interfaces
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 5 Sep 2014 18:15:16 +0000 (20:15 +0200)]
gallium/radeon: implement randomized SDMA texture copy testing (v2)
v2: - adjustments for exercising all important SDMA code paths
- decrease the probability of getting huge sizes (faster testing)
- increase the probability of getting power-of-two dimensions
- change the memory cap to 128MB (faster testing)
- better detect which engine has been used
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 28 Apr 2016 17:22:28 +0000 (19:22 +0200)]
gallium/radeon: discard CMASK or DCC if overwriting a whole texture by DMA
v2: simplify the conditionals
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 21 Apr 2016 21:46:19 +0000 (23:46 +0200)]
gallium/radeon: use a common function for DMA blit preparation
this is more robust and probably fixes some bugs already
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 28 Apr 2016 17:45:22 +0000 (19:45 +0200)]
gallium/radeon: split out code for discarding DCC
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 28 Apr 2016 17:44:42 +0000 (19:44 +0200)]
gallium/radeon: rename r600_texture_disable_cmask -> discard_cmask
because it doesn't decompress
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 5 May 2016 19:02:24 +0000 (21:02 +0200)]
st/mesa: use transfer_inline_write for memcpy TexSubImage path
This allows drivers to use their own fast path for texture uploads.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 8 May 2016 22:39:32 +0000 (00:39 +0200)]
gallium/radeon: fix partial layered transfers of cube (array) textures
a staging cube texture with array_size % 6 != 0 doesn't work very well
just use 2D_ARRAY or 2D for all staging textures
Cc: 11.1 11.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 8 May 2016 11:40:40 +0000 (13:40 +0200)]
gallium/radeon: align alignments for better buffer reuse
It's for the buffer cache.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 8 May 2016 10:30:25 +0000 (12:30 +0200)]
gallium/radeon: use gart_page_size instead of hardcoded 4096
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 8 May 2016 11:35:19 +0000 (13:35 +0200)]
winsys/radeon: use gart_page_size instead of private size_align
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 8 May 2016 10:27:14 +0000 (12:27 +0200)]
winsys/amdgpu: move gart_page_size to struct radeon_winsys
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Roland Scheidegger [Tue, 10 May 2016 01:48:13 +0000 (03:48 +0200)]
gallivm: print declarations of intrinsics with GALLIVM_DEBUG=ir
Those aren't really interesting, however outputting them is helpful when
trying to feed the IR to llvm llc (or opt) for debugging.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Sun, 8 May 2016 00:27:45 +0000 (02:27 +0200)]
gallivm: use InternalLinkage instead of PrivateLinkage for texture functions
At least with MCJIT the disassembler will crash otherwise when trying to
disassemble such functions.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Sat, 7 May 2016 22:40:07 +0000 (00:40 +0200)]
gallivm: disable avx512 features
We don't target this yet, and some llvm versions incorrectly enable it based
on cpu string, causing crashes.
(Albeit this is a losing battle, it is pretty much guaranteed when the next
new feature comes along llvm will mistakenly enable it on some future cpu,
thus we would have to proactively disable all new features as llvm adds them.)
This should fix https://bugs.freedesktop.org/show_bug.cgi?id=94291 (untested)
Tested-by: Timo Aaltonen <tjaalton@ubuntu.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com
CC: <mesa-stable@lists.freedesktop.org>
Jose Fonseca [Mon, 9 May 2016 21:35:58 +0000 (14:35 -0700)]
Revert "nir: Try to warn when C99 extensions are used in nir headers."
This reverts commit
99474dc29b0f45413d0e538d7321da9ad4c9f6f5.
-Wpedantic is too verbose, even when applied to just a few includes.
We'll just have to deal with the issues as they come.
Reviewed-by: Brian Paul <brianp@vmware.com>
Samuel Iglesias Gonsálvez [Wed, 20 Apr 2016 07:59:11 +0000 (09:59 +0200)]
i965/fs: fix MOV_INDIRECT exec_size for doubles
In that case, the writes need two times the size of a 32-bit value.
We need to adjust the exec_size, so it is not breaking any hardware
rule.
v2:
- Add an assert to verify type size is not less than 4 bytes (Jordan).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Samuel Iglesias Gonsálvez [Tue, 19 Apr 2016 07:49:40 +0000 (09:49 +0200)]
i965/fs: take into account doubles when calculating read_size for MOV_INDIRECT
v2:
- Fix assert's line width (Topi).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Samuel Iglesias Gonsálvez [Fri, 27 Nov 2015 11:52:22 +0000 (12:52 +0100)]
i965/fs: demote_pull_constants() did not take into account double types
The constants could be double, and it was allocating size for float types
for the destination register of varying pull constant loads.
Then the fs_visitor::validate() will complain.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Samuel Iglesias Gonsálvez [Thu, 5 May 2016 07:18:07 +0000 (09:18 +0200)]
i965/fs: push first double-based uniforms in push constant buffer
When there is a mix of definitions of uniforms with 32-bit or 64-bit
data type sizes, the driver ends up doing misaligned access to double
based variables in the push constant buffer.
To fix this, this patch pushes first all the 64-bit variables and
then the rest. Then, all the variables would be aligned to
its data type size.
v2:
- Fix typo and improve comment (Jordan).
- Use ralloc(NULL,...) instead of rzalloc(mem_ctx,...) (Jordan).
- Fix typo (Topi).
- Use pointers instead of references in set_push_pull_constant_loc() (Topi).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Iago Toral Quiroga [Thu, 31 Mar 2016 10:05:31 +0000 (12:05 +0200)]
i965/fs: recognize writes with a subreg_offset > 0 as partial
Usually, writes to a subreg_offset > 0 would also have a stride > 1
and we would recognize them as partial, however, there is one case
where this does not happen, that is when we generate code for 64-bit
imemdiates in gen7, where we produce something like this:
mov(8) vgrf10:UD, <low 32-bit>
mov(8) vgrf10+0.4:UD, <high 32-bit>
and then we use the result with a stride of 0, as in:
mov(8) vgrf13:DF, vgrf10<0>:DF
Although we could try to avoid this issue by producing different code
for this by using writes with a stride of 2, that runs into other
problems affecting gen7 and the fact is that any instruction that
writes to a subreg_offset > 0 is a partial write so we should really
recognize them as such.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Fri, 15 Jan 2016 13:59:13 +0000 (14:59 +0100)]
i965/fs/lower_simd_width: Fix registers written for split instructions
When the original instruction had a stride > 1, the combined registers
written by the split instructions won't amount to the same register space
written by the original instruction because the split instructions will
use a stride of 1. The current code assumed otherwise and computed the
number of registers written by split instructions as an equal share based
on the relation between the lowered width and the original execution size
of the instruction.
It is only after the split, when we interleave the components of the result
from the lowered instructions back into the original dst register, that the
original stride takes effect and we write all the registers specified by
the original instruction.
Just make the number of register written the same as the vgrf space we
allocate for the dst of the split instruction.
Fixes crashes in fp64 tests produced as a result of assigning incorrectly the
number of registers written by split instructions, which led to incorrect
validation of the size of the writes against the allocated vgrf space.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Mon, 18 Jan 2016 10:31:36 +0000 (11:31 +0100)]
i965/fs: rename our lower_d2f pass to lower_d2x
Since it no longer handles conversions from double to float but from
double to various other 32-bit types.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Tue, 12 Jan 2016 13:08:57 +0000 (14:08 +0100)]
i965/fs: implement i2d and u2d
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Mon, 18 Jan 2016 10:23:49 +0000 (11:23 +0100)]
i965/fs: implement d2i and d2u
These need the same treatment as d2f, so generalize our d2f lowering to cover
these too.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Mon, 18 Jan 2016 10:23:33 +0000 (11:23 +0100)]
i965/fs: implement d2b
v2: Use subscript() instead of stride() (Curro)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Thu, 7 Jan 2016 13:15:37 +0000 (14:15 +0100)]
i965/fs: implement fsign() for doubles
v2 (Sam):
- Fix indentation (Kenneth)
- Simplify code (Kenneth)
v3: Use subscript() instead of stride() (Curro)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Thu, 7 Jan 2016 13:12:26 +0000 (14:12 +0100)]
i965/fs: add null_reg_df
Probably not needed since we fix the dst type of comparisons
automatically, but for consistency with the rest of null_reg_*
functions.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Tue, 10 Nov 2015 09:18:55 +0000 (10:18 +0100)]
i965/fs: We only support 32-bit integer ALU operations for now
Add asserts so we remember to address this when we enable 64-bit
integer support, as suggested by Connor and Jason.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Wed, 27 Jan 2016 11:48:38 +0000 (12:48 +0100)]
i965/fs: handle fp64 opcodes in brw_do_channel_expressions
In the case of the pack opcode we are already doing the
lowering in NIR, so no need to do it here. The unpack opcode
operates on scalars, so it should not be lowered.
In the case of frexp_sig and frexp_exp, they are lowered in
lower_instructions, so we don't have to care about them.
All the remaining opcodes involve conversions from and to doubles
and are business as usual.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Connor Abbott [Thu, 30 Jul 2015 07:20:40 +0000 (00:20 -0700)]
i965/fs: add support for f2d and d2f
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Connor Abbott [Sun, 1 Nov 2015 08:10:21 +0000 (03:10 -0500)]
i965/fs: add a pass for legalizing d2f
We need to do this late, in order to avoid partial writes during the
optimization loop.
v2: Use subscript() instead of stride().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Connor Abbott [Tue, 11 Aug 2015 21:24:55 +0000 (14:24 -0700)]
i965/fs: fix dst width calculation in CSE
v2 (Sam):
- Fix line width (Topi).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>