Don Breazeal [Mon, 14 Dec 2015 19:18:06 +0000 (11:18 -0800)]
Target remote mode fork and exec event documentation
This patch implements documentation updates for target remote mode fork and
exec events. A summary of the rationale for the changes made here:
* Connecting to a remote target -- explain that the two protocols exist.
* Connecting in target remote mode -- explain invoking gdbserver for target
remote mode, and move remote-specific text from original "Connecting to a
remote target" section.
* Connecting in target extended-remote mode -- promote this section from
"Using the gdbserver Program | Running gdbserver | Multi-Process Mode for
gdbserver". Put it next to the target remote mode section.
* Host and target files -- collect paragraphs dealing with how to locate
symbol files from original sections "Connecting to a remote target" and
"Using the gdbserver program | Connecting to gdbserver".
* Steps for connecting to a remote target -- used to be "Using the
gdbserver program | Connecting to gdbserver"
* Remote connection commands -- used to be the bulk of "Connecting to a
remote target". Added "target extended-remote" commands and information.
gdb/ChangeLog:
* NEWS: Announce fork and exec event support for target remote.
gdb/doc/ChangeLog:
* gdb.texinfo (Forks): Correct Linux kernel version where
fork and exec events are supported, add notes about support
of these events in target remote mode.
(Connecting): Reorganize and clarify distinctions between
target remote, extended-remote, and multiprocess.
Reorganize related text from separate sections into new
sections.
(Server): Note effects of target extended-remote mode.
Delete section on Multi-Process Mode for gdbserver.
Move some text to "Connecting" node.
Don Breazeal [Mon, 14 Dec 2015 19:18:05 +0000 (11:18 -0800)]
Target remote mode fork and exec event support
This patch implements support for fork and exec events with target remote
mode Linux targets. For such targets with Linux kernels 2.5.46 and later,
this enables follow-fork-mode, detach-on-fork and fork and exec
catchpoints.
The changes required to implement this included:
* Don't exit from gdbserver if there are still active inferiors.
* Allow changing the active process in remote mode.
* Enable fork and exec events in remote mode.
* Print "Ending remote debugging" only when disconnecting.
* Combine remote_kill and extended_remote_kill into a single function
that can handle the multiple inferior case for target remote. Also,
the same thing for remote_mourn and extended_remote_mourn.
* Enable process-style ptids in target remote.
* Remove restriction on multiprocess mode in target remote.
gdb/gdbserver/ChangeLog:
* server.c (process_serial_event): Don't exit from gdbserver
in remote mode if there are still active inferiors.
gdb/ChangeLog:
* inferior.c (number_of_live_inferiors): New function.
(have_live_inferiors): Use number_of_live_inferiors in place
of duplicate code.
* inferior.h (number_of_live_inferiors): Declare new function.
* remote.c (set_general_process): Remove restriction on target
remote mode.
(remote_query_supported): Likewise.
(remote_detach_1): Exit in target remote mode only when there
is just one live inferior left.
(remote_disconnect): Unpush the target directly instead of
calling remote_mourn.
(remote_kill): Rewrite function to handle both target remote
and extended-remote. Call remote_kill_k.
(remote_kill_k): New function.
(extended_remote_kill): Delete function.
(remote_mourn, extended_remote_mourn): Combine functions into
one, remote_mourn, and enable extended functionality for target
remote.
(remote_pid_to_str): Enable "process" style ptid string for
target remote.
(remote_supports_multi_process): Remove restriction on target
remote mode.
Don Breazeal [Mon, 14 Dec 2015 19:18:05 +0000 (11:18 -0800)]
Target remote mode fork and exec test updates
This patch updates tests for fork and exec events in target remote mode.
In the majority of cases this was a simple matter of removing some code
that disabled the test for target remote. In a few cases the test needed
to be disabled; in those cases the gdb_protocol was checked instead of
using the [is_remote target] etc.
In a couple of cases we needed to use clean_restart, since target remote
doesn't support the run command, and in one case we had to modify an expect
expression to allow for a "multiprocess-style" ptid.
Tested with the patch that implemented target remote mode fork and exec
event support.
gdb/testsuite/ChangeLog:
* gdb.base/execl-update-breakpoints.exp (main): Enable for target
remote.
* gdb.base/foll-exec-mode.exp (main): Disable for target remote.
* gdb.base/foll-exec.exp (main): Enable for target remote.
* gdb.base/foll-fork.exp (main): Likewise.
* gdb.base/foll-vfork.exp (main): Likewise.
* gdb.base/multi-forks.exp (main): Likewise, and use clean_restart.
(proc continue_to_exit_bp_loc): Use clean_restart.
* gdb.base/pie-execl.exp (main): Disable for target remote.
* gdb.base/watch-vfork.exp (main): Enable for target remote.
* gdb.mi/mi-nsthrexec.exp (main): Likewise.
* gdb.threads/execl.exp (main): Likewise.
* gdb.threads/fork-child-threads.exp (main): Likewise.
* gdb.threads/fork-plus-threads.exp (main): Disable for target
remote.
* gdb.threads/fork-thread-pending.exp (main): Enable for target
remote.
* gdb.threads/linux-dp.exp (check_philosopher_stack): Allow
pid.tid style ptids, instead of just tid.
* gdb.threads/thread-execl.exp (main): Enable for target remote.
* gdb.threads/watchpoint-fork.exp (main): Likewise.
* gdb.trace/report.exp (use_collected_data): Allow pid.tid style
ptids, instead of just tid.
Matthew Wahab [Mon, 14 Dec 2015 17:46:21 +0000 (17:46 +0000)]
[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Scalar Shift By Immediate to support
FP16, making this support available when +simd+fp16 is enabled.
The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.
The general form for these instructions is
<OP> <Hd>, <Hs>, #<imm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16: Add tests for Adv.SIMD scalar shift
by immediate instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SSHIFT_H): New.
(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
and fcvtzu to the Adv.SIMD scalar shift by immediate group.
Change-Id: I40506496f52dd96909e7344f243b38a1870df7ff
Matthew Wahab [Mon, 14 Dec 2015 17:40:03 +0000 (17:40 +0000)]
[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Shift By Immediate to support FP16,
making this support available when +simd+fp16 is enabled.
The new instructions legal make some uses of the 4h vector type that had
been invalid. This patch adjusts a test that checks for these uses.
The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, #<imm>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
instructions.
* gas/aarch64/illegal.d: Update expected output.
* gas/aarch64/illegal.s: Replace tests for illegal use of 'h'
specifier.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_VSHIFT_H): New.
(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
and fcvtzu to the Adv.SIMD shift by immediate group.
Change-Id: I3480f63883d54db46562573185da6982f2365ee8
Matthew Wahab [Mon, 14 Dec 2015 17:35:47 +0000 (17:35 +0000)]
[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Scalar Pairwise, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNMP, FADDP, FMAXP, FMINNMP and FMINP
The general form for these instructions is
<OP> <Hd>, <V>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD Scalar
Pairwise instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_PAIR_H): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.
Change-Id: I19937ede3441b66dd0f940269ece895b17d3c345
Matthew Wahab [Mon, 14 Dec 2015 17:27:52 +0000 (17:27 +0000)]
[AArch64][PATCH 11/14] Add support for the 2H vector type.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. The FP16 additions to the
scalar pairwise group introduce a new vector type, 2H. This patch adds
support for this vector type to binutils.
The patch adds a new operand qualifier to the enum
aarch64.h:aarch64_opnd_qualifier. This interferes with the calculation
used by aarch64-dis.c:get_vreg_qualifier_from_value, called when
decoding an instruction. Since the new vector type is only used in FP16
scalar pairwise instructions which do not require the function, this
patch adjusts the function to ignore the new qualifier.
gas/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (parse_neon_type_for_operand): Adjust to
take into account new vector type 2H.
(vectype_to_qualifier): Likewise.
include/opcode/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (enum aarch64_opnd_qualifier): Add
AARCH64_OPND_QLF_V_2H.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.coM>
* aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
and adjust calculation to ignore qualifier for type 2H.
* aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".
Change-Id: Idf9a3694732962c80fde04f08c7304de9164f126
Matthew Wahab [Mon, 14 Dec 2015 17:25:35 +0000 (17:25 +0000)]
[AArch64][PATCH 10/14] Rework code mapping vector types to operand qualifiers.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. The FP16 additions to the
scalar pairwise group introduce a new vector type. This patch reworks
code in the assembler to allow the addition of the new type.
The new vector type requires the addtion of a new operand qualifier to
the enum aarch64_opnd_qualifier which is defined
include/opcodes/aarch64.h, in the group prefixed by AARCH64_OPN_QLF_V_.
The correctness of the GAS utility function
tc-aarch64.c:vectype_to_qualifier is heavily dependent on the number and
ordering of this group. In particular, it makes assumptions about the
positions of the members of the group that are not true if a qualifier
for type 2H is added before the qualifier for 4H.
This patch reworks the function to weaken its assumptions, making it
calculate positions in the group from the type (B, H, S, D, Q) and
register width.
gas/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (vectype_to_qualifier): Calculate operand
qualifier from per-type base and offet.
Change-Id: I95535864e342a6dec46f69d2696b3900a008f0b1
Matthew Wahab [Mon, 14 Dec 2015 17:22:36 +0000 (17:22 +0000)]
[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds an FP16
instruction to the group Adv.SIMD Modified Immediate, making it
available when +simd+fp16 is enabled.
The instruction added is: FMOV.
The form of this instructions is
<OP> <Hd>, #<imm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD modified immediate
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SIMD_IMM_H): New.
(aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
modified immediate group.
Change-Id: Ic66af44c494e6a53fb1cf01c372cdc62d12643e2
Matthew Wahab [Mon, 14 Dec 2015 17:16:50 +0000 (17:16 +0000)]
[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Across Lanes, making them available
when +simd+fp16 is enabled.
The instructions added are: FMAXNMV, FMAXV, FMINNMV and FMINV.
The general form for these instructions is
<OP> <Hd>, <V>.<T>
where T is 4h or 8h.
The new instructions valid make uses of the 8H and 4H that were
previously illegal. The patch adjusts a test for illegal uses of vector
types to take this into account.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
instructions.
* gas/aarch64/illegal.d: Update expected output.
* gas/aarch64/illegal.s: Replace test for illegal use of 'h'
specifier.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_XLANES_FP_H): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
fminnmv, fminv to the Adv.SIMD across lanes group.
Change-Id: Ib9a47e867f55e0272c2446eb7e16837503d2f94c
Matthew Wahab [Mon, 14 Dec 2015 17:07:51 +0000 (17:07 +0000)]
[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Indexed Element, making them available
when +simd+fp16 is enabled.
The instructions added are: FMLA, FMLS, FMUL and FMULX.
The general form for these instructions is
<OP> <Hd>, <Hs>, <V>.h[<idx>]
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar indexed element
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
fmls, fmul and fmulx to the scalar indexed element group.
Change-Id: I6a4ee20a9ae1019b89d0fd05da55222f267c5627
Matthew Wahab [Mon, 14 Dec 2015 17:01:56 +0000 (17:01 +0000)]
[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Indexed Element, making them available
when +simd+fp16 is enabled.
The instructions added are: FMLA, FMLS, FMUL and FMULX.
The general form for these instructions is
<OP> <V>.<T>, <V>.<T>, <V>.h[<idx>]
where T is 4h or 8h
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector indexed element
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_ELEMENT_FP_H): New.
(aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
fmulx to the vector indexed element group.
Change-Id: Ib70cd4eaa6ea2938f84ac41f31d72644dbb0ceb4
Matthew Wahab [Mon, 14 Dec 2015 16:57:04 +0000 (16:57 +0000)]
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
Matthew Wahab [Mon, 14 Dec 2015 16:54:38 +0000 (16:54 +0000)]
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
Matthew Wahab [Mon, 14 Dec 2015 16:49:34 +0000 (16:49 +0000)]
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
Matthew Wahab [Mon, 14 Dec 2015 16:44:02 +0000 (16:44 +0000)]
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
Matthew Wahab [Mon, 14 Dec 2015 16:34:47 +0000 (16:34 +0000)]
[AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch set adds the 16-bit
Adv.SIMD vector and scalar instructions to binutils, making them
available when both +simd and +fp16 architecture extensions are enabled.
The series also adds support for a new vector type, 2H, used by the FP16
scalar pairwise instructions.
The patches in this series:
- Add a FP16 Adv.SIMD feature macro for use by the encoding/decoding
routines.
- Add FP16 instructions in the group Vector Three Register Same.
- Add FP16 instructions in the group Scalar Three Register Same.
- Add FP16 instructions in the group Vector Two Register Misc.
- Add FP16 instructions in the group Scalar Two Register Misc.
- Add FP16 instructions in the group Vector Indexed Element.
- Add FP16 instructions in the group Scalar Indexed Element.
- Add FP16 instructions in the group Adv.SIMD Across Lanes.
- Add FP16 instructions in the group Adv.SIMD Modified Immediate.
- Rework some code for handling vector types to weaken its assumptions
about available vector-types.
- Add support for the 2H vector type.
- Add FP16 instructions in the group Adv.SIMD Scalar Pairwise.
- Add FP16 instructions in the group Adv.SIMD Shift By Immediate.
- Add a FP16 instructions in the group Adv.SIMD Scalar Shift By
Immediate.
This patch adds the feature macro SIMD_F16 to the AArch64
encoding/decoding routines. It is used to decide when the new
instructions are available to the assembler and is true when both +simd
and +fp16 are selected.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-tbl.h (aarch64_feature_simd_f16): New.
(SIMD_F16): New.
Change-Id: Iee5a37928418f15e51dfaa927b24cafef7295e8f
Matthew Wahab [Mon, 14 Dec 2015 16:28:46 +0000 (16:28 +0000)]
[AArch64] Fix errors rebasing the ARMv8.2 AT and system registers patch
A mistake with rebasing the ARMv8.2 AT instruction patch left this part
+ /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
+ if ((reg->value == CPENS (0, C7, C9, 0)
+ || reg->value == CPENS (0, C7, C9, 1))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
+ return FALSE;
in aarch64_pstatefield_supported_p rather than in
aarch64_sys_ins_reg_supported_p, where it was supposed to be.
The patch adding support for id_aa64mmfr2_el1, also had the effect of
removing a conditional branch in aarch64_sys_reg_supported_p.
The effect of both of these is to suppress an error if some ARMv8.2
system registers are used with the wrong -march settings.
This patch fixes these mistakes.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
removed statement.
(aarch64_pstatefield_supported_p): Move feature checks for AT
registers ..
(aarch64_sys_ins_reg_supported_p): .. to here.
Change-Id: I48783d118eaaf0f3312e8b08a8340ef7af4e36a4
Andrew Burgess [Fri, 11 Dec 2015 17:06:35 +0000 (17:06 +0000)]
gdb: Use TYPE_LENGTH macro
Fixes a couple of places where we access the length field of the type
structure directly, rather than using the TYPE_LENGTH macro.
gdb/ChangeLog:
* i386-tdep.c (i386_mpx_info_bounds): Use TYPE_LENGTH.
(i386_mpx_set_bounds): Likewise.
* solib-darwin.c (darwin_load_image_infos): Likewise.
(darwin_solib_read_all_image_info_addr): Likewise.
Jan Beulich [Mon, 14 Dec 2015 08:25:10 +0000 (09:25 +0100)]
gas: free allocated symbol name in .cfi_label handling
I've just noticed this further oversights of the original commit.
Jan Beulich [Mon, 14 Dec 2015 08:24:04 +0000 (09:24 +0100)]
nm: basic COFF symbol type support for SysV-style symbol table dumping
GDB Administrator [Mon, 14 Dec 2015 00:00:19 +0000 (00:00 +0000)]
Automatic date update in version.in
Cary Coutant [Sun, 13 Dec 2015 22:04:24 +0000 (14:04 -0800)]
Remove const from return type of get_output_view.
gold/
* object.h (Object::get_output_view): remove const from return type.
(Object::do_get_output_view): Likewise.
(Sized_relobj_file::do_get_output_view): Likewise.
* reloc.cc (Sized_relobj_file::do_get_output_view): Likewise.
GDB Administrator [Sun, 13 Dec 2015 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in
Alan Modra [Sat, 12 Dec 2015 10:58:27 +0000 (21:28 +1030)]
Fix SH gas testsuite invalid assembly exposed by
ec9ab52c
* gas/sh/tlsd.s: Use .tdata not .tbss.
* gas/sh/tlsnopic.s: Likewise.
Alan Modra [Sat, 12 Dec 2015 06:56:33 +0000 (17:26 +1030)]
Enable 2 operand form of powerpc mfcr with -many
This is a workaround for a gcc bug.
PR 19359
* ppc-opc.c (insert_fxm): Remove "ignored" from error message.
(powerpc_opcodes): Remove single-operand mfcr.
GDB Administrator [Sat, 12 Dec 2015 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in
Andrew Burgess [Sat, 21 Nov 2015 11:13:07 +0000 (12:13 +0100)]
gdb: Extend help text for 'list' command.
Reference the 'listsize' setting in the help text for the 'list' command
to help users find this setting.
gdb/ChangeLog:
* cli/cli-cmds.c (_initialize_cli_cmds): Extend help text for
'list' command.
Andrew Burgess [Mon, 16 Nov 2015 09:39:43 +0000 (09:39 +0000)]
gdb: Add an error when 'list -' reaches the start of a file.
When a a user uses 'list +' to list forward through a source file they
eventually reach the end of the source file. Subsequent uses of 'list
+' result in an error message like this, that let the user know they are
at the end of the source file:
Line number XXX out of range; FILENAME has YYY lines.
Compare this to the current behaviour of 'list -' which lists backwards
through a source file. When the user reaches the beginning of the
source file, subsequent uses of 'list -' result in the command silently
returning. This can be confusing if the previous uses of 'list -' have
scrolled off the users display, the user receives no reminder that the
have already seen the start of the file.
After this commit a use of 'list -' when the user has already seen the
start of a file will receive the following error:
Already at the start of FILENAME.
gdb/ChangeLog:
* cli/cli-cmds.c (list_command): Add an error when trying to use
'-' to scan read off the start of the source file.
gdb/testsuite/ChangeLog:
* gdb.base/list.exp (test_list_forward): Add end of file error
test.
(test_repeat_list_command): Add end of file error test.
(test_list_backwards): Add beginning of file error test.
Andrew Burgess [Mon, 16 Nov 2015 09:33:32 +0000 (09:33 +0000)]
gdb: 'list' command, tweak handling of +/- arguments.
There is an inconsistency with the handling of the special +/- arguments
to the list command.
For the very first time that list is used (after the inferior has
changed locations) then only the first character of the argument string
is checked, so 'list +BLAH' will operate as 'list +' and 'list -----FOO'
will operate as 'list -'. This compares to each subsequent use of list,
where the whole argument string is checked, so 'list +BLAH' will try to
list lines of code around the function '+BLAH'.
This commit unifies the behaviour so that the whole argument string is
checked, in order to list the next 10, or previous 10 lines from a file
only 'list +' and 'list -' are now valid.
gdb/ChangeLog:
* cli/cli-cmds.c (list_command): Check that the argument string is
a single character, either '+' or '-'.
gdb/testsuite/ChangeLog:
* gdb.base/list.exp (test_list_invalid_args): New function,
defined, and called.
Andrew Burgess [Wed, 25 Nov 2015 00:11:43 +0000 (00:11 +0000)]
gdb: Make test names unique in list.exp.
gdb/testsuite/ChangeLog:
* gdb.base/list.exp (test_list): Make test names unique.
Andrew Burgess [Mon, 16 Nov 2015 09:30:35 +0000 (09:30 +0000)]
gdb: Small code restructure for list_command.
Move handling of special +/- arguments to the list_command function
inside a single if block, this helps group all related functionality
together. There should be no user visible changes after this commit.
gdb/ChangeLog:
* cli/cli-cmds.c (list_command): Move all handling of +/-
arguments into a single if block.
Andrew Burgess [Mon, 16 Nov 2015 09:27:40 +0000 (09:27 +0000)]
gdb: Use NULL instead of 0 for pointer comparison.
Small code cleanup, use NULL instead of 0 when checking pointers. There
should be no user visible changes after this commit.
gdb/ChangeLog:
* cli/cli-cmds.c (list_command): Use NULL instead of 0 when
checking pointers.
Andrew Burgess [Thu, 12 Nov 2015 09:48:32 +0000 (09:48 +0000)]
gdb: Make lines_to_list variable static.
Small clean up, make variable static.
gdb/ChangeLog:
* source.c (lines_to_list): Make static.
Cary Coutant [Fri, 11 Dec 2015 22:20:41 +0000 (14:20 -0800)]
Pass relocations to Target::do_calls_non_split.
gold/
* target.h (Target::calls_non_split): Add prelocs, reloc_count
parameters.
(Target::do_calls_non_split): Likewise.
* target.cc (Target::do_calls_non_split): Likewise.
* reloc.cc (Sized_relobj_file::split_stack_adjust_reltype): Adjust
call to Target::calls_non_split.
* i386.cc (Target_i386::do_calls_non_split): Add prelocs, reloc_count
parameters.
* powerpc.cc (Target_powerpc::do_calls_non_split): Likewise.
* x86_64.cc (Target_x86_64::do_calls_non_split): Likewise.
Cary Coutant [Fri, 11 Dec 2015 22:01:22 +0000 (14:01 -0800)]
Make output views accessible to Target during do_relocate().
gold/
* object.cc (Sized_relobj_file::Sized_relobj_file): Initialize
output_views_.
* object.h (Object::get_output_view): New function.
(Object::do_get_output_view): New function.
(Sized_relobj_file::do_get_output_view): New function.
(Sized_relobj_file::output_views_): New data member.
* reloc.cc: (Sized_relobj_file::do_relocate): Store pointer to
output views in class object.
(Sized_relobj_file::do_get_output_view): New function.
Yao Qi [Fri, 11 Dec 2015 16:21:09 +0000 (16:21 +0000)]
Remove gdb.base/coremaker2.c
I happen to find that coremaker2.c isn't used in the testsuite (if I
don't miss anything). I don't believe it until I see this ChangeLog
entry,
1999-11-18 Fred Fish <fnf@cygnus.com>
* gdb.base/coremaker2.c: Add sample program for generating
cores that is more self contained than coremaker.c. Eventually
I'll add more code to this and tie it into the testsuite.
looks Fred didn't "tie it into testsuite" later.
gdb/testsuite:
2015-12-11 Yao Qi <yao.qi@linaro.org>
* gdb.base/coremaker2.c: Remove.
Yao Qi [Fri, 11 Dec 2015 11:19:52 +0000 (11:19 +0000)]
Understand arm breakpoints in aarch64_breakpoint_at
AArch64 GDBserver can debug ARM program, and it should recognize
various arm breakpoint instructions. This patch should be included
in
17b1509a.
gdb/gdbserver:
2015-12-11 Yao Qi <yao.qi@linaro.org>
* linux-aarch64-low.c (aarch64_breakpoint_at): Call
arm_breakpoint_at if the process is 32-bit.
Yao Qi [Fri, 11 Dec 2015 11:19:52 +0000 (11:19 +0000)]
Use arm_eabi_breakpoint on aarch32
Nowdays, GDBserver chooses arm breakpoint instructions by checking
macro __ARM_EABI__. When aarch64 GDBserver debugs arm program,
arm_eabi_breakpoint is still needed, but __ARM_EABI__ isn't defined
in aarch64 compiler. This causes GDBserver chooses the wrong
breakpoint instruction for arm program. This patch fixes it.
gdb/gdbserver:
2015-12-11 Yao Qi <yao.qi@linaro.org>
* linux-aarch32-low.c [__aarch64__]: Use arm_abi_breakpoint
arm breakpoint.
Matthew Wahab [Fri, 11 Dec 2015 10:22:40 +0000 (10:22 +0000)]
[AArch64][Patch 5/5] Add instruction PSB CSYNC
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. This patch adds the instruction to
binutils as a HINT alias that takes an operand.
A new operand type, AARCH64_OPND_BARRIER_PSB, is added to represent the
operand to PSB. A parser for the operand type is added to the assembler
and a printer to the disassembler. The operand name "csync" is added to
the list of HINT options with HINT number #17. Encoding and decoding of
the operand is handled by the ins_hint/ext_hint functions added in the
preceding patches.
gas/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_hint_opt_hsh): New.
(parse_barrier_psb): New.
(parse_operands): Add case for AARCH64_OPND_BARRIER_PSB.
(md_begin): Set up aarch64_hint_opt_hsh.
gas/testsuite/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/system-2.d: Enable the statistical profiling
extension. Update the expected output.
* gas/aarch64/system-2.s: Add tests for PSB CSYNC.
* gas/aarch64/system.d: Update the expected output.
include/opcode/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (aarch64_hint_options): Add "csync".
(aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB.
* aarch64-tbl.h (aarch64_feature_stat_profile): New.
(STAT_PROFILE): New.
(aarch64_opcode_table): Add "psb".
(AARCH64_OPERANDS): Add "BARRIER_PSB".
Change-Id: I5ffb672d26a8b15b48785478d359350a9b70ca09
Matthew Wahab [Fri, 11 Dec 2015 10:11:27 +0000 (10:11 +0000)]
[AArch64][Patch 4/5] Support HINT aliases taking operands.
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. This patch adds support for aliases
of HINT which take an operand, adding a table to store operand names and
their matching hint number as well as encoding and decoding functions
for such operands. Parsing and printing the operands are deferred to any
support added for aliases with such operands.
include/opcode/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_hint_options): Declare.
(aarch64_opnd_info): Add field hint_option.
opcodes/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm.c (aarch64_ins_hint): New.
* aarch64-asm.h (aarch64_ins_hint): Declare.
* aarch64-dis.c (aarch64_ext_hint): New.
* aarch64-dis.h (aarch64_ext_hint): Declare.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (aarch64_hint_options): New.
* aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
Change-Id: I2205038fc1c47d3025d1f0bc2fbf405b5575b287
Matthew Wahab [Fri, 11 Dec 2015 09:56:07 +0000 (09:56 +0000)]
[AArch64][Patch 3/5] Adjust maximum number of instruction aliases.
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. The HINT instruction currently has 8
aliases, which is the maximum number allowed. This patch raises to 16
the limit on the number of aliases an instruction can have.
opcodes/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
Change-Id: I131044bf6e0fe0940a9e7478d9bf52137748907d
Matthew Wahab [Fri, 11 Dec 2015 09:52:11 +0000 (09:52 +0000)]
[AArch64][Patch 2/5] Add Statistical Profiling Extension system registers.
The Statistical Profile extension included in the ARMv8.2 architecture
adds a number of system registers. This patch adds the registers to
binutils, making them available when the architecture extension
"+profile" is enabled.
opcodes/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
pmscr_el2.
(aarch64_sys_reg_supported_p): Add architecture feature tests for
the new registers.
gas/testsuite/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.s: Add tests for the statistical profiling
system registers.
* gas/aarch64/sysreg-2.d: Enable the statistical profiling
extension and update the expected output.
Change-Id: Ibf23ad34db7c33f0fcd30010b796748b38be6efb
Matthew Wahab [Fri, 11 Dec 2015 09:30:26 +0000 (09:30 +0000)]
[AArch64][Patch 1/5] Support the ARMv8.2 Statistical Profiling Extension.
The Statistical Profile extension included in the ARMv8.2 architecture
adds a number of system registers and a new instruction. This patch set
adds support for the extension to binutils, enabled when
-march=armv8.2-a+profile is given.
The patches in this series:
- Add the new command line option and feature flags.
- Add the new system registers.
- Adjust the maximum number of aliases permitted for an instruction.
- Add support for HINT aliases which take operands.
- Add the new instruction, an alias of the HINT instruction.
This patch adds the option "profile" to the permitted architecture
extensions, disabling it by default.
gas/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_features): Add "profile".
* doc/c-aarch64.texi (AArch64 Extensions): Add "profile".
include/opcode/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_PROFILE): New.
Change-Id: If9bb4a9b69a264180f96f8ffaf10b15ced273699
GDB Administrator [Fri, 11 Dec 2015 00:00:13 +0000 (00:00 +0000)]
Automatic date update in version.in
H.J. Lu [Thu, 10 Dec 2015 20:35:35 +0000 (12:35 -0800)]
ld -r doesn't need plugin for slim lto object
Plugin isn't required on slim lto object for relocatable link.
bfd/
PR ld/19317
* linker.c (_bfd_generic_link_add_one_symbol): Don't complain
plugin needed to handle slim lto object for relocatable link.
ld/testsuite/
PR ld/19317
* ld-plugin/lto.exp (lto_no_fat): New.
(lto_link_tests): Add a test for PR ld/19317.
(lto_run_tests): Likewise.
(run_ld_link_tests): Likewise.
Antoine Tremblay [Thu, 10 Dec 2015 19:43:48 +0000 (14:43 -0500)]
Fix regression revealed by corethreads.exp
This patch fixes a regression introduced by:
https://sourceware.org/ml/gdb-patches/2015-12/msg00192.html
We can't use thread_from_lwp with core files. As mentioned in a comment,
td_ta_map_lwp2thr uses ps_get_thread_area, but we can't use that
currently on core targets, as it uses ptrace directly.
Use directly record_thread instead.
This fixes :
PASS -> FAIL: gdb.threads/corethreads.exp: thread0 found
PASS -> FAIL: gdb.threads/corethreads.exp: thread1 found
gdb/ChangeLog:
* linux-thread-db.c (find_new_threads_callback): Use record_thread.
H.J. Lu [Thu, 10 Dec 2015 19:28:48 +0000 (11:28 -0800)]
ld -r doesn't need plugin for slim lto object
Plugin isn't required on slim lto object for relocatable link.
PR ld/19317
* symtab.cc (Symbol_table::add_from_relobj): Don't complain
plugin needed to handle slim lto object for relocatable link.
Pedro Alves [Thu, 10 Dec 2015 17:47:57 +0000 (17:47 +0000)]
[gdb/doc] Explain that there's always a thread
This warning is a few years out of date -- there's always a thread
nowadays.
gdb/doc/ChangeLog:
* gdb.texinfo (Threads): Replace warning with explanation
about single-threaded programs.
Matthew Wahab [Thu, 10 Dec 2015 16:58:51 +0000 (16:58 +0000)]
[Aarch64] Support ARMv8.2 AT instructions
ARMv8.2 adds new instructions AT S1E1RP and AT S1E1WP to Aarch64. This
patch adds support for the instructions, making them available when
-march=armv8.2-a is selected.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Update for new tests for AT S1E1RP and
AT S1E1WP.
* gas/aarch64/sysreg-2.s: Add tests for AT S1E1RP and AT S1E1WP.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
(aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
feature test for "s1e1rp" and "s1e1wp".
Change-Id: I09e1044b629ab0a34b03c423e8d4e71ff92daad4
Pedro Alves [Thu, 10 Dec 2015 11:43:19 +0000 (11:43 +0000)]
[gdb/doc] Remove references to no-longer-supported systems
HP-UX and SGI/IRIX are no longer supported. Remove references
throughout.
AFAICS from the sources, "catch fork" seems to be supported in
multiple Unix systems -- just remove the "only works on xxx" remarks.
Update the list of supported shared library types.
gdb/doc/ChangeLog:
* gdb.texinfo (Threads): Remove mention of SGI.
(Forks): Remove mention of HP-UX.
(Breakpoints): Remove mention of HP-UX.
(Set Watchpoints) <hardware watchpoints>: Don't mention HP-UX.
Reword in terms of architectures.
(Set Catchpoints) <catch exec, catch fork, catch vfork>: Don't
mention supported systems.
(Convenience Vars): Don't mention HP-UX.
(Jumping): Remove mention of HP-UX in comment.
(Files) <shared libraries>: Update supported shared library types
list. Remove mention of HP-UX.
(Native): Remove HP-UX subsection.
(SVR4 Process Information): Remove mention of HP-UX.
Pedro Alves [Thu, 10 Dec 2015 16:49:32 +0000 (16:49 +0000)]
Remove "spaces" references from gdb.multi/base.exp
I think these references to "spaces" came from the original multi-exec
submission that exposed "symbol spaces" to the user and had a
different UI, and then survived a global find/replace.
gdb/testsuite/ChangeLog:
2015-12-10 Pedro Alves <palves@redhat.com>
* gdb.multi/base.exp: Remove stale "spaces" references.
Matthew Wahab [Thu, 10 Dec 2015 16:38:44 +0000 (16:38 +0000)]
[AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction.
ARMv8.2 adds the new system instruction DC CVAP. This patch adds support
for the instruction to binutils, enabled when -march=armv8.2-a is
selected.
gas/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (parse_sys_ins_reg): Add check of
architectural support for system register.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Add tests for dc instruction.
* gas/aarch64/sysreg-2.s: Add uses of dc instruction.
include/opcode/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
(aarch64_sys_ins_reg_supported_p): New.
Change-Id: I3158b97d9bbee9644c2d0e2986db807412ef1053
Matthew Wahab [Thu, 10 Dec 2015 16:31:35 +0000 (16:31 +0000)]
[AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.
ARMv8.2 adds the new system instruction DC CVAP. This patch series adds
support for this instruction to binutils, enabled when -march=armv8.2-a
is selected.
The AArch64 binutils record of some system registers uses a boolean
value to hold the single flag currently supported for them. To allow
these registers to be limited to specific architectures, the first patch
in this series replaces the boolean flag with a bitset and feature test.
include/opcode/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
(aarch64_sys_ins_reg_has_xt): Declare.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
with aarch64_sys_ins_reg_has_xt.
(aarch64_ext_sysins_op): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): Likewise.
(F_HASXT): New.
(aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
(aarch64_sys_regs_dc): Likewise.
(aarch64_sys_regs_at): Likewise.
(aarch64_sys_regs_tlbi): Likewise.
(aarch64_sys_ins_reg_has_xt): New.
Change-Id: I363637a6c3f54d7ffff953b3a0734e8139cae819
Pedro Alves [Thu, 10 Dec 2015 16:21:06 +0000 (16:21 +0000)]
Stop using nowarnings in gdb/testsuite/gdb.multi/
Several of the gdb.multi tests use the "nowarnings" option to suppress
warnings. The warnings in question all come from missing headers,
like e.g.:
src/gdb/testsuite/gdb.multi/multi-arch-exec.c:28:3: warning: incompatible implicit declaration of built-in function 'exit' [enabled by default]
exit (1);
^
There's no point in trying to avoid to include standard headers. In
gdb.base/hangout.c's case, it's even dangerous, as that file calls
printf. In order to compile a call to a variatic function correctly,
a declaration must be visible.
gdb/testsuite/ChangeLog:
2015-12-10 Pedro Alves <palves@redhat.com>
* gdb.multi/base.exp: Don't use nowarnings.
* gdb.multi/bkpt-multi-exec.exp: Don't use nowarnings.
* gdb.multi/hangout.c: Include stdio.h.
* gdb.multi/hello.c: Include stdlib.h.
* gdb.multi/multi-arch-exec.c: Include stdlib.h.
* gdb.multi/multi-arch-exec.exp: Don't use nowarnings.
* gdb.multi/multi-arch.exp: Don't use nowarnings.
Kwok Cheung Yeung [Thu, 10 Dec 2015 16:11:07 +0000 (16:11 +0000)]
ld: Fix LTO for MinGW targets
When creating a dummy BFD for an IR file, the output BFD is used as
a template for the new BFD, when it needs to be the input BFD passed
into the function when not dealing with a BFD plugin.
On most targets this is not an issue as the input and output formats
are the same anyway, but on MinGW targets, there are two variant
formats used (pe-i386/pe-x86-64 and pei-i386/pei-x86-64) which are
similar but not interchangeable here.
PR ld/18199
* plugin.c (plugin_get_ir_dummy_bfd): Use srctemplate as the
template when calling bfd_create if it does not use the BFD
plugin target vector.
Matthew Wahab [Thu, 10 Dec 2015 16:01:29 +0000 (16:01 +0000)]
[AArch64][binutils] Add support for ARMv8.2 PSTATE.UAO.
ARMv8.2 adds a new control bit PSTATE.UAO. This patch adds support for
this bit to binutils, following the same basic pattern as for
PSTATE.PAN. The new control bit is only available when -march=armv8.2-a
is specified.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/uao-directive.d: New.
* gas/aarch64/uao.d: New.
* gas/aarch64/uao.s: New.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs): Add "uao".
(aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
(aarch64_pstatefields): Add "uao".
(aarch64_pstatefield_supported_p): Add checks for "uao".
Change-Id: Id571628ac5227b78aaf1876e85d15d7b6c0a2896
Jose E. Marchesi [Thu, 10 Dec 2015 16:01:35 +0000 (11:01 -0500)]
gas: documentation for the SPARC %dN and %qN fp registers notation
gas/ChangeLog:
2015-12-10 Jose E. Marchesi <jose.marchesi@oracle.com>
* doc/c-sparc.texi (Sparc-Regs): Document the %dN and %qN notation
for floating-point registers.
Antoine Tremblay [Thu, 10 Dec 2015 15:44:08 +0000 (10:44 -0500)]
Remove support for thread events without PTRACE_EVENT_CLONE in GDB
Before, on systems that did not support PTRACE_EVENT_CLONE, both GDB and
GDBServer coordinated with libthread_db.so to insert breakpoints at magic
locations in libpthread.so, in order to break at thread creation and
thread death.
Support for thread events was removed from GDBServer as patch:
https://sourceware.org/ml/gdb-patches/2015-11/msg00466.html
This patch removes support for thread events in GDB.
No regressions found on Ubuntu 14.04 x86_64.
gdb/ChangeLog:
* breakpoint.c (remove_thread_event_breakpoints): Remove.
* breakpoint.h (remove_thread_event_breakpoints): Remove
declaration.
* linux-nat.c (in_pid_list_p): Remove.
(lin_lwp_attach_lwp): Remove.
* linux-nat.h (lin_lwp_attach_lwp): Remove declaration.
* linux-thread-db.c (thread_db_use_events): Remove.
(struct thread_db_info) <td_create_bp_addr>: Remove.
<td_death_bp_addr>: Likewise.
<td_ta_event_addr_p>: Likewise.
<td_ta_set_event_p>: Likewise.
<td_ta_clear_event_p>: Likewise.
<td_ta_event_getmsg_p>: Likewise.
<td_thr_event_enable_p>: Likewise.
(attach_thread): Likewise.
(detach_thread): Likewise.
(have_threads_callback): Likewise.
(have_threads): Likewise.
(enable_thread_event): Likewise.
(enable_thread_event_reporting): Likewise.
(try_thread_db_load_1): Remove td_ta_event_addr, td_ta_set_event,
td_ta_clear_event, td_ta_event_getmsg, td_thr_event_enable
initializations.
(try_thread_db_load_1): Remove enable_thread_event_reporting call.
(disable_thread_event_reporting): Remove.
(record_thread): Adapt to thread_db_use_event removal.
(detach_thread): Remove.
(thread_db_detach): Adapt to thread_db_use_event removal.
(check_event): Remove.
(thread_db_wait): Adapt to thread events support removal.
(thread_db_mourn_inferior): Likewise.
(find_new_threads_callback): Likewise.
(find_new_threads_once): Likewise.
(thread_db_update_thread_list): Likewise.
Matthew Wahab [Thu, 10 Dec 2015 14:09:03 +0000 (14:09 +0000)]
[AArch64][PATCH 2/2] Add RAS system registers.
The ARMv8.2 RAS extension adds a number of new registers. This patch
adds the registers and makes them available whenever the RAS extension
is enabled, as it is when -march=armv8.2-a is selected.
The new registers are:
erridr_el1, errselr_el1, erxfr_el1, erxctlr, erxaddr_el1,
erxmisc0_el1, erxmisc1_el1, vsesr_el2, disr_el1 and
vdisr_el2.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Add tests for new registers.
* gas/aarch64/sysreg-2.s: Likewise. Also replace some spaces with
tabs.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
"errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
"erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
(aarch64_sys_reg_supported_p): Add architecture feature tests for
new registers.
Change-Id: I8a01a0f0ee7987f89eead32650f6afcc749b3c74
Matthew Wahab [Thu, 10 Dec 2015 14:05:01 +0000 (14:05 +0000)]
[AArch64][PATCH 1/2] Add support for RAS instruction ESB.
The ARMv8.2 RAS extension adds a new barrier instruction ESB as an alias
and the preferred form of HINT 16.
This patch adds an architectural feature flag for the RAS extension and
includes it in the features selected enabled by -march=armv8.2-a. It
also adds the ESB instruction, making it available whenever the RAS
feature is enabled.
Because ESB is the preferred form and because the target architecture
isn't available to the disassembler, HINT 16 will be disassembled as ESB
even when the target has no support for the RAS extension.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/system-2.d: New.
* gas/aarch64/system-2.s: New.
* gas/aarch64/system.d: Adjust expected output for HINT 16.
include/opcode/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_RAS): New.
(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-tbl.h (aarch64_feature_ras): New.
(RAS): New.
(aarch64_opcode_table): Add "esb".
Change-Id: Id4713917da15cca3b977284f43febd1c9b3d9faf
Matthew Wahab [Thu, 10 Dec 2015 13:58:21 +0000 (13:58 +0000)]
[AArch64] Fix ARMv8.1 and ARMv8.2 feature settings.
ARMv8.1 includes CRC as a required extension but this isn't reflected in
the features enabled by -march=armv8.1-a. The FP16 feature modifier also
clashes with AARCH64_FEATURE_V8_1 and the list of features for ARMv8.2
is missing ARMv8.1 features.
This patch enables +crc for -march values of armv8.1-a and later. It
also fixes the values for AARCH64_FEATURE_F16 and makes
AARCH64_ARCH_V8_2 and superset of AARCH64_ARCH_V8_2.
gas/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* doc/c-aarch64.texi (AArch64 Extensions): Update entry for crc.
include/opcode
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_F16): Fix clash with
AARCH64_FEATURE_V8_1.
(AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
AARCH64_FEATURE_V8_1.
Change-Id: I8af5369f6df2430b28f6cec92870d2a4d14a7431
Pedro Alves [Thu, 10 Dec 2015 11:39:58 +0000 (11:39 +0000)]
[gdb/doc] Stack, Examining the Stack: Reorder menu
Commit
fc58fa65d454 (gdb/doc: Restructure frame command documentation)
reordered the sections in the 'Examining the Stack' chapter, but
missed updating the menu:
src/gdb/doc/gdb.texinfo:6968: warning: node next `Backtrace' in menu `Frame Filter Management' and in sectioning `Selection' differ
src/gdb/doc/gdb.texinfo:7167: warning: node prev `Selection' in menu `Frame Filter Management' and in sectioning `Backtrace' differ
src/gdb/doc/gdb.texinfo:7252: warning: node `Frame Filter Management' is next for `Frame Info' in sectioning but not in menu
src/gdb/doc/gdb.texinfo:7317: warning: node `Selection' is next for `Frame Filter Management' in menu but not in sectioning
src/gdb/doc/gdb.texinfo:7317: warning: node prev `Frame Filter Management' in menu `Backtrace' and in sectioning `Frame Info' differ
gdb/doc/ChangeLog:
2015-12-10 Pedro Alves <palves@redhat.com>
* gdb.texinfo (Stack): Reorder menu.
Andrew Burgess [Fri, 16 Oct 2015 08:08:19 +0000 (10:08 +0200)]
gdb: Handle multiple base address in debug_ranges data.
It is possible to use multiple base addresses within a single address
range series, within the .debug_ranges section. The following is a
simplified example for 32-bit addresses:
.section ".debug_ranges"
.4byte 0xffffffff
.4byte BASE_1
.4byte START_OFFSET_1
.4byte END_OFFSET_1
.4byte START_OFFSET_2
.4byte END_OFFSET_2
.4byte 0xffffffff
.4byte BASE_2
.4byte START_OFFSET_3
.4byte END_OFFSET_3
.4byte 0
.4byte 0
In this example START/END 1 and 2 are relative to BASE_1, while
START/END 3 are relative to BASE_2.
Currently gdb does not correctly parse this DWARF, resulting in
corrupted address range information. This commit fixes this issue, and
adds a new test to cover this case.
In order to support testing of this feature extensions were made to the
testsuite dwarf assembler, additional functionality was added to the
.debug_line generation function, and a new function for generating the
.debug_ranges section was added.
gdb/ChangeLog:
* dwarf2read.c (dwarf2_ranges_read): Unify and fix base address
reading code.
gdb/testsuite/ChangeLog:
* gdb.dwarf2/dw2-ranges-base.c: New file.
* gdb.dwarf2/dw2-ranges-base.exp: New file.
* lib/dwarf.exp (namespace eval Dwarf): Add new variables to
support additional line table, and debug ranges generation.
(Dwarf::ranges): New function, generate .debug_ranges.
(Dwarf::lines): Support generating simple line table programs.
(Dwarf::assemble): Initialise new namespace variables.
Andrew Burgess [Wed, 9 Dec 2015 19:13:54 +0000 (19:13 +0000)]
arc/gas: Accept, but ignore, dummy arguments.
There's a set of legacy command line arguments that the arc assembler
still accepts, however, these arguments not longer have any effect on
the assembler.
Currently we return false from md_parse_option for all of these
arguments, with the result that the assembler terminates with an error
message.
We should return true indicating that the argument has been accepted,
even though we ignore it.
gas/ChangeLog:
* config/tc-arc.c (md_parse_option): Return 1 in order to accept
dummy arguments.
Sandra Loosemore [Thu, 10 Dec 2015 00:13:58 +0000 (16:13 -0800)]
Fix GOT address computations in initial PLT entries for nios2.
2015-12-09 Sandra Loosemore <sandra@codesourcery.com>
bfd/
* elf32-nios2.c (nios2_elf32_finish_dynamic_sections): Correct
%hiadj/%lo computations for _GLOBAL_OFFSET_TABLE_ in initial
PLT entries. Assert alignment requirements.
GDB Administrator [Thu, 10 Dec 2015 00:00:12 +0000 (00:00 +0000)]
Automatic date update in version.in
Kevin Buettner [Wed, 25 Nov 2015 04:53:13 +0000 (21:53 -0700)]
dwarf2loc.c: Perform a pointer to address conversion for DWARF_VALUE_MEMORY.
This patch fixes the following failures for rl78-elf:
FAIL: gdb.base/vla-datatypes.exp: print int_vla
FAIL: gdb.base/vla-datatypes.exp: print unsigned_int_vla
FAIL: gdb.base/vla-datatypes.exp: print double_vla
FAIL: gdb.base/vla-datatypes.exp: print float_vla
FAIL: gdb.base/vla-datatypes.exp: print long_vla
FAIL: gdb.base/vla-datatypes.exp: print unsigned_long_vla
FAIL: gdb.base/vla-datatypes.exp: print char_vla
FAIL: gdb.base/vla-datatypes.exp: print short_vla
FAIL: gdb.base/vla-datatypes.exp: print unsigned_short_vla
FAIL: gdb.base/vla-datatypes.exp: print unsigned_char_vla
FAIL: gdb.base/vla-datatypes.exp: print foo_vla
FAIL: gdb.base/vla-datatypes.exp: print bar_vla
FAIL: gdb.base/vla-datatypes.exp: print vla_struct_object
FAIL: gdb.base/vla-datatypes.exp: print vla_union_object
FAIL: gdb.base/vla-ptr.exp: print td_vla
FAIL: gdb.mi/mi-vla-c99.exp: evaluate complete vla
The first failure in this bunch occurs due to printing an incorrect
result for a variable length array:
print int_vla
$1 = {-1, -1, -1, -1, -1}
The result should actually be this:
$1 = {0, 2, 4, 6, 8}
When I started examining this bug, I found that printing an
individual array element worked correctly. E.g. "print int_vla[2]"
resulted in 4 being printed. I have not looked closely to see why
this is the case.
I found that evaluation of the location expression for int_vla was
causing problems. This is the relevant DWARF entry for int_vla:
<2><15a>: Abbrev Number: 10 (DW_TAG_variable)
<15b> DW_AT_name : (indirect string, offset: 0xbf): int_vla
<15f> DW_AT_decl_file : 1
<160> DW_AT_decl_line : 35
<161> DW_AT_type : <0x393>
<165> DW_AT_location : 4 byte block: 86 7a 94 2 (DW_OP_breg22 (r22): -6; DW_OP_deref_size: 2)
I found that DW_OP_breg22 was providing a correct result.
DW_OP_deref_size was fetching the correct value from memory. However,
the value being fetched should be considered a pointer.
DW_OP_deref_size zero extends the fetched value prior to pushing
it onto the evaluation stack. (The DWARF-4 document specifies this
action; so GDB is faithfully implementing the DWARF-4 specification.)
However, zero extending the pointer is not sufficient for converting
that value to an address for rl78 and (perhaps) other architectures
which define a `pointer_to_address' method. (I suspect that m32c
would have the same problem.)
Ideally, we would perform the pointer to address conversion in
DW_OP_deref_size. We don't, however, know the type of the object
that the address refers to in DW_OP_deref_size. I can't think
of a way to infer the type at that point in the code.
Before proceeding, I should note that there are two other DWARF
operations that could be used in place of DW_OP_deref_size. One of
these is DW_OP_GNU_deref_type. Current GDB implements this operation,
but as is obvious from the name, it is non-standard DWARF. The other
operation is DW_OP_xderef_size. Even though it's part of DWARF-2
through DWARF-4 specifications, it's not presently implemented in GDB.
Present day GCC does not output dwarf expressions containing this
operation either. [Of the two, I like DW_OP_GNU_deref_type better.
Using it avoids the need to specify an "address space identifier".
(GCC, GDB, and other non-free tools all need to agree on the meanings
of these identifiers.)]
Back to the bug analysis...
The closest consumer of the DW_OP_deref_size result is the
DWARF_VALUE_MEMORY case in dwarf2_evaluate_loc_desc_full. At that
location, we do know the object type to which the address is intended
to refer. I added code to perform a pointer to address conversion at
this location. (See the patch.)
I do have some misgivings regarding this patch. As noted earlier, it
would really be better to perform the pointer to address conversion in
DW_OP_deref_size. I can't, however, think of a way to make this work.
Changing GCC to output one of the other aforementioned operations might
be preferable but, as noted earlier, these solutions have problems as
well. Long term, I think it'd be good to have something like
DW_OP_GNU_deref_type become part of the standard. If that can't or
won't happen, we'll need to implement DW_OP_xderef_size.
But until that happens, this patch will work for expressions in which
DW_OP_deref_size occurs last. It should even work for dereferences
followed by adding an offset. I don't think it'll work for more than
one dereference in the same expression.
gdb/ChangeLog:
* dwarf2loc.c (dwarf2_evaluate_loc_desc_full): Perform a pointer
to address conversion for DWARF_VALUE_MEMORY.
Kevin Buettner [Tue, 8 Dec 2015 06:07:29 +0000 (23:07 -0700)]
gdb.base/async.exp: Handle "asynchronous execution not supported"
This change eliminates some failures on simulator targets and makes
the test run a bit quicker too - without this change, we have to wait
for timeouts.
gdb/testsuite/ChangeLog:
* gdb.base/async.exp (proc test_background): Add case
for asynchronous execution not supported.
H.J. Lu [Wed, 9 Dec 2015 16:01:57 +0000 (08:01 -0800)]
Implement Intel OSPKE instructions
This patch implements Intel OSPKE instructions documented in Intel64
and IA-32 Architectures Software Developer’s Manual Volume 2, September
2015.
gas/testsuite/
* gas/i386/i386.exp: Run ospke and x86-64-ospke.
* gas/i386/ospke.d: New file.
* gas/i386/ospke.s: Likewise.
* gas/i386/x86-64-ospke.d: Likewise.
opcodes/
* i386-dis.c (MOD_0F01_REG_5): New.
(RM_0F01_REG_5): Likewise.
(reg_table): Use MOD_0F01_REG_5.
(mod_table): Add MOD_0F01_REG_5.
(rm_table): Add RM_0F01_REG_5.
* i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
(cpu_flags): Add CpuOSPKE.
* i386-opc.h (CpuOSPKE): New.
(i386_cpu_flags): Add cpuospke.
* i386-opc.tbl: Add rdpkru and wrpkru instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
Jan Beulich [Wed, 9 Dec 2015 13:35:07 +0000 (14:35 +0100)]
gas/ELF: slightly relax elf/file*.d expectations
Despite the re-ordering done for the file symbols, some targets manage
to put section symbols ahead of it.
Luis Machado [Wed, 9 Dec 2015 12:56:27 +0000 (10:56 -0200)]
varobj zero-padded hexadecimal format
This set of patches add support for the zero-padded hexadecimal format for
varobj's, defined as "zero-hexadecimal". We currently only support regular
non-zero-padded hexadecimal.
Talking with IDE developers, they would like to have this option that is
already available to GDB's print/x commands, in the CLI, as 'z'.
gdb/ChangeLog:
2015-12-09 Luis Machado <lgustavo@codesourcery.com>
* gdb/mi/mi-cmd-var.c (mi_parse_format): Handle new "zero-hexadecimal"
format.
* gdb/varobj.c (varobj_format_string): Add "zero-hexadecimal" entry.
(format_code): Add 'z' entry.
(varobj_set_display_format): Handle FORMAT_ZHEXADECIMAL.
* gdb/varobj.h (varobj_display_formats) <FORMAT_ZHEXADECIMAL>: New enum
field.
* NEWS: Add new note to MI changes citing the new zero-hexadecimal
format for -var-set-format.
gdb/doc/ChangeLog:
2015-12-09 Luis Machado <lgustavo@codesourcery.com>
* gdb.texinfo (GDB/MI Variable Objects): Update text to mention
-var-set-format's new zero-hexadecimal format.
gdb/testsuite/ChangeLog:
2015-12-09 Luis Machado <lgustavo@codesourcery.com>
* gdb.mi/mi-var-display.exp: Add new checks for the zero-hexadecimal
format and change test names to make them unique.
Jose E. Marchesi [Wed, 9 Dec 2015 12:32:52 +0000 (07:32 -0500)]
sparc: support %dN and %qN syntax for FP registers.
The SPARC Refence Manual documents the %dN and %qN syntax to
refer to double and quad-precision floating-point registers,
respectively. See OSA2015 Appendix C, Assembly Language Syntax,
C1.1 Register Names.
This patch adds support for these names to GAS. This eases the
porting of software from Solaris to GNU/Linux, as these register
names have been supported by the Solaris linker for a long time
and many assembler require that support.
gas/ChangeLog:
2015-12-09 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_ip): Support %dN and %qN notation for
double and quad-precision floating-point registers.
Ruslan Kabatsayev [Wed, 9 Dec 2015 12:17:40 +0000 (12:17 +0000)]
Fix wrong output of x87 registers due to truncation to double on amd64
When `info float` is used on an AMD64 system, GDB prints
floating-point values of x87 registers with raw contents like
0x361a867a8e0527397ce0 or 0xc4f988454a1ddd3cfdab wrongly.
This happens due to truncation to double, after which the former
becomes 0.0, and the latter becomes negative infinity. This is caused
by failed detection of x86-64 host, which results in setting
gdb_host_{float,double,long_double}_format to zeros.
This commit fixes this misdetection, and adds a test to make sure
future commits don't introduce a regression here.
gdb/ChangeLog:
2015-12-09 Ruslan Kabatsayev <b7.
10110111@gmail.com>
PR gdb/18702
* configure.host: Fix detection of x86_64 host when setting
floatformats.
gdb/testsuite/ChangeLog:
2015-12-09 Ruslan Kabatsayev <b7.
10110111@gmail.com>
Pedro Alves <pedro@redhat.com>
PR gdb/18702
Add checking of floatformats setup on x86_64 hosts.
* gdb.arch/i386-float.S (main): Load bigval and smallval.
(smallval, bigval): New labels/constants.
* gdb.arch/i386-float.exp: Use with_test_prefix and test "info
float" after loading bigval and smallval.
Nick Clifton [Wed, 9 Dec 2015 12:01:19 +0000 (12:01 +0000)]
Fix compile time warning building RX target.
Alan Modra [Wed, 9 Dec 2015 00:00:18 +0000 (10:30 +1030)]
[GOLD] PowerPC style fix
* powerpc.cc (Target_powerpc::Relocate::relocate): New constant
d_offset. Use throughout.
(Target_powerpc::relocate_relocs): Likewise.
Alan Modra [Tue, 8 Dec 2015 23:48:44 +0000 (10:18 +1030)]
[GOLD] Edit PowerPC64 ELFv2 function entry code
In an fixed position executable, the entry code does not need to be
PIC and can thus lose a dependency on r12.
* powerpc.cc (Target_powerpc::Relocate::relocate): Edit ELFv2
entry code.
(Target_powerpc::relocate_relocs): Edit relocs to suit.
Alan Modra [Tue, 8 Dec 2015 23:48:30 +0000 (10:18 +1030)]
[GOLD] Relocate::relocate() params
Some linker code editing needs to change multiple insns. In some
cases multiple relocations are involved and it is not sufficient to
make the changes independently as relocations are processed, because
doing so might lead to a partial edit. So in order to safely edit we
need all the relocations available in relocate(). Also, to emit
edited relocs corresponding to the edited code sequence we need some
way to pass information from relocate() to relocate_relocs(),
particularly if the edit depends on insns. We can't modify input
relocs in relocate() as they are mmapped PROT_READ, nor it is
particularly clean to write relocs to the output at that stage. So
add a Relocatable_relocs* field to relinfo to mark edited relocs.
Given that relocate is passed the raw reloc pointer, it makes sense to
remove the rel/rela parameter and r_type too. However, that means the
mips relocate() needs to know whether SHT_REL or SHT_RELA relocs are
being processed. So add a rel_type for mips, which also has the
benefit of removing relocate() overloading there.
This patch adds the infrastructure without making use of it.
Note that relinfo->rr will be NULL if not outputting relocations.
* object.h (struct Relocate_info): Add "rr".
* reloc.h (Relocatable_relocs::set_strategy): New accessor.
* reloc.cc (Sized_relobj_file::do_relocate_sections): Init
relinfo.rr for relocate_section and relocate_relocs.
* powerpc.cc (relocate): Add rel_type and preloc parameters.
Delete rela and r_type params, instead recalculate these from
preloc.
(relocate_relocs): Delete Relocatable_relocs* param, instead
use relinfo->rr.
* aarch64.cc: Likewise.
* arm.cc: Likewise.
* i386.cc: Likewise.
* mips.cc: Likewise.
* s390.cc: Likewise.
* sparc.cc: Likewise.
* target.h: Likewise.
* tilegx.cc: Likewise.
* x86_64.cc: Likewise.
* testsuite/testfile.cc: Likewise.
* target-reloc.h (relocate_section): Adjust to suit.
(apply_relocation, relocate_relocs): Likewise.
GDB Administrator [Wed, 9 Dec 2015 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in
Nick Clifton [Tue, 8 Dec 2015 09:49:49 +0000 (09:49 +0000)]
Fix static analysis warning about undefined bheaviour.
PR binutils/19310
* dwarf.c (display_debug_frames): Recode range test to avoid
undefined behaviour.
Jan Beulich [Tue, 8 Dec 2015 09:14:49 +0000 (10:14 +0100)]
gas: consistently emit diagnostics for non-zero data emission to .bss/.struct
Jan Beulich [Tue, 8 Dec 2015 09:12:54 +0000 (10:12 +0100)]
gas: don't get confused by .asci{i,z} after .struct
While not allowed, this certainly shouldn't result in confusing the
programmer (by skipping lines in unexpected ways): Without returning,
demand_empty_rest_of_line() (at the end of the function) will demand
the _next_ line to be empty, and without the conditional we would
ignore the next line.
Jan Beulich [Tue, 8 Dec 2015 09:11:58 +0000 (10:11 +0100)]
ELF: don't re-order SHF_FILE symbols
.file directives may be used to identify the scope of local symbols,
the purpose of which gets subverted when re-ordering them. Only allow
the first of them to be moved to the first position.
Pierre-Marie de Rodat [Thu, 3 Sep 2015 15:34:58 +0000 (17:34 +0200)]
DOCO: Enhance the menu to select function overloads with signatures
gdb/ChangeLog:
* NEWS: Announce this enhancement and the corresponding new
option.
gdb/doc/ChangeLog:
* gdb.texinfo (Ada Mode Into): Move overloading support
description to its own node.
(Overloading support for Ada): New node.
DJ Delorie [Tue, 8 Dec 2015 06:29:25 +0000 (01:29 -0500)]
rl78: relaxation fixes
Various fixes to linker relaxation. In general, we need to support
relaxing every branch, even if we don't relax it in the assembler,
so we can optionally defer relaxation to the linker.
* elf32-rl78.c (rl78_offset_for_reloc): Add more relocs.
(rl78_elf_relax_section): Add bc/bz/bnc/bnz/bh/bnh. Fix reloc
choices.
* config/rl78-parse.y: Make all branches relaxable via
rl78_linkrelax_branch().
* config/tc-rl78.c (rl78_linkrelax_branch): Mark all relaxable
branches with relocs.
(options): Add OPTION_NORELAX.
(md_longopts): Add -mnorelax.
(md_parse_option): Support OPTION_NORELAX.
(op_type_T): Add bh, sk, call, and br.
(rl78_opcode_type): Likewise.
(rl78_relax_frag): Fix not-relaxing logic. Add sk.
(md_convert_frag): Fix relocation handling.
(tc_gen_reloc): Strip relax relocs when not linker relaxing.
(md_apply_fix): Defer overflow handling for anything that needs a
PLT, to the linker.
* config/tc-rl78.h (TC_FORCE_RELOCATION): Force all relocations to
the linker when linker relaxing.
* doc/c-rl78.texi (norelax): Add.
DJ Delorie [Tue, 8 Dec 2015 06:15:58 +0000 (01:15 -0500)]
rx: Fix p_vaddr reconstruction logic.
* elf32-rx.c (rx_elf_object_p): Ignore empty and nobits sections.
DJ Delorie [Tue, 8 Dec 2015 03:33:39 +0000 (22:33 -0500)]
rl78: Enable MULU for all ISAs.
Unlike other mul/div opcodes, MULU is available on all variants
of the RL78.
* rl78-decode.opc: Enable MULU for all ISAs.
* rl78-decode.c: Regenerate.
GDB Administrator [Tue, 8 Dec 2015 00:00:22 +0000 (00:00 +0000)]
Automatic date update in version.in
Jan Beulich [Mon, 7 Dec 2015 16:52:25 +0000 (17:52 +0100)]
ld: relax alignment requirements of compressed .debug_* section checks
This fixes a failure of the gabinormal linking test on some distros
(where e.g. crt1.o has a .debug_aranges section with larger alignment).
Yao Qi [Mon, 7 Dec 2015 15:56:31 +0000 (15:56 +0000)]
Support Z0 packet in AArch64 multi-arch debugging
In commit
6085d6f6, Z0 packet is disabled in aarch64 GDBserver if
the inferior is 32-bit or there may be multiple inferiors, because
Z0 packet isn't supported for arm then. Recently, Z0 packet
is supported in arm target, so we don't have such limitation in
aarch64 GDBserver, that is to say, aarch64 GDBserver can use Z0
packet in multi-arch/multi-inferior debugging when the inferior's
arch is arm.
Part of this patch is to revert
6085d6f6, and the rest of the patch
is to move some breakpoint related arm_* functions into
linux-aarch32-low.c in order to share them between arm and aarch64.
This patch is regression tested on aarch64-linux for debugging both
aarch64 programs and arm programs respectively.
gdb/gdbserver:
2015-12-07 Yao Qi <yao.qi@linaro.org>
* configure.srv: Append arm.o to srv_tgtobj for
aarch64*-*-linux* target.
* linux-aarch32-low.c (arm_abi_breakpoint): New macro. Moved
from linux-arm-low.c.
(arm_eabi_breakpoint, arm_breakpoint): Likewise.
(arm_breakpoint_len, thumb_breakpoint): Likewise.
(thumb_breakpoint_len, thumb2_breakpoint): Likewise.
(thumb2_breakpoint_len): Likewise.
(arm_is_thumb_mode, arm_breakpoint_at): Likewise.
(arm_breakpoint_kinds): Likewise.
(arm_breakpoint_kind_from_pc): Likewise.
(arm_sw_breakpoint_from_kind): Likewise.
(arm_breakpoint_kind_from_current_state): Likewise.
* linux-aarch32-low.h (arm_breakpoint_kind_from_pc): Declare.
(arm_sw_breakpoint_from_kind): Declare.
(arm_breakpoint_kind_from_current_state): Declare.
(arm_breakpoint_at): Declare.
* linux-aarch64-low.c (aarch64_sw_breakpoint_from_kind): Call
arm_sw_breakpoint_from_kind if process is 32-bit.
(aarch64_breakpoint_kind_from_pc): New function.
(aarch64_breakpoint_kind_from_current_state): New function.
(the_low_target): Initialize fields breakpoint_kind_from_pc
and breakpoint_kind_from_current_state.
* linux-arm-low.c (arm_breakpoint_kinds): Move to
linux-aarch32-low.c.
(arm_abi_breakpoint, arm_eabi_breakpoint): Likewise.
(arm_breakpoint, arm_breakpoint_len): Likewise.
(thumb_breakpoint, thumb_breakpoint_len): Likewise.
(thumb2_breakpoint, thumb2_breakpoint_len): Likewise.
(arm_is_thumb_mode): Likewise.
(arm_breakpoint_at): Likewise.
(arm_breakpoint_kind_from_pc): Likewise.
(arm_sw_breakpoint_from_kind): Likewise.
(arm_breakpoint_kind_from_current_state): Likewise.
Revert:
2015-08-04 Yao Qi <yao.qi@linaro.org>
* linux-aarch64-low.c (aarch64_supports_z_point_type): Return
0 for Z_PACKET_SW_BP if it may be used in multi-arch debugging.
* server.c (extended_protocol): Remove "static".
* server.h (extended_protocol): Declare it.
Nick Clifton [Mon, 7 Dec 2015 14:44:46 +0000 (14:44 +0000)]
oops - accidentally omittde from previous delta.
Nick Clifton [Mon, 7 Dec 2015 14:43:47 +0000 (14:43 +0000)]
Fix relaxation in RX linker when --no-keep-memory is specified.
* elf32-rx.c (elf32_rx_relax_delete_bytes): Add extra parameter -
the start of the relocs for the section. Delete code to load in
the relocs.
(elf32_rx_relax_section): Do not free the loaded relocs.
Pierre-Marie de Rodat [Thu, 3 Sep 2015 15:34:58 +0000 (17:34 +0200)]
Enhance the menu to select function overloads with signatures
So far, trying to evaluate an expression involving a function call for
which GDB could find multiple function candidates outputs a menu so that
the user can select the one to run. For instance, with the two
following functions:
type New_Integer is new Integer;
function F (I : Integer) return Boolean;
function F (I : New_Integer) return Boolean;
Then we get the following GDB session:
(gdb) print f(1)
Multiple matches for f
[0] cancel
[1] foo.f at foo.adb:23
[2] foo.f at foo.adb.28
>
While the source location information is sufficient in order to
determine which one to select, one has to look for them in source files,
which is not convenient.
This commit tunes this menu in order to also include the list of formal
and return types (if any) in each entry. The above then becomes:
(gdb) print f(1)
Multiple matches for f
[0] cancel
[1] foo.f (integer) return boolean at foo.adb:23
[2] foo.f (foo.new_integer) return boolean at foo.adb.28
>
Since this output is more verbose than previously, this change also
introduces an option (set/show ada print-signatures) to get the original
output.
gdb/ChangeLog:
* ada-lang.c (print_signatures): New.
(ada_print_symbol_signature): New.
(user_select_syms): Add signatures to the output of candidate
symbols using ada_print_symbol_signature.
(_initialize_ada_language): Add a "set/show ada
print-signatures" boolean option.
gdb/testsuite/ChangeLog:
* gdb.ada/fun_overload_menu.exp: New testcase.
* gdb.ada/fun_overload_menu/foo.adb: New testcase.
Tested on x86_64-linux, no regression.
Andreas Arnez [Mon, 7 Dec 2015 09:43:39 +0000 (10:43 +0100)]
Add myself as a write-after-approval GDB maintainer
gdb/ChangeLog:
* MAINTAINERS (Write After Approval): Add Andreas Arnez.
Nick Clifton [Mon, 7 Dec 2015 10:19:19 +0000 (10:19 +0000)]
Add support for MSP430 F5 hardware multiply.
* msp430-sim.c (sim_open): Check for needed memory at address
0x500 not 0x200.
(get_op): Add support for F5 hardware multiply addresses.
(put_op): Likewise.
Alan Modra [Mon, 7 Dec 2015 03:22:01 +0000 (13:52 +1030)]
PowerPC ifunc with local symbols
This fixes some cases where the linker would incorrectly error on plt
relocs to local ifunc symbols. I've also tidied plt and ifunc
handling for ppc64, where check_relocs was allowing for the
possibility of plt calls via addr14/addr24 relocs but relocate_section
was not.
* elf32-ppc.c (ppc_elf_check_relocs): Don't error on local ifunc
plt call. Wrap long lines.
(ppc_elf_relocate_section): Wrap long lines.
* elf64-ppc.c (ppc64_elf_check_relocs): Don't error on local ifunc
plt calls. Move __tls_get_addr checks later. Don't create plt
for addr14/addr24 relocs.
(ppc64_elf_gc_sweep_hook): Adjust to suit check_relocs changes.
(ppc64_elf_relocate_section): Correct local ifunc handling for
PLT64, PLT32 and PLT16 relocs.
Alan Modra [Mon, 7 Dec 2015 03:11:36 +0000 (13:41 +1030)]
PR19323 memory allocation greater than 4G
On 32-bit targets, memory requested for program/section headers on a
fuzzed binary can wrap to 0. A bfd_alloc of zero bytes actually
returns a one byte allocation rather than a NULL pointer. This then
leads to buffer overflows.
Making this check unconditional triggers an extremely annoying gcc-5
warning.
PR19323
* elfcode.h (elf_object_p): Check for ridiculous e_shnum and
e_phnum values.
Alan Modra [Mon, 7 Dec 2015 02:45:24 +0000 (13:15 +1030)]
[GOLD] R_PPC64_ENTRY support
elfcpp/
* powerpc.h (R_PPC64_ENTRY): Define.
gold/
* powerpc.cc (add_2_2_12, ld_2_12, lis_2): Define.
(Target_powerpc::Scan::local, global): Handle R_PPC64_ENTRY.
(Target_powerpc::Relocate::relocate): Edit code at R_PPC64_ENTRY.
Alan Modra [Mon, 7 Dec 2015 02:44:53 +0000 (13:14 +1030)]
R_PPC64_ENTRY
Add a new relocation that marks large-model entry code, for edit back
to medium-model.
include/elf/
* ppc64.h (R_PPC64_ENTRY): Define.
bfd/
* reloc.c (BFD_RELOC_PPC64_ENTRY): New.
* elf64-ppc.c (reloc_howto_type ppc64_elf_howto_raw): Add
entry for R_PPC64_ENTRY.
(LD_R2_0R12, ADD_R2_R2_R12, LIS_R2, ADDIS_R2_R12): Define.
(ppc64_elf_reloc_type_lookup): Handle R_PPC64_ENTRY.
(ppc64_elf_relocate_section): Edit code at R_PPC64_ENTTY. Use
new insn defines.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
Alan Modra [Mon, 7 Dec 2015 02:44:35 +0000 (13:14 +1030)]
tc-ppc.c md_apply_fix tidy
* config/tc-ppc.c (md_apply_fix): Localize variables. Reduce casts.
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