Qiang Yu [Fri, 14 Apr 2023 07:58:31 +0000 (15:58 +0800)]
ac/llvm,radeonsi: lower some pack/unpack ops not supported by aco
aco only support the split vertion of these instructions.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Tue, 9 May 2023 09:48:24 +0000 (17:48 +0800)]
ac/llvm,radeonsi: lower ineg in nir
aco does not implement it.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Sat, 15 Apr 2023 08:10:57 +0000 (16:10 +0800)]
ac/llvm,radeonsi: lower txf offset in nir
aco will complain if txf has offset. Not if other
texture ops.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Fri, 14 Apr 2023 13:05:05 +0000 (21:05 +0800)]
ac/llvm,radeonsi: lower fsin/fcos in nir
ACO only support nir_fsin/cos_amd.
There's some pixel changes for gl-radeonsi-stoney trace.
Different pixels:
furmark 61 (no tolerance), 0 (1% tol.)
gimark 93867 (no tolerance), 888 (1% tol.)
tessmark 39 (no tolerance), 0 (1% tol.)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Sat, 15 Apr 2023 06:35:27 +0000 (14:35 +0800)]
ac/llvm,radeonsi: lower idiv in nir
aco does not implement these idiv ops.
nir_lower_idiv is for idiv ops <= 32bit and ported from
llvm amdgpu, so llvm do the same.
nir_lower_divmod64 is for 64bit idiv ops.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Tue, 9 May 2023 09:01:19 +0000 (17:01 +0800)]
tgsi_to_nir: call nir_lower_int64 when required
Use case: radeonsi will generate internal tgsi shader
with 64bit udiv instruction, and we want all 64bit udiv
to be lowered in nir by lower_int64_options.
For GLSL shaders, this is done in glsl to nir, so we do
the same for tgsi here.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Thu, 13 Apr 2023 06:19:19 +0000 (14:19 +0800)]
radeonsi: remove ps vgpr index save when args init
They will be set by ac_get_fs_input_vgpr_cnt() later anyway.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Fri, 14 Apr 2023 08:54:03 +0000 (16:54 +0800)]
radeonsi: support print raw shader binary
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Thu, 13 Apr 2023 00:54:44 +0000 (08:54 +0800)]
radeonsi: support raw shader binary upload
Only monolithic shader.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Sun, 23 Apr 2023 09:23:23 +0000 (17:23 +0800)]
ac/binary: pack prefech align code to a function
To be used by radeonsi raw shader binary.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Wed, 12 Apr 2023 13:44:13 +0000 (21:44 +0800)]
radeonsi: add a raw shader binary type
It's the output of ACO compiler. To share the si_shader_binary
struct with ELF type:
* add a type field to indicate RAW or ELF
* rename elf_buffer/size to code_buffer/size
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Wed, 12 Apr 2023 10:38:18 +0000 (18:38 +0800)]
radeonsi: init spi ps input shader config when aco
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Wed, 12 Apr 2023 10:24:12 +0000 (18:24 +0800)]
radeonsi: pack spi ps input fixup to a function
To be shared with ACO spi ps input construction.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Wed, 12 Apr 2023 07:37:06 +0000 (15:37 +0800)]
radeonsi: add shader info uses_sampleid
Used by ACO to set spi_ps_intput.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Wed, 12 Apr 2023 06:53:47 +0000 (14:53 +0800)]
radeonsi: add shader info for frag coord and sample pos read
To construct spi_ps_input when ACO compilation.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Wed, 12 Apr 2023 02:05:18 +0000 (10:05 +0800)]
radeonsi: add use_aco field for struct si_shader
We are going to use aco for monolithic ps first.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Wed, 5 Apr 2023 11:50:43 +0000 (19:50 +0800)]
radeonsi: add aco debug option
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Wed, 5 Apr 2023 11:44:19 +0000 (19:44 +0800)]
meson: build radeonsi with aco
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
David Heidelberg [Tue, 2 May 2023 23:01:36 +0000 (01:01 +0200)]
ci/skqp: handle all warnings printed with clang >= 14
Useful for the https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21977
Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22808>
Konstantin Seurer [Thu, 11 May 2023 17:03:11 +0000 (19:03 +0200)]
radv: Stop running constant folding during ray query lowering
Now that committed is an intrinsic index, there is no need for constant
folding.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22963>
Konstantin Seurer [Thu, 11 May 2023 17:00:51 +0000 (19:00 +0200)]
nir: Make rq_load committed src an index
committed has to be a constant so there is no need to have a src and
depend on constant folding to remove the i2b.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22963>
David Heidelberg [Fri, 28 Apr 2023 10:23:22 +0000 (12:23 +0200)]
gtest: Update to 1.13.0
Fix msan issue found with recent GCC on Debian 12.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8915
Acked-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22814>
David Heidelberg [Fri, 28 Apr 2023 10:51:59 +0000 (12:51 +0200)]
util/tests: adjust for new gtest
GTest deprecated the GTEST_ARRAY_SIZE_ macro.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22814>
M Henning [Fri, 12 May 2023 19:39:28 +0000 (15:39 -0400)]
nv50: Fix return type of nv50_blit_is_array
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22997>
M Henning [Fri, 12 May 2023 17:16:49 +0000 (13:16 -0400)]
nvc0: Free blitter->vp
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22997>
M Henning [Fri, 12 May 2023 17:14:51 +0000 (13:14 -0400)]
nv50,nvc0: Free nir from blitter fp shader
Fixes:
d11145e837 ("nv50,nvc0: Use nir in nv50_blitter_make_fp")
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22997>
Jesse Natalie [Fri, 12 May 2023 16:14:06 +0000 (09:14 -0700)]
dxil: Use unified atomics
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22993>
Jesse Natalie [Thu, 11 May 2023 20:23:34 +0000 (13:23 -0700)]
microsoft/compiler: Back-propagate type requirement information
For ALU ops where input types are known, we can store that info on
the input sources. This can be used to produce the correct overloads
of load instructions that don't immediately need to be followed by
bitcasts, or similarly to produce a constant value which can be directly
consumed by the relevant instruction without needing a bitcast.
Similarly for values that will be stored in an output, we know type
information. And using that info, we can use more-correct information
for phis instead of forcing all phi sources to be bitcast to int just
to be bitcast back to float on the other side for an alu or an output
store.
One missing piece is SSBO stores, where we can support int or float.
If the input is coming from a phi, we don't influence the phi's type,
so it'll be int, even though the incoming sources might've been float.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22972>
Jesse Natalie [Thu, 11 May 2023 17:58:25 +0000 (10:58 -0700)]
microsoft/compiler: Duplicate some SSA values to simplify SSA typing
For each phi src, ensure that it's only used as a phi src.
This lets us give each phi their own unique types without worrying
about them stomping on each other. Also scalarize phis.
For each constant, ensure that it's only used once. The DXIL backend
will already dedupe these consts within the module, but this lets a
single load_const have multiple types depending on how it's used.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22972>
Jesse Natalie [Thu, 11 May 2023 16:58:01 +0000 (09:58 -0700)]
microsoft/compiler: Remove alu type info from store_dest()
We pass in a *typed* value, we don't need to pass in additional
type info. That's just more opportunities to get it wrong.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22972>
Marek Olšák [Thu, 27 Apr 2023 07:49:10 +0000 (03:49 -0400)]
ac/llvm: rewrite and unify how GLC, DLC, SLC are set
Use ACCESS_* flags in call sites instead of GLC/DLC/SLC.
ACCESS_* flags are extended to describe other aspects of memory instructions
like load/store/atomic/smem.
Then add a function that converts the access flags to GLC, DLC, SLC.
The new functions are also usable by ACO.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22770>
Marek Olšák [Fri, 28 Apr 2023 04:11:32 +0000 (00:11 -0400)]
ac/llvm: don't treat ACCESS_NON_READABLE as ACCESS_COHERENT
... and expect it to behave like ACCESS_NON_TEMPORAL.
Handling ACCESS_NON_TEMPORAL is sufficient.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22770>
Marek Olšák [Fri, 28 Apr 2023 04:11:32 +0000 (00:11 -0400)]
aco: don't treat ACCESS_NON_READABLE as ACCESS_COHERENT
... and expect it to behave like ACCESS_NON_TEMPORAL.
Handling ACCESS_NON_TEMPORAL is sufficient.
This was copied from ac_nir_to_llvm.c.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22770>
Felix DeGrood [Tue, 9 May 2023 00:11:46 +0000 (00:11 +0000)]
intel: Secondary CB print primary CB's renderpass
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
Felix DeGrood [Wed, 26 Apr 2023 20:13:58 +0000 (20:13 +0000)]
intel: batch consecutive dispatches into implicit renderpasses
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
Felix DeGrood [Wed, 26 Apr 2023 18:52:21 +0000 (18:52 +0000)]
intel: refactor INTEL_MEASURE pointer dumping
Refactor framebuffer to renderpass to mirror previous INTEL_MEASURE
changes.
We dump hashes/pointers for shaders and framebuffer/renderpass.
Reduce from 64bit to 32bit pointers. We don't benefit from the
extra precision and reduced output size is convenient.
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
Felix DeGrood [Wed, 26 Apr 2023 18:26:06 +0000 (18:26 +0000)]
anv: re-enable RT data in INTEL_MEASURE
Per-RenderTarget analysis was removed from anv's INTEL_MEASURE
previously, probably after switching to dynamic rendering model.
Restore capability by tracking count of beginRenderPass calls.
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
Felix DeGrood [Wed, 26 Apr 2023 17:10:24 +0000 (17:10 +0000)]
anv: fix INTEL_MEASURE on MTL
Ensure counter buffer is coherent. Required for MTL which changes
coherence policy.
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
Alyssa Rosenzweig [Fri, 12 May 2023 14:56:07 +0000 (10:56 -0400)]
nir/validate: Handle unified atomics
nir_validate checks that the format of an atomic (if specified) is compatible
with the atomic operation. For example, we can't fadd R64_UINT texels. The logic
can't be extended as-is to unified atomics because it's split across different
switch cases for different atomic-op intrinsics. So we add our own validation
case, porting over the logic from the separate existing cases below.
(The redundant logic will be deleted once we delete legacy atomics.)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Fri, 12 May 2023 14:55:28 +0000 (10:55 -0400)]
nir/opt_uniform_atomics: Handle unified atomics
This is the one place where using nir_atomic_op instead of nir_op directly is a
little annoying, since we need to translate between the two enums, but it's not
a big deal.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Fri, 12 May 2023 14:54:05 +0000 (10:54 -0400)]
nir/lower_ssbo: Handle unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Fri, 12 May 2023 14:53:41 +0000 (10:53 -0400)]
nir/lower_io: Handle unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Fri, 12 May 2023 17:16:18 +0000 (13:16 -0400)]
nir/lower_task_shader: Handle unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Jesse Natalie [Fri, 12 May 2023 16:13:37 +0000 (09:13 -0700)]
nir: Load/store atomic op indices when lowering image intrinsics
They might not be stored in the same const index after lowering
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Fri, 12 May 2023 14:52:57 +0000 (10:52 -0400)]
nir: Handle unified atomics in simple cases
Lots of passes can be made unified-atomics-aware simply by adding extra cases in
their switch statements. This commit fixes a bunch of passes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Thu, 11 May 2023 13:58:39 +0000 (09:58 -0400)]
ir3: Use unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Karol Herbst [Tue, 9 May 2023 16:15:37 +0000 (18:15 +0200)]
nv50/ir: Use unified atomics
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Tue, 9 May 2023 13:02:00 +0000 (09:02 -0400)]
zink: Use unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Wed, 10 May 2023 23:16:28 +0000 (19:16 -0400)]
aco,radv: Use unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Tue, 9 May 2023 00:40:22 +0000 (20:40 -0400)]
ac/llvm: Use unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Tue, 9 May 2023 00:42:20 +0000 (20:42 -0400)]
ac/llvm: Don't handle atomic derefs
Should not be seen, already would be stubbed out.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Suggested-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Tue, 9 May 2023 00:12:20 +0000 (20:12 -0400)]
ntt: Use unified atomics
Nice deduplication of the NIR->TGSI enum translation.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Mon, 8 May 2023 23:38:16 +0000 (19:38 -0400)]
gallivm: Use unified atomics
This is a huge win because gallivm duplicated the translations in a zillion
places.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Mon, 8 May 2023 22:14:14 +0000 (18:14 -0400)]
pan/mdg: Use unified atomics
This doesn't actually save anything, since Italo already introduced magic macros
for this, but it ticks off one more driver on the list to convert. It's also
more legible, so that's nice :-)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Mon, 8 May 2023 20:05:25 +0000 (16:05 -0400)]
pan/mdg: Fix icky formatting
clang-format butchered this initializer pretty badly.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Mon, 8 May 2023 20:04:37 +0000 (16:04 -0400)]
pan/bi: Use unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Mon, 8 May 2023 19:26:28 +0000 (15:26 -0400)]
agx: Use unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Mon, 8 May 2023 19:30:06 +0000 (15:30 -0400)]
nir: Add pass to lower atomics to unified
In the future, we'd like to have all drivers only ingest unified atomics, and
all frontends only produce unified atomics, and garbage collect the existing
non-unified atomics. To get to that future, it's a lot nicer to convert drivers
one-by-one. Add a pass to translate old-style atomics to new-style atomics so
drivers can opt-in to the new form one-by-one. Once all drivers are converted,
we can convert producers one-by-one. Finally, we can just drop the calls to the
pass and garbage collect this pass and the old atomics. That's probably a while
out, though, so this will be out bridge to get there.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Mon, 8 May 2023 19:29:31 +0000 (15:29 -0400)]
nir: Add unified atomics
Currently, we have an atomic intrinsic for each combination of memory type
(global, shared, image, etc) and atomic operation (add, sub, etc). So for m
types of memory supported by the driver and n atomic opcodes, the driver has to
handle O(mn) intrinsics. This makes a total mess in every single backend I've
looked at, without fail.
It would be a lot nicer to unify the intrinsics. There are two obvious ways:
1. Make the memory type a constant index, keep different intrinsics for
different operations. The problem with this is that different memory types
imply different intrinsic signatures (number of sources, etc). As an
example, it doesn't make sense to unify global_atomic_amd with
global_atomic_2x32, as an example. The first takes 3 scalar sources, the
second takes 1 vector and 1 scalar. Also, in any single backend, there are a
lot more operations than there are memory types.
2. Make the opcode a constant index, keep different intrinsics for different
operations. This works well, with one exception: compswap and fcompswap
take an extra argument that other atomics don't, so there's an extra axis of
variation for the intrinsic signatures.
So, the solution is to have 2 intrinsics for each memory type -- for atomics
taking 1 argument and atomics taking 2 respectively. Both of these intrinsics
take an nir_atomic_op enum to describe its operation. We don't use a nir_op for
this purpose, as there are some atomics (cmpxchg, inc_wrap, etc) that don't
cleanly map to any ALU op and it would be weird to force it.
The plan is to transition to these new opcodes gradually. This series adds a
lowering pass producing these opcodes from the existing opcodes, so that
backends can opt-in to the new forms one-by-one. Then we can convert backends
separately without any cross-tree flag day. Once everything is converted, we can
convert the producers and core NIR as a flag day, but we have far fewer
producers than backends so this should be fine. Finally we can drop the old
stuff.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Rhys Perry [Thu, 11 May 2023 16:08:39 +0000 (17:08 +0100)]
aco/gfx11: fix VMEM/DS->VALU WaW/RaW hazard
Previously, we could safely read/write unused lanes of VMEM/DS
destination VGPRs without waiting for the load to finish. That doesn't
seem to be the case on GFX11.
fossil-db (gfx1100):
Totals from 6698 (4.94% of 135636) affected shaders:
Instrs:
11184274 ->
11199420 (+0.14%); split: -0.00%, +0.14%
CodeSize:
57578344 ->
57638928 (+0.11%); split: -0.00%, +0.11%
Latency:
198348808 ->
198382472 (+0.02%); split: -0.00%, +0.02%
InvThroughput:
24376324 ->
24378439 (+0.01%); split: -0.00%, +0.01%
VClause: 192420 -> 192559 (+0.07%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8722
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8239
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22965>
Dmitry Rogozhkin [Fri, 12 May 2023 16:22:36 +0000 (09:22 -0700)]
meson/vaon12: fix driver file name for mingw build
This fixes vaon12 driver file name to be consistent with libva
expectation - vaon12_drv_video.dll - without lib prefix.
Signed-off-by: Dmitry Rogozhkin <dmitry.v.rogozhkin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22995>
Yiwei Zhang [Fri, 12 May 2023 07:47:54 +0000 (00:47 -0700)]
lvp: avoid accessing member of NULL ptr for global entries
Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22979>
Yiwei Zhang [Fri, 12 May 2023 07:46:35 +0000 (00:46 -0700)]
pipe-loader: avoid undefined memcpy behavior
If either dest or src is an invalid or null pointer, the behavior is
undefined, even if count is zero.
Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22979>
Mike Blumenkrantz [Fri, 12 May 2023 16:36:57 +0000 (12:36 -0400)]
zink: disable dynamic state exts if the previous ones aren't present
this would be weird if a driver did it
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22996>
Mike Blumenkrantz [Fri, 12 May 2023 16:34:20 +0000 (12:34 -0400)]
zink: disable have_EXT_vertex_input_dynamic_state without EDS2
this is disabled already in the draw paths but not the pipeline paths
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22996>
Jesse Natalie [Fri, 12 May 2023 16:18:46 +0000 (09:18 -0700)]
nir_lower_system_values: Add ASSERTED to assert-only variable
Fixes:
1e0e4657 ("spirv/nir: wire ray interection triangle position fetch")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22994>
Eric Engestrom [Wed, 10 May 2023 11:54:58 +0000 (12:54 +0100)]
ci: replace write + cat with tee
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22945>
Eric Engestrom [Tue, 9 May 2023 17:49:16 +0000 (18:49 +0100)]
ci: stop marking environment variable list as executable
We're only going to read it, not execute it.
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22945>
Eric Engestrom [Tue, 9 May 2023 17:44:21 +0000 (18:44 +0100)]
ci: drop GENERATE_ENV_SCRIPT
Added in
16b417b8d617df418ad1 ("ci, valve: Add the dEQP runners for
Valve CI") but never used.
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22945>
Alyssa Rosenzweig [Thu, 11 May 2023 17:53:59 +0000 (13:53 -0400)]
nir: Use nir_block_last_phi_instr more
We have a helper, don't open code it.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22967>
Alyssa Rosenzweig [Thu, 11 May 2023 17:49:42 +0000 (13:49 -0400)]
ac/llvm: Use nir_foreach_phi
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22967>
Alyssa Rosenzweig [Thu, 11 May 2023 17:49:02 +0000 (13:49 -0400)]
dxil: Use nir_foreach_phi_safe
This should be faster, since we're not iterating pointlessly over all the
non-phis after the phi.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22967>
Alyssa Rosenzweig [Thu, 11 May 2023 17:20:43 +0000 (13:20 -0400)]
nir: Use nir_foreach_phi(_safe)
The pattern shows up all the time open-coded. Use the macro instead.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22967>
Alyssa Rosenzweig [Thu, 11 May 2023 17:11:57 +0000 (13:11 -0400)]
nir: Add nir_foreach_phi(_safe) macro
Serious preprocessor voodoo here. There are two tricks here.
1. Iterating only phis. We know that phis come only at the beginning of a block,
so all over the tree, we open-code iteration like:
nir_foreach_instr(instr, block) {
if (instr->type != phi)
break;
/* do stuff */
}
We can express this equivalently as
nir_foreach_instr(instr, block)
if (instr->type != phi)
break;
else {
/* do stuff */
}
So, we can define a macro
#define nir_foreach_phi(instr, block)
if (instr->type != phi)
break;
else
and then
nir_foreach_phi(..)
statement;
and
nir_foreach_phi(..) {
...
}
will expand to the right thing.
2. Automatically getting the phi as a phi. We want the instruction to go to some
hidden variable, and then automatically insert nir_phi_instr *phi =
nir_instr_as_phi(instr_internal); We can't do that directly, since we need to
express the assignment implicitly in the control flow for the above trick to
work. But we can do it indirectly with a loop initializer.
for (nir_phi_instr *phi = nir_instr_as_phi(instr_internal); ...)
That loop needs to break after exactly one iteration. We know that phi
will always be non-null on its first iteration, since the original
instruction is non-null, so we can use phi==NULL as a sentinel and express a
one-iteration loop as for (phi = nonnull; phi != NULL; phi = NULL).
Putting these together gives the macros implemented used.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22967>
Georg Lehmann [Tue, 25 Apr 2023 18:56:18 +0000 (20:56 +0200)]
aco: don't apply dpp if the alu instr uses the operand twice
CP77 has a ton of fma(dpp(a), dpp(a), b).
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22698>
Georg Lehmann [Sun, 23 Apr 2023 12:55:17 +0000 (14:55 +0200)]
aco: use VOP3+DPP
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22698>
Georg Lehmann [Wed, 26 Apr 2023 15:44:25 +0000 (17:44 +0200)]
aco/ra: convert VOPC_DPP instructions without vcc to VOP3
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22698>
Georg Lehmann [Sun, 23 Apr 2023 09:26:39 +0000 (11:26 +0200)]
aco: add assembler tests for VOP3(P) with DPP
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22698>
Georg Lehmann [Sun, 23 Apr 2023 08:51:01 +0000 (10:51 +0200)]
aco/builder: support VOP3(P) with dpp
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22698>
Georg Lehmann [Sun, 23 Apr 2023 08:42:58 +0000 (10:42 +0200)]
aco/assembler: support VOP3P with DPP
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22698>
Georg Lehmann [Tue, 9 May 2023 18:24:52 +0000 (20:24 +0200)]
aco/optimizer: copy pass flags for newly created valu instructions
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22698>
Georg Lehmann [Wed, 3 May 2023 10:48:01 +0000 (12:48 +0200)]
aco/optimizer: don't use pass_flags for mad idx
fma can use DPP on GFX11+, so we want to keep the exec id in pass_flags
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22698>
Georg Lehmann [Wed, 3 May 2023 11:07:35 +0000 (13:07 +0200)]
aco/vn: compare all valu modifers
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes:
9b4ea9ff901 ("aco/vn: hash opsel for VOP12C")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22698>
Mike Blumenkrantz [Fri, 12 May 2023 13:10:04 +0000 (09:10 -0400)]
zink: add back some anv qbo flakes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22987>
Alyssa Rosenzweig [Tue, 9 May 2023 21:15:47 +0000 (17:15 -0400)]
docs: Include ALU opcode descriptions
If we have a description for an ALU opcode in NIR, include it with our generated
HTML documentation so people don't need to go to nir_opcodes.py anyway because
the documentation is missing the documentation ;-)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Tested-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22929>
Alyssa Rosenzweig [Tue, 9 May 2023 21:10:24 +0000 (17:10 -0400)]
nir: Make ALU descriptions machine-readable
We already document a lot of ALU opcodes, let's make this machine-readable so we
can put the descriptions in our generated HTML documentation.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22929>
Alyssa Rosenzweig [Tue, 9 May 2023 21:10:05 +0000 (17:10 -0400)]
nir: Allow adding descriptions to ALU opcodes
This will let us generate nicer documentation.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22929>
Juan A. Suarez Romero [Fri, 12 May 2023 09:10:07 +0000 (11:10 +0200)]
vc4/ci: re-enable VC4 testing
But keeps piglit's quick_gl disabled, as it contains the test causing
the GPU resets.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22982>
Bas Nieuwenhuizen [Thu, 11 May 2023 23:08:27 +0000 (01:08 +0200)]
amd/drm-shim: Update docs for more devices.
We don't have to update the docs for every new entry.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22975>
Bas Nieuwenhuizen [Thu, 11 May 2023 20:49:18 +0000 (22:49 +0200)]
amd/drm-shim: Add raphael&mendocino, polaris12 and gfx1100.
Decided to follow the chip names pretty much.This set happens to be
what is in my workstation currently.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22975>
Bas Nieuwenhuizen [Thu, 11 May 2023 20:34:28 +0000 (22:34 +0200)]
amd/drm-shim: Add vangogh entry.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22975>
Tapani Pälli [Wed, 3 May 2023 04:13:07 +0000 (07:13 +0300)]
anv: handle missing astc for gfx125 in CreateImageView
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22818>
Samuel Pitoiset [Wed, 10 May 2023 09:34:19 +0000 (11:34 +0200)]
radv: configure PA_CL_VRS_CNTL entirely from the cmd buffer
We already have all the information needed to configure it.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22942>
Samuel Pitoiset [Wed, 10 May 2023 09:12:06 +0000 (11:12 +0200)]
radv: re-emit fragment shading rate state when PA_CL_VRS_CNTL changes
Found by inspection.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22942>
Samuel Pitoiset [Wed, 10 May 2023 10:44:48 +0000 (12:44 +0200)]
radv: dirty the dynamic vertex input state only when needed
This shouldn't be necessary when the VS doesn't have a prolog.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22944>
Samuel Pitoiset [Wed, 10 May 2023 10:41:21 +0000 (12:41 +0200)]
radv: reset the emitted VS prolog when a new vertex shader is bound
When a new vertex shader is bound, the VS prolog needs to be
re-emitted, and this allows us to avoid tracking if the pipeline is
dirty.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22944>
Iván Briano [Fri, 12 May 2023 02:48:39 +0000 (19:48 -0700)]
hasvk: avoid assert due to unsupported format
Fixes:
0a4c92b646f ("hasvk: Use the common vk_ycbcr_conversion object")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9011
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22978>
Nanley Chery [Fri, 14 Apr 2023 20:10:54 +0000 (13:10 -0700)]
anv: Enable MCS init with ISL_AUX_OP_AMBIGUATE
Up until now, we have been initializing MCS with fast clears. This is
mostly safe, but there's a corner case that can be an issue.
The issue is with a workaround for MCS that requires the sampler not see
any fast-cleared blocks for certain surfaces (
14013111325). Even though
we have been initializing MCS with fast clears, we expect most
applications to be safe because we expect that they would only sample
the samples they've rendered to previously (and the render would've
removed the fast-cleared blocks). In other words we don't expect that
apps would transition from VK_IMAGE_LAYOUT_UNDEFINED to
VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL and start sampling immediately.
If an application took the unexpected path of sampling undefined
samples, it's possible they'd hit the issue described in the workaround.
Fix this corner case by using an ambiguate to initialize MCS.
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22545>
Nanley Chery [Mon, 1 May 2023 18:54:20 +0000 (11:54 -0700)]
anv: Drop the MCS initialization performance warning
The comment above the warning explains that not all bit patterns are
necessarily valid. While we're at it, fix a typo in that comment.
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22545>
Nanley Chery [Fri, 14 Apr 2023 00:46:13 +0000 (17:46 -0700)]
iris: Enable MCS init with ISL_AUX_OP_AMBIGUATE
Add support for using BLORP's ambiguate pass to initialize MCS instead
of mapping and memsetting it on the CPU. Note that this won't be used if
the first operation on the MSAA layer is a fast clear.
Since we're no longer mapping, this removes a blocker towards getting
MCS_CCS enabled in small-BAR mode.
This functionality is difficult to test because of the way iris is set
up. It always tries to compress writes. So, a test would only read the
ambiguated MCS element if it tries to read from undefined samples.
To test this, I locally disabled fast clears and rendering with MCS (via
iris_resource_render_aux_usage). I continued to allow sampling with MCS
in iris_resource_texture_aux_usage. So, writes go directly to the main
surface and reads go through the ambiguated MCS surface.
When I then ran the test group, dEQP-GLES3.functional.multisample.*, all
48/64 supported tests passed on my Ice Lake. If I slightly changed
BLORP's ambiguate pass, I observed several tests failing.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22545>