Timothy Arceri [Fri, 4 Nov 2016 02:51:59 +0000 (13:51 +1100)]
mesa/glsl/i965: remove Driver.NewShader()
After removing brw_shader in the previous commit this is no longer
needed.
V2: remove use in src/compiler/glsl/test_optpass.cpp
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Fri, 4 Nov 2016 02:37:21 +0000 (13:37 +1100)]
i965: move compiled_once flag to brw_program
This allows us to delete brw_shader and removes the last use of
gl_linked_shader in the codegen paths.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Thu, 3 Nov 2016 23:10:19 +0000 (10:10 +1100)]
mesa/glsl: move BlendSupport bitfield to gl_program
This will let us to make _CurrentFragmentProgram a gl_program pointer
allowing for simpilifications to be made.
We also need to add a field to gl_shader to hold it during parsing.
In gl_program we put it inside a union in anticipation of moving
more fields here that can be only fs or vertex stage fields.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Thu, 3 Nov 2016 03:35:08 +0000 (14:35 +1100)]
mesa: store gl_program in gl_transform_feedback_object rather than gl_shader_program
This will allow us to make the CurrentProgram array store gl_program which allows
us to do a bunch of simplifications.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Thu, 3 Nov 2016 05:00:37 +0000 (16:00 +1100)]
mesa/glsl: move LinkedTransformFeedback from gl_shader_program to gl_program
This will help allow us to store gl_program in the CurrentProgram array rather
than gl_shader_program which will allow a bunch of simplifications.
Note that we make LinkedTransformFeedback a pointer so we don't waste
memory creating a struct for each stage. We also store a pointer to
the gl_program that will contain the pointer in gl_shader_program so
we can get easy access to the correct stage.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Tue, 8 Nov 2016 09:59:25 +0000 (20:59 +1100)]
i965: get LinkedTransformFeedback from gl_transform_feedback_object
We have already set the gl_shader_program pointer to the correct
shader program in _mesa_BeginTransformFeedback() so use it.
This is more consistent with how we do it for gen7.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Mon, 31 Oct 2016 11:08:24 +0000 (22:08 +1100)]
mesa: move _Used to gl_program
We no longer need to initialise it because gl_program is never reused.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Mon, 31 Oct 2016 11:06:37 +0000 (22:06 +1100)]
mesa/compiler: add local_size_variable to shader_info
This will be used in api_validate.c in a following patch when we
switch to using gl_program pointers for the pipelines CurrentProgram
array.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Mon, 31 Oct 2016 10:51:40 +0000 (21:51 +1100)]
mesa: pass gl_program to _mesa_append_uniforms_to_file()
This now contains everything we need.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Mon, 31 Oct 2016 08:35:49 +0000 (19:35 +1100)]
glsl/mesa: set separate_shader directly in shader_info
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Wed, 28 Dec 2016 21:56:43 +0000 (08:56 +1100)]
mesa/glsl: move subroutine metadata to gl_program
This will allow us to store gl_program rather than gl_shader_program
as the current program perstage which allows us to simplify code
that makes use of the CurrentProgram list.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Mon, 31 Oct 2016 08:57:57 +0000 (19:57 +1100)]
mesa/compiler: add stage to shader_info
This will allow us to simplify the current program logic for SSO.
Also since we aim to detach shader_info from nir_shader this will come
in handy avoiding passing nir_shader around just to keep track of
the stage we are dealing with.
V2: set stage for arb asm programs also.
Reviewed-by: Eric Anholt <eric@anholt.net>
Eric Anholt [Tue, 27 Dec 2016 21:52:54 +0000 (13:52 -0800)]
vc4: Rework scheduling of thread switch to cut one more NOP.
Jonas's patch got us most of the benefit of scheduling instructions into
the delay slots of thread switch, but if there had been nothing to pair
the thrsw with, it would move the thrsw up and leave a NOP where the thrsw
was.
Instead, don't pair anything with thrsw through the normal scheduling
path, and have a separate helper function that inserts the thrsw earlier
if possible and inserts any necessary NOPs.
total instructions in shared programs: 93027 -> 92643 (-0.41%)
instructions in affected programs: 14952 -> 14568 (-2.57%)
Jonas Pfeil [Sun, 20 Nov 2016 19:45:13 +0000 (20:45 +0100)]
vc4: Fill thread switching delay slots
Scan for instructions without a signal set in front of the switching
instruction and move the signal up there.
shader-db results:
total instructions in shared programs: 94494 -> 93027 (-1.55%)
instructions in affected programs: 23545 -> 22078 (-6.23%)
v2: Fix re-emitting of the instruction in the loop trying to emit NOPs,
drop a scheduling change from branch delay slots. (by anholt)
Signed-off-by: Jonas Pfeil <pfeiljonas@gmx.de>
Eric Anholt [Tue, 27 Dec 2016 20:29:09 +0000 (12:29 -0800)]
vc4: Enable NIR-based loop unrolling.
This successfully unrolls a new shader in GLB2.7, which also gets that
shader to successfully compile in multithreaded mode.
Timothy Arceri [Thu, 29 Dec 2016 02:18:59 +0000 (13:18 +1100)]
nir: stop gcc warning about uninitialised variables
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Dave Airlie [Tue, 27 Dec 2016 23:28:05 +0000 (23:28 +0000)]
radv: denote support for extended storage image formats.
I'm sure anv has support for these as well, but this is just
a first use of the interface to allow different supported spir-v
features.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 27 Dec 2016 23:27:14 +0000 (23:27 +0000)]
spirv: add interface for drivers to define support extensions.
I expect over time the struct contents will change as all
drivers support stuff etc, but for now this should be a good
starting point.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Chad Versace [Tue, 27 Dec 2016 22:26:24 +0000 (14:26 -0800)]
mesa/shaderobj: Fix races on refcounts
Use atomic ops when updating gl_shader::RefCount.
Fixes intermittent failures and crashes in
'dEQP-EGL.functional.sharing.gles2.multithread.*'.
All tests in that group now pass except
'dEQP-EGL.functional.sharing.gles2.multithread.simple_egl_server_sync.textures.copyteximage2d_texsubimage2d_render'.
Tested with:
mesa: branch 'master' at d6545f2
deqp: branch 'nougat-cts-dev' at 4acf725 with additional local fixes
DEQP_TARGET: x11_egl
hw: Intel Broadwell 0x1616
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99085
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Cc: Mark Janes <mark.a.janes@intel.com>
Cc: Haixia Shi <hshi@chromium.org>
Rob Clark [Mon, 26 Dec 2016 19:16:57 +0000 (14:16 -0500)]
freedreno/ir3: fix linkage::var size
It should actually be 32 for a4xx/a5xx.. we still only advertise 16 but
for a5xx the linkage map includes position/psize.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sun, 25 Dec 2016 18:16:51 +0000 (13:16 -0500)]
freedreno/ir3: treat clipvertex like a normal varying
We need this in case it is streamed out. Not sure why we were treating
it specially before. Having it as a VS out is harmless if FS doesn't
have a matching input.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sat, 24 Dec 2016 19:44:26 +0000 (14:44 -0500)]
freedreno/a5xx: transform-feedback support
We'll need to revisit when adding hw binning pass support, whether we
can still do this in main draw step, as we do w/ a3xx/a4xx, or if we
needed to move it to the binning stage.
Still some failing piglits but most tests pass and the common cases seem
to work.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sat, 24 Dec 2016 16:57:35 +0000 (11:57 -0500)]
freedreno: update generated headers
Pull in a5xx streamout related regs. Also fixes a couple incorrect
register definitions.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sat, 24 Dec 2016 00:19:01 +0000 (19:19 -0500)]
freedreno/ir3: UBO support for 64b GPUs (a5xx)
Update address calculation to support 64b addresses.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 22 Dec 2016 03:43:52 +0000 (22:43 -0500)]
freedreno/ir3: rework location of driver constants
Rework how we lay out driver constants (driver-params, UBO/TFBO buffer
addresses, immediates) for more flexibility. For a5xx+ we need to deal
with the fact that gpu ptrs are 64b instead of 32b, which makes the
fixed offset scheme not work so well. While we are dealing with that
we might also make the layout more dynamic to account for varying # of
UBOs, etc.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 22 Dec 2016 03:47:42 +0000 (22:47 -0500)]
freedreno/a5xx: fix emit for bo addresses
Reloc for the buffer address is two dwords on 64b devices (a5xx+)
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 6 Dec 2016 18:32:31 +0000 (13:32 -0500)]
freedreno/a5xx: texture layout
Seems to be imilar to a4xx, and sampler state "array-pitch" needs
to be aligned to page size.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 22 Dec 2016 05:56:48 +0000 (00:56 -0500)]
ttn: set ->info->num_ubos
For dealing w/ 32b vs 64b gpu addresses, I need to rework how we pass
UBO buffer addresses to shader, and knowing up front the # of UBOs is
useful. But I noticed ttn wasn't setting this.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Chad Versace [Tue, 27 Dec 2016 18:25:58 +0000 (10:25 -0800)]
anv: Handle vkGetPhysicalDeviceQueueFamilyProperties with count == 0
The spec implicitly allows the incoming count to be 0. From the Vulkan
1.0.38 spec, Section 4.1 Physical Devices:
If the value referenced by pQueueFamilyPropertyCount is not 0 [then
do stuff].
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Chad Versace [Fri, 23 Dec 2016 01:06:14 +0000 (17:06 -0800)]
egl: Emit correct error when robust context creation fails
Fixes dEQP-EGL.functional.create_context_ext.robust_*
on Intel with GBM.
If the user sets the EGL_CONTEXT_OPENGL_ROBUST_ACCESS_BIT_KHR in
EGL_CONTEXT_FLAGS_KHR when creating an OpenGL ES context, then
EGL_KHR_create_context spec requires that we unconditionally emit
EGL_BAD_ATTRIBUTE because that flag does not exist for OpenGL ES. When
creating an OpenGL context, the spec requires that we emit EGL_BAD_MATCH
if we can't support the request; that error is generated in the egl_dri2
layer where the driver capability is actually checked.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99188
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Damien Grassart [Sun, 25 Dec 2016 00:00:58 +0000 (01:00 +0100)]
anv: return count of queue families written
The Vulkan spec indicates that
vkGetPhysicalDeviceQueueFamilyProperties() should overwrite
pQueueFamilyPropertyCount with the number of structures actually
written to pQueueFamilyProperties.
Signed-off-by: Damien Grassart <damien@grassart.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Cc: mesa-stable@lists.freedesktop.org
Chad Versace [Thu, 22 Dec 2016 23:00:12 +0000 (15:00 -0800)]
i965: Allow import/export of ARGB1555 images
To my knowledge, this fixes no tests. I simply wrote the patch for
completeness as a follow-up to the previous two patches.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Chad Versace [Thu, 22 Dec 2016 22:39:44 +0000 (14:39 -0800)]
mesa/texformat: Handle GL_RGBA + GL_UNSIGNED_SHORT_5_5_5_1
_mesa_choose_tex_format() already handles GL_RGBA + GL_UNSIGNED_SHORT_1_5_5_5_REV
by converting it to MESA_FORMAT_B5G5R5A1_UNORM. Teach it do the same for
the non-reversed type. Otherwise, the switch's fallthrough converts it
to an 8888 format, which has incompatible precision in the alpha
channel.
Patch 2/2 to fix dEQP-EGL.functional.image.modify.tex_rgb5_a1_tex_subimage_rgba8
on Intel.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99185
Cc: Haixia Shi <hshi@chromium.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Chad Versace [Thu, 22 Dec 2016 22:44:47 +0000 (14:44 -0800)]
dri: Add __DRI_IMAGE_FORMAT_ARGB1555
This allows eglCreateImage() to accept textures of said format.
Patch 1/2 to fix
dEQP-EGL.functional.image.modify.tex_rgb5_a1_tex_subimage_rgba8
on Intel.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99185
Cc: Haixia Shi <hshi@chromium.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Tapani Pälli [Wed, 21 Dec 2016 08:21:34 +0000 (10:21 +0200)]
egl/dri2: implement query surface hook
This makes better guarantee that the values we return are
in sync what the underlying drawable currently has.
Together with dEQP change in bug #98327 this fixes following test:
dEQP-EGL.functional.resize.surface_size.grow
v2: avoid unnecessary x11 roundtrips (Chad Versace)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98327
Dave Airlie [Tue, 27 Dec 2016 03:26:11 +0000 (03:26 +0000)]
radv: add some asserts for operations on general queue
These might be useful in the future, or not.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Mon, 26 Dec 2016 23:57:36 +0000 (00:57 +0100)]
radv: Also skip DCC clear flushes for compute.
(airlied: fixes DOOM hang with compute queue enabled)
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Dave Airlie [Fri, 23 Dec 2016 06:24:21 +0000 (06:24 +0000)]
radv: handle queue present directly to winsys
Don't call the QueueSubmit interface, just call direct to the
winsys, so we can pass the wait semaphores.
Noticed while debugging doom, doesn't fix anything.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jordan Justen [Sat, 24 Dec 2016 02:41:15 +0000 (18:41 -0800)]
intel/blorp_blit: Fix max blit size for gen6
Fixes ES3-CTS.gtf.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_stencil_blit
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Dave Airlie [Fri, 23 Dec 2016 06:41:32 +0000 (06:41 +0000)]
radv: fix rendering to b10g11r11_ufloat_pack32
doom was causing a printf about an illegal color, it was due the
non-void returning -1, and the other function checking for 4,
align these.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 23 Dec 2016 05:41:18 +0000 (05:41 +0000)]
radv: handle multi-component shared load/stores.
This was seen in doom shaders, so handle it properly.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave AIrlie <airlied@redhat.com>
Vedran Miletić [Wed, 21 Dec 2016 12:49:36 +0000 (13:49 +0100)]
clover: Use Clang's diagnostics
Presently errors from frontend are handled only if they occur in
clang::CompilerInvocation::CreateFromArgs(). This patch uses
clang::DiagnosticsEngine to detect errors such as invalid values for
Clang frontend arguments.
Fixes Piglit's cl/program/build/fail/invalid-version-declaration.cl
test.
v2: fix inconsistent code formatting
Signed-off-by: Vedran Miletić <vedran@miletic.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Aaron Watry <awatry@gmail.com>
Damien Grassart [Sat, 24 Dec 2016 23:41:45 +0000 (00:41 +0100)]
radv: return count of queue families written
The Vulkan spec indicates that
vkGetPhysicalDeviceQueueFamilyProperties() should overwrite
pQueueFamilyPropertyCount with the number of structures actually
written to pQueueFamilyProperties.
Signed-off-by: Damien Grassart <damien@grassart.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Jason Ekstrand [Thu, 22 Dec 2016 23:26:12 +0000 (15:26 -0800)]
i965/generator/tex: Handle an immediate sampler with an indirect texture
In this case we were dying when we tried to do SHL addr sampler imm(8)
because that puts an immediate in src0 of a two source instruction. This
fixes 2704 of the new separate sampler Vulkan CTS tests on Sky Lake.
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Bruce Cherniak [Fri, 23 Dec 2016 00:06:41 +0000 (18:06 -0600)]
swr: fix icc compile error
ICC doesn't like the use of nullptr (std::nullptr_t) argument in
p_atomic_set. GCC and clang don't complain.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99119
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Dave Airlie [Thu, 22 Dec 2016 01:52:30 +0000 (11:52 +1000)]
radv: set some proper values for interp offset limits.
These are taken from the amdgpu-pro driver, and cause no
CTS change.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 22 Dec 2016 00:35:46 +0000 (10:35 +1000)]
radv: bump texel offsets to align with radeonsi
it appears from the amdgpu-pro results the hw can do more,
but let's just align with radeonsi for now.
No CTS regressions.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jason Ekstrand [Tue, 20 Dec 2016 05:29:51 +0000 (21:29 -0800)]
nir/algebraic: Add optimizations for "a == a && a CMP b"
This sequence shows up The Talos Principal, at least under Vulkan,
and prevents loop analysis from properly computing trip counts in a
few loops.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jason Ekstrand [Sat, 17 Dec 2016 07:30:40 +0000 (23:30 -0800)]
i965: Use nir_opt_trivial_continues and nir_opt_if
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Jason Ekstrand [Mon, 19 Dec 2016 21:11:43 +0000 (13:11 -0800)]
nir: Add a pass for moving SPIR-V continue blocks to the ends of loops
When shaders come in from SPIR-V, we handle continue blocks by placing
the contents of the continue inside of a "if (!first_iteration)". We do
this so that we can properly handle the fact that continues in SPIR-V
jump to the continue block at the end of the loop rather than jumping
directly to the top of the loop like they do in NIR. In particular, the
increment step of a simple for loop ends up in the continue block. This
pass looks for this case in loops that don't actually have any continues
and moves the continue contents to the end of the loop instead. We need
this because loop unrolling doesn't work if the increment is inside of a
condition.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Jason Ekstrand [Sat, 17 Dec 2016 00:54:17 +0000 (16:54 -0800)]
nir: Add an optimization pass to remove trivial continues
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Jason Ekstrand [Mon, 19 Dec 2016 18:46:04 +0000 (10:46 -0800)]
nir: Correctly handle blocks in cf_node_cf_tree_next
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Timothy Arceri [Fri, 9 Dec 2016 05:49:10 +0000 (16:49 +1100)]
i965: make use of nir_lower_returns() for GL
Fixes two new piglit tests:
spec/glsl-1.10/execution/vs-nested-return-sibling-loop.shader_test
spec/glsl-1.10/execution/vs-nested-return-sibling-loop2.shader_test
shader-db results for BDW:
total instructions in shared programs:
12903158 ->
12903134 (-0.00%)
instructions in affected programs: 27100 -> 27076 (-0.09%)
helped: 32
HURT: 6
total cycles in shared programs:
294922518 ->
294922804 (0.00%)
cycles in affected programs: 4372828 -> 4373114 (0.01%)
helped: 31
HURT: 8
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Fri, 9 Dec 2016 05:49:09 +0000 (16:49 +1100)]
nir: update nir_lower_returns to only predicate instructions when needed
Unless an if statement contains nested returns we can simply add
any following instructions to the branch without the return.
V2: fix handling if_nested_return value when there is a sibling if/loop
that doesn't contain a return. (Spotted by Ken)
V3:
- add a better comment to the new variable
- remove instructions after if when both branches return
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Tue, 13 Dec 2016 00:37:25 +0000 (11:37 +1100)]
i965: disable loop unrolling in GLSL IR
There is a single regression in loop unrolling which is:
loops HURT: shaders/orbital_explorer.shader_test GS SIMD8: 0 -> 1
However the loop is huge so it seems reasonable not to unroll it. It's
surprising that GLSL IR does unroll it.
shader-db results BDW:
total instructions in shared programs:
13037455 ->
13036947 (-0.00%)
instructions in affected programs: 17982 -> 17474 (-2.83%)
helped: 63
HURT: 25
total cycles in shared programs:
262217870 ->
262227990 (0.00%)
cycles in affected programs: 2287046 -> 2297166 (0.44%)
helped: 969
HURT: 844
total loops in shared programs: 2951 -> 2952 (0.03%)
loops in affected programs: 0 -> 1
helped: 0
HURT: 1
LOST: 0
GAINED: 1
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Tue, 13 Dec 2016 00:36:51 +0000 (11:36 +1100)]
i965: use nir loop unrolling pass
shader-db results for BDW:
total instructions in shared programs:
12589614 ->
12590119 (0.00%)
instructions in affected programs: 50525 -> 51030 (1.00%)
helped: 7
HURT: 145
total cycles in shared programs:
241524604 ->
241490502 (-0.01%)
cycles in affected programs: 1941404 -> 1907302 (-1.76%)
helped: 302
HURT: 449
total loops in shared programs: 4245 -> 2947 (-30.58%)
loops in affected programs: 1535 -> 237 (-84.56%)
helped: 1142
HURT: 0
total spills in shared programs: 14453 -> 14453 (0.00%)
spills in affected programs: 0 -> 0
helped: 0
HURT: 0
total fills in shared programs: 18984 -> 18984 (0.00%)
fills in affected programs: 0 -> 0
helped: 0
HURT: 0
LOST: 26
GAINED: 15
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Thu, 15 Sep 2016 02:20:38 +0000 (12:20 +1000)]
nir: pass compiler rather than devinfo to functions that call nir_optimize
Later we will pass compiler to nir_optimise to be used by the loop unroll
pass.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Thu, 15 Sep 2016 05:49:57 +0000 (15:49 +1000)]
nir: add a loop unrolling pass
V2:
- tidy ups suggested by Connor.
- tidy up cloning logic and handle copy propagation
based of suggestion by Connor.
- use nir_ssa_def_rewrite_uses to fix up lcssa phis
suggested by Connor.
- add support for complex loop unrolling (two terminators)
- handle case were the ssa defs use outside the loop is already a phi
- support unrolling loops with multiple terminators when trip count
is know for each terminator
V3:
- set correct num_components when creating phi in complex unroll
- rewrite update remap table based on Jasons suggestions.
- remove unrequired extract_loop_body() helper as suggested by Jason.
- simplify the lcssa phi fix up code for simple loops as per Jasons suggestions.
- use mem context to keep track of hash table memory as suggested by Jason.
- move is_{complex,simple}_loop helpers to the unroll code
- require nir_metadata_block_index
- partially rewrote complex unroll to be simpler and easier to follow.
V4:
- use rzalloc() when creating nir_phi_src but not setting pred right away
fixes regression cause by ralloc() no longer zeroing memory.
V5:
- simplify calling of complex_unroll()
- use new loop terminator fields to get the break/continue from blocks
and simplify loop unrolling code
- handle slightly less trivial loop terminators. if branches can
now have instructions but can only contain a single block.
- use nir print type IR snippets in unroll function descriptions
- add better explanation and variable for why we need to clone
additional times when the second terminator it the limiting
terminator.
- partially convert out of ssa before unrolling loops (suggested by Jason)
v6:
- remove unused nir_builder
- use Jasons new from ssa helper
- tidy/fixup cursor use
- unroll terminators that contain control flow correctly
- unroll complex loops with control flow before the terminators
correctly
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Thu, 25 Aug 2016 02:48:57 +0000 (12:48 +1000)]
nir: add helper for cloning nir_cf_list
V2:
- updated to create a generic list clone helper nir_cf_list_clone()
- continue to assert on clone when fallback flag not set as suggested
by Jason.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Wed, 14 Dec 2016 05:14:20 +0000 (16:14 +1100)]
nir: update fixup_phi_srcs() to handle registers
We need to do this because we partially get out of SSA when unrolling
and cloning loops.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Thu, 25 Aug 2016 03:00:57 +0000 (13:00 +1000)]
nir: create helper for fixing phi srcs when cloning
This will be useful for fixing phi srcs when cloning a loop body
during loop unrolling.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Thomas Helland [Mon, 29 Aug 2016 00:02:34 +0000 (10:02 +1000)]
nir: Add a LCSAA-pass
V2: Do a "depth first search" to convert to LCSSA
V3: Small comment fixup
V4: Rebase, adapt to removal of function overloads
V5: Rebase, adapt to relocation of nir to compiler/nir
Still need to adapt to potential if-uses
Work around nir_validate issue
V6 (Timothy):
- tidy lcssa and stop leaking memory
- dont rewrite the src for the lcssa phi node
- validate lcssa phi srcs to avoid postvalidate assert
- don't add new phi if one already exists
- more lcssa phi validation fixes
- Rather than marking ssa defs inside a loop just mark blocks inside
a loop. This is simpler and fixes lcssa for intrinsics which do
not have a destination.
- don't create LCSSA phis for loops we won't unroll
- require loop metadata for lcssa pass
- handle case were the ssa defs use outside the loop is already a phi
V7: (Timothy)
- pass indirect mask to metadata call
v8: (Timothy)
- make convert to lcssa a helper function rather than a nir pass
- replace inside loop bitset with on the fly block index logic.
- remove lcssa phi validation special cases
- inline code from useless helpers, suggested by Jason.
- always do lcssa on loops, suggested by Jason.
- stop making lcssa phis special. Add as many source as the block
has predecessors, suggested by Jason.
V9: (Timothy)
- fix regression with the is_lcssa_phi field not being initialised
to false now that ralloc() doesn't zero out memory.
V10: (Timothy)
- remove extra braces in SSA example, pointed out by Topi
V11: (Timothy)
- add missing support for LCSSA phis in if conditions.
V12: (Timothy)
- small tidy up suggested by Jason.
- always create lcssa phi even if it just points to an lcssa
phi from an inner loop
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Thomas Helland [Tue, 13 Dec 2016 03:39:51 +0000 (14:39 +1100)]
nir: Add a loop analysis pass
This pass detects induction variables and calculates the
trip count of loops to be used for loop unrolling.
V2: Rebase, adapt to removal of function overloads
V3: (Timothy Arceri)
- don't try to find trip count if loop terminator conditional is a phi
- fix trip count for do-while loops
- replace conditional type != alu assert with return
- disable unrolling of loops with continues
- multiple fixes to memory allocation, stop leaking and don't destroy
structs we want to use for unrolling.
- fix iteration count bugs when induction var not on RHS of condition
- add FIXME for && conditions
- calculate trip count for unsigned induction/limit vars
V4: (Timothy Arceri)
- count instructions in a loop
- set the limiting_terminator even if we can't find the trip count for
all terminators. This is needed for complex unrolling where we handle
2 terminators and the trip count is unknown for one of them.
- restruct structs so we don't keep information not required after
analysis and remove dead fields.
- force unrolling in some cases as per the rules in the GLSL IR pass
V5: (Timothy Arceri)
- fix metadata mask value 0x10 vs 0x16
V6: (Timothy Arceri)
- merge loop_variable and nir_loop_variable structs and lists suggested by Jason
- remove induction var hash table and store pointer to induction information in
the loop_variable suggested by Jason.
- use lowercase list_addtail() suggested by Jason.
- tidy up init_loop_block() as per Jasons suggestions.
- replace switch with nir_op_infos[alu->op].num_inputs == 2 in
is_var_basic_induction_var() as suggested by Jason.
- use nir_block_last_instr() in and rename foreach_cf_node_ex_loop() as suggested
by Jason.
- fix else check for is_trivial_loop_terminator() as per Connors suggetions.
- simplify offset for induction valiables incremented before the exit conditions is
checked.
- replace nir_op_isub check with assert() as it should have been lowered away.
V7: (Timothy Arceri)
- use rzalloc() on nir_loop struct creation. Worked previously because ralloc()
was broken and always zeroed the struct.
- fix cf_node_find_loop_jumps() to find jumps when loops contain
nested if statements. Code is tidier as a result.
V8: (Timothy Arceri)
- move is_trivial_loop_terminator() to nir.h so we can use it to assert is
the loop unroll pass
- fix analysis to not bail when looking for terminator when the break is in the else
rather then the if
- added new loop terminator fields: break_block, continue_from_block and
continue_from_then so we don't have to gather these when doing unrolling.
- get correct array length when forcing unrolling of variables
indexed arrays that are the same size as the iteration count
- add support for induction variables of type float
- update trival loop terminator check to allow an if containing
instructions as long as both branches contain only a single
block.
V9: (Timothy)
- bunch of tidy ups and simplifications suggested by Jason.
- rewrote trivial terminator detection, now the only restriction is there
must be no nested jumps, anything else goes.
- rewrote the iteration test to use nir_eval_const_opcode().
- count instruction properly even when forcing an unroll.
- bunch of other tidy ups and simplifications.
V10: (Timothy)
- some trivial tidy ups suggested by Jason.
- conditional fix for break inside continue branch by Jason.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Tue, 6 Dec 2016 01:12:20 +0000 (12:12 +1100)]
i965: use nir_lower_indirect_derefs() for GLSL
This moves the nir_lower_indirect_derefs() call into
brw_preprocess_nir() so thats is called by both OpenGL and Vulkan
and removes that call to the old GLSL IR pass
lower_variable_index_to_cond_assign()
We want to do this pass in nir to be able to move loop unrolling
to nir.
There is a increase of 1-3 instructions in a small number of shaders,
and 2 Kerbal Space program shaders that increase by 32 instructions.
The changes seem to be caused be the difference in the GLSL IR vs
NIR variable index lowering passes. The GLSL IR pass creates a
simple if ladder for arrays of size 4 or less, while the NIR pass
implements a binary search for all arrays regardless of size.
Shader-db results BDW:
total instructions in shared programs:
13021176 ->
13021819 (0.00%)
instructions in affected programs: 57693 -> 58336 (1.11%)
helped: 20
HURT: 190
total cycles in shared programs:
299805580 ->
299750826 (-0.02%)
cycles in affected programs: 2290024 -> 2235270 (-2.39%)
helped: 337
HURT: 442
total fills in shared programs: 19984 -> 19984 (0.00%)
fills in affected programs: 0 -> 0
helped: 0
HURT: 0
LOST: 4
GAINED: 0
V2: remove the do_copy_propagation() call from the i965 GLSL IR
linking code. This call was added in
f7741c52111 but since we are
moving the variable index lowering to NIR we no longer need it and
can just rely on the nir copy propagation pass.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Fri, 16 Sep 2016 12:36:30 +0000 (22:36 +1000)]
i965: allow sampler indirects on all gens
Without this we will regress the max-samplers piglit test on Gen6
and lower when loop unrolling is done in NIR. There is a check
in the GLSL IR linker that errors when it finds indirects and
EmitNoIndirectSampler is set.
As far as I can tell there is no reason for not enabling this for
all gens regardless of whether they fully support ARB_gpu_shader5
or not.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Tue, 20 Dec 2016 04:11:47 +0000 (20:11 -0800)]
nir: Add a couple quick-and-dirty out-of-SSA helpers
These are designed for use within an optimization pass when SSA becomes
more pain than it's worth. They're very naive and don't generate
anything close to optimal register-based NIR. Also, they may result in
shaders which do not validate because of, for instance, registers in phi
sources. However, the register-based into-SSA pass should be pretty
efficient at cleaning up the mess.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Arda Coskunses [Thu, 22 Dec 2016 22:03:11 +0000 (15:03 -0700)]
vulkan/wsi/x11: don't crash on null wsi x11 connection
Without this check driver crash when application window
closed unexpectedly.
Acked-by: Edward O'Callaghan <funfunctor@folklore194.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Arda Coskunses [Thu, 22 Dec 2016 21:55:03 +0000 (14:55 -0700)]
vulkan/wsi/x11: don't crash on null visual
When application window closed unexpectedly due to
lost window visualtypes getting invlaid parameters
which is causing a crash. Necessary check is added
to prevent the crash.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Christian Inci [Mon, 19 Dec 2016 22:26:35 +0000 (23:26 +0100)]
radeonsi: Bugfix needed for hashcat
Hashcat needs MAX_GLOBAL_BUFFERS to be 21 or even 22 for some modes. It'll crash otherwise.
I'm adding an assert to see if programs need it to be even higher.
Signed-off-by: Christian Inci <chris.bugsfd@broke-the-inter.net>
[Handle first properly; should be NFC, since clover always uses first == 0.]
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Thu, 15 Dec 2016 11:19:07 +0000 (12:19 +0100)]
radeonsi: fix gl_ClipDistance and gl_ClipVertex for points
The clipper hardware doesn't consider points as primitives that can be
clipped. Simply setting the corresponding cull bits works, and should not
have an adverse effect on other primitive types according to the hardware
team.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Nicolai Hähnle [Fri, 9 Dec 2016 22:21:28 +0000 (23:21 +0100)]
radeonsi: only set VS_OUT_MISC_SIDE_BUS_ENA when the misc vector is used
Should have no effect (other than perhaps on power consumption), but
Vulkan does this.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Vinson Lee [Sat, 3 Dec 2016 01:44:34 +0000 (17:44 -0800)]
llvmpipe: Link tests with CLOCK_LIB.
Fix linking error with 'make check'.
CXXLD lp_test_format
../../../../src/gallium/auxiliary/.libs/libgallium.a(os_time.o): In function `os_time_get_nano':
src/gallium/auxiliary/os/os_time.c:59: undefined reference to `clock_gettime'
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Fredrik Höglund [Wed, 7 Dec 2016 18:20:08 +0000 (19:20 +0100)]
radv: fix dual source blending
Add the index to the location when assigning driver locations for
output variables.
Otherwise two fragment shader outputs declared as:
layout (location = 0, index = 0) out vec4 output1;
layout (location = 0, index = 1) out vec4 output2;
will end up aliasing one another.
Note that this patch will make the second output variable in the above
example alias a possible third output variable with location = 1 and
index = 0. But this shouldn't be a problem in practice since only one
color attachment is supported when dual-source blending is used.
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Thu, 22 Dec 2016 00:20:32 +0000 (10:20 +1000)]
radv: enable shaderStorageImageExtendedFormats
This passes all the CTS tests that get enabled for this.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 21 Dec 2016 23:45:39 +0000 (09:45 +1000)]
radv: enable shaderGatherImageExtended
Thanks to Ilia's patch this works fine on radv.
No regressions in CTS, all enabled tests pass.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 21 Dec 2016 23:28:40 +0000 (23:28 +0000)]
radv/image: only touch queue family info for concurrent images.
The spec says to ignore these fields for exclusive images.
Fixes crashes in:
dEQP-VK.clipping.*
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 21 Dec 2016 22:09:46 +0000 (22:09 +0000)]
radv: flush smem for uniform buffer bit.
(cc'ing stable as I'd like to backport the ubo speedup as well)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Junwei Zhang [Thu, 4 Aug 2016 05:08:40 +0000 (13:08 +0800)]
radeonsi: add Polaris12 PCI ID
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Junwei Zhang [Mon, 19 Dec 2016 18:51:25 +0000 (13:51 -0500)]
radeonsi: add Polaris12 support (v3)
v2: use gfxip names for llvm 4.0+
v3: use tonga for llvm <= 3.8, drop gfxip name,
we can just change that we change the other asics.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Ian Romanick [Mon, 19 Dec 2016 23:06:41 +0000 (15:06 -0800)]
glsl: Eliminate the open-coded version of process_block_array_leaf
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Juan A. Suarez Romero [Thu, 24 Nov 2016 12:25:27 +0000 (13:25 +0100)]
ttn: handle GLSL_SAMPLER_DIM_SUBPASS_MS case
Fixes a warning.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Juan A. Suarez Romero [Thu, 3 Nov 2016 07:56:23 +0000 (08:56 +0100)]
i965: allow unsourced enabled VAO
The GL 4.5 spec says:
"If any enabled array’s buffer binding is zero when DrawArrays
or one of the other drawing commands defined in section 10.4 is
called, the result is undefined."
This commits avoids crashing the code, which is not a very good
"undefined result".
This fixes spec/!opengl 3.1/vao-broken-attrib piglit test.
Edward O'Callaghan [Tue, 6 Dec 2016 00:28:56 +0000 (11:28 +1100)]
svga: Fix a strict-aliasing violation in shader dumper
As per the C spec, it is illegal to alias pointers to different
types. This results in undefined behaviour after optimization
passes, resulting in very subtle bugs that happen only on a
full moon..
Use a memcpy() as a well defined coercion between the isomorphic
bit-field interpretations of memory.
V.2: Use C99 compat STATIC_ASSERT() over C11 static_assert().
Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Roland Scheidegger [Wed, 21 Dec 2016 03:43:07 +0000 (04:43 +0100)]
draw: use SoA fetch, not AoS one
Now that there's some SoA fetch which never falls back, we should always get
results which are better or at least not worse (something like rgba32f will
stay the same).
For cases which get way better, think something like R16_UNORM with 8-wide
vectors: this was 8 sign-extend fetches, 8 cvt, 8 muls, followed by
a couple of shuffles to stitch things together (if it is smart enough,
6 unpacks) and then a (8-wide) transpose (not sure if llvm could even
optimize the shuffles + transpose, since the 16bit values were actually
sign-extended to 128bit before being cast to a float vec, so that would be
another 8 unpacks). Now that is just 8 fetches (directly inserted into
vector, albeit there's one 128bit insert needed), 1 cvt, 1 mul.
v2: ditch the old AoS code instead of just disabling it.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Wed, 21 Dec 2016 03:30:02 +0000 (04:30 +0100)]
gallivm: generalize the compressed format soa fetch a bit
This can now handle rgtc (unorm) too - this path no longer handles plain
formats, but that's unnecessary they now all have their proper SoA unpack
(this will still be dog-slow though due to the actual fetch being per-pixel
util fallbacks).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Sun, 11 Dec 2016 22:41:07 +0000 (23:41 +0100)]
gallivm: provide soa fetch path handling formats with more than 32bit
This previously always fell back to AoS conversion. Even for 4-float formats
(which is the optimal case by far for that fallback case) this was suboptimal,
since it meant the conversion couldn't be done with 256bit vectors. While this
may still only be partly possible for some formats, (unless there's AVX2
support) at least the transpose can be done with half the unpacks
(and before using the transpose for AoS fallbacks, it was worse still).
With less than 4 channels, things got way worse with the AoS fallback
quickly even with 128bit vectors.
The strategy is pretty much the same as the existing one for formats
which fit into 32 bits, except there's now multiple vectors to be
fetched (2 or 4 to be exact), which need to be shuffled first (if it's 4
vectors, this amounts to a transpose, for 2 it's a bit different),
then the unpack is done the same (with the exception that the shift
of the channels is now modulo 32, and we need to select the right
vector).
In fact the most complex part about it is to get the shuffles right
for separating into lo/hi parts for AVX/AVX2...
This also makes use of the new ability of gather to use provided type
information, which we abuse to outsmart llvm so we get decent shuffles,
and to fetch 3x32bit vectors without having to ZExt the scalar.
And just because we can, we handle double formats too, albeit they are
a bit different (draw sometimes needs to handle that).
v2: fix typo float/int bug (generating inefficient code).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Sun, 11 Dec 2016 22:39:22 +0000 (23:39 +0100)]
gallivm: optimize gather a bit, by using supplied destination type
By using a dst_type in the the gather interface, gather has some more
knowledge about how values should be fetched.
E.g. if this is a 3x32bit fetch and dst_type is 4x32bit vector gather
will no longer do a ZExt with a 96bit scalar value to 128bit, but
just fetch the 96bit as 3x32bit vector (this is still going to be
2 loads of course, but the loads can be done directly to simd vector
that way).
Also, we can now do some try to use the right int/float type. This should
make no difference really since there's typically no domain transition
penalties for such simd loads, however it actually makes a difference
since llvm will use different shuffle lowering afterwards so the caller
can use this to trick llvm into using sane shuffle afterwards (and yes
llvm is really stupid there - nothing against using the shuffle
instruction from the correct domain, but not at the cost of doing 3 times
more shuffles, the case which actually matters is refusal to use shufps
for integer values).
Also do some attempt to avoid things which look great on paper but llvm
doesn't really handle (e.g. fetching 3-element 8 bit and 16 bit vectors
which is simply disastrous - I suspect type legalizer is to blame trying
to extend these vectors to 128bit types somehow, so fetching these with
scalars like before which is suboptimal due to the ZExt).
Remove the ability for truncation (no point, this is gather, not conversion)
as it is complex enough already.
While here also implement not just the float, but also the 64bit avx2
gathers (disabled though since based on the theoretical numbers the benefit
just isn't there at all until Skylake at least).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Wed, 21 Dec 2016 03:23:55 +0000 (04:23 +0100)]
gallivm: optimize SoA AoS fallback fetch path a little
We should do transpose, not extract/insert, at least with "sufficient" amount
of channels (for 4 channels, extract/insert shuffles generated otherwise look
truly terrifying). Albeit we shouldn't fallback to that so often in any case.
v2: ditch the extract/insert path, not worth keeping (we're going to avoid
hitting the fallback that often with future patches).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Sun, 11 Dec 2016 22:37:30 +0000 (23:37 +0100)]
gallivm: (trivial) handle non-aligned fetch for lp_build_fetch_rgba_soa
soa fetch so far always assumed that data was aligned. However, we want to
use this for vertex fetch, and data might not be aligned there, so handle
it in this path too (basically just pass through alignment through to other
functions). (It looks like it wouldn't work for for cached s3tc but this is
no different than with AoS fetch.)
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Axel Davy [Sun, 18 Dec 2016 18:21:08 +0000 (19:21 +0100)]
st/nine: Upload on secondary context for Draw*Up
Avoid synchronization by using the secondary context
for uploading the vertex data for Draw*Up.
v2: Rely on u_upload_mgr to use persistent coherent
buffers. Do not flush.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Tue, 13 Dec 2016 00:16:21 +0000 (01:16 +0100)]
st/nine: Dirty MANAGED buffers at Lock time
Tests suggest MANAGED buffers are made dirty
at Lock time, not at Unlock time.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Sun, 4 Dec 2016 19:34:59 +0000 (20:34 +0100)]
st/nine: Implement new buffer upload path
This new buffer upload path enables to lock
faster than the normal path when using
DISCARD/NOOVERWRITE.
v2: Diverse cleanups and fixes.
v3: Fix allocation size for 'lone' buffers and
add more debug info.
v4: Rewrite of the path to handle when DISCARD/NOOVERWRITE
is not used anymore. The resource content is copied to the
new resource used.
v5: flush for safety after unmap (not sure it is really required
here, but safer to flush).
v6: Do not use the path if persistent coherent mapping is unavailable.
Fix buffer creation flags.
v7: Do not flush since it is not needed.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Sun, 4 Dec 2016 18:23:11 +0000 (19:23 +0100)]
st/nine: Allow non-zero resource offset for vertex buffers
Next patches will introduce an offset.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Sun, 4 Dec 2016 09:34:34 +0000 (10:34 +0100)]
st/nine: Do not wait for DEFAULT lock for volumes when we can
If the volumes (and the texture container) are not referenced,
then they are no pending operations on them. We can lock directly.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Sun, 4 Dec 2016 09:33:19 +0000 (10:33 +0100)]
st/nine: Do not wait for DEFAULT lock for surfaces when we can
If the surfaces (and the texture container) are not referenced,
then they are no pending operations on them. We can lock directly.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Sun, 4 Dec 2016 09:32:01 +0000 (10:32 +0100)]
st/nine: Add arguments to context's blit and copy_region
The new arguments enable to reference the objects while
the function hasn't run.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Sun, 4 Dec 2016 00:13:25 +0000 (01:13 +0100)]
st/nine: Idem for nine_context_gen_mipmap
Will enable to use the bind count as an information for
whether the surface/volume is used in the worker thread.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Sun, 4 Dec 2016 00:10:34 +0000 (01:10 +0100)]
st/nine: Bind destination for surface/volume uploads
Will enable to use the bind count as an information for
whether the surface/volume is used in the worker thread.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Sat, 3 Dec 2016 23:29:16 +0000 (00:29 +0100)]
st/nine: Use nine_context_box_upload for volumes
Use nine_context_box_upload for uploads:
. systemmem volume to default volume
. managed volume internal content to its resource.
Check the uploads are executed before any action
that can alter the data, that is LockBox and
volume destruction.
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Sun, 4 Dec 2016 23:12:52 +0000 (00:12 +0100)]
st/nine: Fix leak with volume dtor
The last level was not released.
Signed-off-by: Axel Davy <axel.davy@ens.fr>