Jonas Devlieghere [Wed, 19 Aug 2020 15:27:54 +0000 (08:27 -0700)]
[lldb] Convert builders to use inheritance (NFC)
Rather than have different modules for different platforms, use
inheritance so we can have a Builer base class and optional child
classes that override platform specific methods.
Differential revision: https://reviews.llvm.org/D86174
Jakub Lichman [Wed, 19 Aug 2020 15:13:19 +0000 (15:13 +0000)]
[mlir][VectorToSCF] Bug in TransferRead lowering fixed
If Memref has rank > 1 this pass emits N-1 loops around
TransferRead op and transforms the op itself to 1D read. Since vectors
must have static shape while memrefs don't the pass emits if condition
to prevent out of bounds accesses in case some memref dimension is smaller
than the corresponding dimension of targeted vector. This logic is fine
but authors forgot to apply `permutation_map` on loops upper bounds and
thus if condition compares induction variable to incorrect loop upper bound
(dimension of the memref) in case `permutation_map` is not identity map.
This commit aims to fix that.
Jon Chesterfield [Wed, 19 Aug 2020 14:44:30 +0000 (15:44 +0100)]
[libomptarget][amdgpu] Support building with static rocm libraries
Matt Arsenault [Wed, 19 Aug 2020 14:07:57 +0000 (10:07 -0400)]
AMDGPU/GlobalISel: Add some bitcast tests
madhur13490 [Wed, 19 Aug 2020 11:18:52 +0000 (11:18 +0000)]
[NFC] Fix typo in AMDGPU doc
Reviewed By: t-tye, arsenm
Differential Revision: https://reviews.llvm.org/D86206
Matt Arsenault [Tue, 18 Aug 2020 18:45:05 +0000 (14:45 -0400)]
AMDGPU/GlobalISel: Add selection tests for pointer constants
Benjamin Kramer [Wed, 19 Aug 2020 13:59:39 +0000 (15:59 +0200)]
Make helpers static. NFC.
Roman Lebedev [Wed, 19 Aug 2020 13:52:09 +0000 (16:52 +0300)]
Revert "[InstCombine] Lower infinite combine loop detection thresholds"
And as being reported by Florian Hahn, there's a hit
in MultiSource/Benchmarks/mafft from the test-suite on X86 with -O3 -flto,
so reverting until addressed.
This reverts commit
71e0b82c9f5039cb3987c91075e78733ef044c07.
Simon Pilgrim [Wed, 19 Aug 2020 13:41:40 +0000 (14:41 +0100)]
Fix MSVC implicit truncation narrowing conversion warning.
Simon Pilgrim [Wed, 19 Aug 2020 13:34:12 +0000 (14:34 +0100)]
[X86][AVX] lowerShuffleWithVPMOV - minor refactor to more closely match lowerShuffleAsVTRUNC
Replace isBuildVectorAllZeros check by using the Zeroable bitmask instead.
Simon Pilgrim [Wed, 19 Aug 2020 13:14:44 +0000 (14:14 +0100)]
Fix unused variable warnings. NFCI.
Aaron Puchert [Wed, 19 Aug 2020 13:04:44 +0000 (15:04 +0200)]
[CodeGen] Use existing EmitLambdaVLACapture (NFC)
Xing GUO [Wed, 19 Aug 2020 13:13:46 +0000 (21:13 +0800)]
[obj2yaml] Refactor the .debug_pub* sections dumper.
It's good to reuse the DWARF parser in lib/DebugInfo so that we don't
need to maintain a separate parser in client side (obj2yaml). Besides,
A test case is added whose length field is a very huge value which makes
obj2yaml stuck when parsing the section.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D86192
Pavel Labath [Wed, 19 Aug 2020 12:58:50 +0000 (14:58 +0200)]
[lldb] Clean up DW_AT_declaration-with-children.s test
Address some post-commit feedback on D85968.
Pavel Labath [Tue, 18 Aug 2020 13:46:26 +0000 (15:46 +0200)]
[lldb] Add typedefs to the DeclContext they are created in
TypeSystemClang::CreateTypedef was creating a typedef in the right
DeclContext, but it was not actually adding it as a child of the
context. The resulting inconsistent state meant that we would be unable
to reference the typedef from an expression directly, but we could use
them if they end up being pulled in by some previous subexpression
(because the ASTImporter will set up the correct links in the expression
ast).
This patch adds the typedef to the decl context it is created in.
Differential Revision: https://reviews.llvm.org/D86140
Simon Pilgrim [Wed, 19 Aug 2020 12:28:59 +0000 (13:28 +0100)]
[X86] lowerShuffleWithVPMOV - remove unnecessary shuffle commutation. NFCI.
canonicalizeShuffleMaskWithCommute should have already ensured the lower elements are from V1, we do have test coverage for this already.
Simon Pilgrim [Wed, 19 Aug 2020 12:00:09 +0000 (13:00 +0100)]
[X86][AVX] getAVX512TruncNode - don't truncate from illegal vector widths.
Thanks to @fhahn for the test case.
Sanjay Patel [Wed, 19 Aug 2020 11:40:10 +0000 (07:40 -0400)]
[InstCombine] update stale comments in test files; NFC
I missed updating these with:
rG23bd33c6acc4
Roman Lebedev [Wed, 19 Aug 2020 11:36:47 +0000 (14:36 +0300)]
[InstCombine] Lower infinite combine loop detection thresholds
It's been a month since
2f3862eb9f21e8a0d48505637fefe6e5e295c18c,
and no new bug reports about the threshold were filled,
so let's bump it again and wait again.
Raphael Isemann [Wed, 19 Aug 2020 11:30:31 +0000 (13:30 +0200)]
[lldb] Make error messages in TestQueues more helpfull
David Green [Wed, 19 Aug 2020 10:58:50 +0000 (11:58 +0100)]
[ARM] Change target triple to arm-none-none-eabi. NFC
Muhammad Omair Javaid [Wed, 19 Aug 2020 10:47:46 +0000 (15:47 +0500)]
[LLDB] Minor fix in TestSVERegisters.py for AArch64/Linux buildbot
This adds a minor test case fix to previously submitted AArch64 SVE
ptrace support. This was failing on LLDB/AArch64 Linux buildbot.
Differential Revision: https://reviews.llvm.org/D79699
Simon Pilgrim [Wed, 19 Aug 2020 10:39:12 +0000 (11:39 +0100)]
[X86][AVX] computeKnownBitsForTargetNode - add VTRUNC/VTRUNCS/VTRUNCUS known zero upper elements handling.
Like many of the AVX512 conversion ops, the VTRUNC ops guarantee the upper destination elements are zero.
Paul Walker [Tue, 18 Aug 2020 16:47:10 +0000 (17:47 +0100)]
[SVE] Add tests for fixed length vector integer operations with immediate operands.
Muhammad Omair Javaid [Wed, 19 Aug 2020 07:38:30 +0000 (12:38 +0500)]
[LLDB] Add ptrace register access for AArch64 SVE registers
This patch adds NativeRegisterContext_arm64 ptrace routines to access
AArch64 SVE register set. This patch also adds a test-case to test
AArch64 SVE register access and dynamic size configuration capability.
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D79699
Simon Pilgrim [Wed, 19 Aug 2020 09:48:22 +0000 (10:48 +0100)]
[X86][AVX] Fold store(extract_element(vtrunc)) to truncated store
Add handling for storing the extracted lower (truncated bits) element from a X86ISD::VTRUNC node - this can be lowered to a generic truncated store directly.
Differential Revision: https://reviews.llvm.org/D86158
Sander de Smalen [Wed, 19 Aug 2020 09:34:25 +0000 (10:34 +0100)]
[Clang][SVE] NFC: Move info about ACLE types into separate function.
This function returns a struct `BuiltinVectorTypeInfo` that contains
the builtin vector's element type, element count and number of vectors
(used for vector tuples).
Reviewed By: c-rhodes
Differential Revision: https://reviews.llvm.org/D86100
Bjorn Pettersson [Wed, 19 Aug 2020 09:36:03 +0000 (11:36 +0200)]
[GlobalISel] Untabify InstructionSelectorImpl.h. NFC
sstefan1 [Wed, 12 Aug 2020 10:20:53 +0000 (12:20 +0200)]
[OpenMPOpt] ICV tracking for calls
Introduce two new AAs. AAICVTrackerFunctionReturned which checks if a
function can have a unique ICV value after it is finished, and
AAICVCallSiteReturned which checks AAICVTrackerFunctionReturned for a
call site. This enables us to check the value of a call and if it
changes the ICV. This also changes the approach in
`getReplacementValues()` to a worklist-based approach so we can explore
all relevant BBs.
Differential Revision: https://reviews.llvm.org/D85544
sstefan1 [Mon, 17 Aug 2020 17:43:55 +0000 (19:43 +0200)]
[IR] Intrinsics default attributes and opt-out flag
Intrinsic properties can now be set to default and applied to all
intrinsics. If the attributes are not needed, the user can opt-out by
setting the DisableDefaultAttributes flag to true.
Differential Revision: https://reviews.llvm.org/D70365
Meera Nakrani [Wed, 19 Aug 2020 08:36:49 +0000 (08:36 +0000)]
[ARM] Enabled VMLAV and Add instructions to use VMLAVA
Used InstCombine to enable VMLAV and Add instructions to generate VMLAVA instead with tests.
luxufan [Thu, 23 Jul 2020 05:45:14 +0000 (13:45 +0800)]
[RISCV] add the assemble and disassemble support of Zvlsseg instructions
This implements the assemble and disassemble support of RISCV Vector
extension Zvlsseg instructions, base on the 0.9 spec version.
Reviewed by HsiangKai
Differential Revision: https://reviews.llvm.org/D84416
Mauri Mustonen [Wed, 19 Aug 2020 07:54:52 +0000 (08:54 +0100)]
[utils] Fix regexp in llvm/utils/extract_vplan.py to extract VPlans.
Regarding this bug in Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=46451
I went ahead and fixed the regexp pattern and now Python script is able
to extract vplan graphs from the log files. Additionally some test for
this would be nice to have but I'm not sure are Python scripts tested
in LLVM and if so where they live.
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D86068
madhur13490 [Thu, 2 Jul 2020 09:08:06 +0000 (09:08 +0000)]
[GlobalISel] Don't skip adding predicate matcher
This patch fixes a bug which skipped
adding predicate matcher for a pattern in many cases.
For example, if predicate is Load and
its memoryVT is non-null then the loop
continues and never reaches to the end which
adds the predicate matcher. This patch moves the
matcher addition to the top of the loop
so that it gets added regardless of contextual checks
later in the loop.
Other way to fix this issue is to remove all "continue" statements
in checks and let the loop continue till end.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D83034
Florian Hahn [Wed, 19 Aug 2020 07:47:03 +0000 (08:47 +0100)]
[DSE,MemorySSA] Use NumRedundantStores instead of NumNoopStores.
Legacy DSE uses NumRedundantStores, while MemorySSA DSE uses
NumNoopStores. We should just use the same counter.
Ronak Chauhan [Wed, 19 Aug 2020 07:37:40 +0000 (13:07 +0530)]
Revert "[AMDGPU] Support disassembly for AMDGPU kernel descriptors"
This reverts commit
cacfb02d28a3cabd4e45d2535cb0686cef48a2c9.
Reverting due to buildbot failures.
Martin Storsjö [Wed, 19 Aug 2020 07:40:27 +0000 (10:40 +0300)]
[clang] Remove stray semicolons, fixing GCC warnings. NFC.
Muhammad Omair Javaid [Wed, 19 Aug 2020 07:29:16 +0000 (12:29 +0500)]
[LLDB] NativeThreadLinux invalidate register cache on stop
In our discussion D79699 SVE ptrace register access support we decide to
invalidate register context cached data on every stop instead of doing
at before Step/Resume.
InvalidateAllRegisters was added to facilitate flushing of SVE register
context configuration and cached register values. It now makes more
sense to move invalidation after every stop where we initiate SVE
configuration update if needed by calling ConfigureRegisterContext.
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D84501
Muhammad Omair Javaid [Wed, 19 Aug 2020 07:27:02 +0000 (12:27 +0500)]
Convert SVE macros into c++ constants and inlines
This patch updates LLDB's in house version of SVE ptrace/sig macros by
converting them into constants and inlines. They are housed under sve
namespace and are used by process elf-core for reading SVE register data.
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D85641
Haojian Wu [Wed, 19 Aug 2020 07:04:31 +0000 (09:04 +0200)]
[AST] Fix a crash on mangling a binding decl from a DeclRefExpr.
Differential Revision: https://reviews.llvm.org/D86130
David Sherwood [Wed, 12 Aug 2020 13:16:22 +0000 (14:16 +0100)]
[SVE][CodeGen] Fix scalable vector issues in DAGTypeLegalizer::GenWidenVectorLoads
In DAGTypeLegalizer::GenWidenVectorLoads the algorithm assumes it only
ever deals with fixed width types, hence the offsets for each individual
store never take 'vscale' into account. I've changed the code in that
function to use TypeSize instead of unsigned for tracking the remaining
load amount. In addition, I've changed the load loop to use the new
IncrementPointer helper function for updating the addresses in each
iteration, since this handles scalable vector types.
Also, I've added report_fatal_errors in GenWidenVectorExtLoads,
TargetLowering::scalarizeVectorLoad and TargetLowering::scalarizeVectorStores,
since these functions currently use a sequence of element-by-element
scalar loads/stores. In a similar vein, I've also added a fatal error
report in FindMemType for the case when we decide to return the element
type for a scalable vector type.
I've added new tests in
CodeGen/AArch64/sve-split-load.ll
CodeGen/AArch64/sve-ld-addressing-mode-reg-imm.ll
for the changes in GenWidenVectorLoads.
Differential Revision: https://reviews.llvm.org/D85909
Craig Topper [Wed, 19 Aug 2020 06:43:15 +0000 (23:43 -0700)]
[X86][Driver] Remove code that forced a core2 mtune from MachO::TranslateArgs.
mtune was previously ignored by the compiler so I'm not sure this
did anything. But after D85384 we're starting to support mtune
and this code is now causing a couple test failures on MacOS.
Shinji Okumura [Wed, 19 Aug 2020 06:01:14 +0000 (15:01 +0900)]
[Attributor][NFC] Add tests to range.ll
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D86128
Yaxun (Sam) Liu [Wed, 19 Aug 2020 04:21:54 +0000 (00:21 -0400)]
Fix test hip-target-id.hip
Some build bot has lld in the directory name, which caused pattern match
issue in the list test.
LLVM GN Syncbot [Wed, 19 Aug 2020 03:44:19 +0000 (03:44 +0000)]
[gn build] Port
7546b29e761
Yaxun (Sam) Liu [Tue, 5 May 2020 03:22:06 +0000 (23:22 -0400)]
[HIP] Support target id by --offload-arch
This patch introduces support of target id by
-offload-arch.
Differential Revision: https://reviews.llvm.org/D60620
Ronak Chauhan [Fri, 19 Jun 2020 10:25:26 +0000 (15:55 +0530)]
[AMDGPU] Support disassembly for AMDGPU kernel descriptors
Decode AMDGPU Kernel descriptors as assembler directives.
Reviewed By: scott.linder
Differential Revision: https://reviews.llvm.org/D80713
aartbik [Wed, 19 Aug 2020 01:50:33 +0000 (18:50 -0700)]
[mlir] [VectorOps] Cleanup mask 1-d test on constants
I forgot to address this in previous CL. Sorry about that.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D86188
Julian Lettner [Fri, 14 Aug 2020 20:42:50 +0000 (13:42 -0700)]
[TSan][libdispatch] Guard test execution on old platforms
`dispatch_async_and_wait()` was introduced in macOS 10.14. Let's
forward declare it to ensure we can compile the test with older SDKs and
guard execution by checking if the symbol is available. (We can't use
`__builtin_available()`, because that itself requires a higher minimum
deployment target.) We also need to specify the `-undefined
dynamic_lookup` compiler flag.
Differential Revision: https://reviews.llvm.org/D85995
Julian Lettner [Mon, 17 Aug 2020 19:41:18 +0000 (12:41 -0700)]
[TSan][libdispatch] Ensure TSan dylib works on old systems
`dispatch_async_and_wait()` was introduced in macOS 10.14, which is
greater than our minimal deployment target. We need to forward declare
it as a "weak import" to ensure we generate a weak reference so the TSan
dylib continues to work on older systems. We cannot simply `#include
<dispatch.h>` or use the Darwin availability macros since this file is
multi-platform.
In addition, we want to prevent building these interceptors at all when
building with older SDKs because linking always fails.
Before:
```
➤ dyldinfo -bind ./lib/clang/12.0.0/lib/darwin/libclang_rt.tsan_osx_dynamic.dylib | grep dispatch_async_and_wait
__DATA __interpose 0x000F5E68 pointer 0 libSystem _dispatch_async_and_wait_f
```
After:
```
➤ dyldinfo -bind ./lib/clang/12.0.0/lib/darwin/libclang_rt.tsan_osx_dynamic.dylib | grep dispatch_async_and_wait
__DATA __got 0x000EC0A8 pointer 0 libSystem _dispatch_async_and_wait (weak import)
__DATA __interpose 0x000F5E78 pointer 0 libSystem _dispatch_async_and_wait (weak import)
```
This is a follow-up to D85854 and should fix:
https://reviews.llvm.org/D85854#2221529
Reviewed By: kubamracek
Differential Revision: https://reviews.llvm.org/D86103
Julian Lettner [Tue, 11 Aug 2020 22:01:20 +0000 (15:01 -0700)]
Reland "[TSan][libdispatch] Add interceptors for dispatch_async_and_wait()"
The linker errors caused by this revision have been addressed.
Add interceptors for `dispatch_async_and_wait[_f]()` which was added in
macOS 10.14. This pair of functions is similar to `dispatch_sync()`,
but does not force a context switch of the queue onto the caller thread
when the queue is active (and hence is more efficient). For TSan, we
can apply the same semantics as for `dispatch_sync()`.
From the header docs:
> Differences with dispatch_sync()
>
> When the runtime has brought up a thread to invoke the asynchronous
> workitems already submitted to the specified queue, that servicing
> thread will also be used to execute synchronous work submitted to the
> queue with dispatch_async_and_wait().
>
> However, if the runtime has not brought up a thread to service the
> specified queue (because it has no workitems enqueued, or only
> synchronous workitems), then dispatch_async_and_wait() will invoke the
> workitem on the calling thread, similar to the behaviour of functions
> in the dispatch_sync family.
Additional context:
> The guidance is to use `dispatch_async_and_wait()` instead of
> `dispatch_sync()` when it is necessary to mix async and sync calls on
> the same queue. `dispatch_async_and_wait()` does not guarantee
> execution on the caller thread which allows to reduce context switches
> when the target queue is active.
> https://gist.github.com/tclementdev/
6af616354912b0347cdf6db159c37057
rdar://
35757961
Reviewed By: kubamracek
Differential Revision: https://reviews.llvm.org/D85854
Mehdi Amini [Tue, 18 Aug 2020 20:01:19 +0000 (20:01 +0000)]
Separate the Registration from Loading dialects in the Context
This changes the behavior of constructing MLIRContext to no longer load globally
registered dialects on construction. Instead Dialects are only loaded explicitly
on demand:
- the Parser is lazily loading Dialects in the context as it encounters them
during parsing. This is the only purpose for registering dialects and not load
them in the context.
- Passes are expected to declare the dialects they will create entity from
(Operations, Attributes, or Types), and the PassManager is loading Dialects into
the Context when starting a pipeline.
This changes simplifies the configuration of the registration: a compiler only
need to load the dialect for the IR it will emit, and the optimizer is
self-contained and load the required Dialects. For example in the Toy tutorial,
the compiler only needs to load the Toy dialect in the Context, all the others
(linalg, affine, std, LLVM, ...) are automatically loaded depending on the
optimization pipeline enabled.
To adjust to this change, stop using the existing dialect registration: the
global registry will be removed soon.
1) For passes, you need to override the method:
virtual void getDependentDialects(DialectRegistry ®istry) const {}
and registery on the provided registry any dialect that this pass can produce.
Passes defined in TableGen can provide this list in the dependentDialects list
field.
2) For dialects, on construction you can register dependent dialects using the
provided MLIRContext: `context.getOrLoadDialect<DialectName>()`
This is useful if a dialect may canonicalize or have interfaces involving
another dialect.
3) For loading IR, dialect that can be in the input file must be explicitly
registered with the context. `MlirOptMain()` is taking an explicit registry for
this purpose. See how the standalone-opt.cpp example is setup:
mlir::DialectRegistry registry;
registry.insert<mlir::standalone::StandaloneDialect>();
registry.insert<mlir::StandardOpsDialect>();
Only operations from these two dialects can be in the input file. To include all
of the dialects in MLIR Core, you can populate the registry this way:
mlir::registerAllDialects(registry);
4) For `mlir-translate` callback, as well as frontend, Dialects can be loaded in
the context before emitting the IR: context.getOrLoadDialect<ToyDialect>()
Differential Revision: https://reviews.llvm.org/D85622
Mehdi Amini [Wed, 19 Aug 2020 00:32:30 +0000 (00:32 +0000)]
Revert "Separate the Registration from Loading dialects in the Context"
This reverts commit
d14cf45735b0d09d7d3caf0824779520dd20ef10.
The build is broken with GCC-5.
River Riddle [Wed, 19 Aug 2020 00:32:24 +0000 (17:32 -0700)]
[mlir] Update the documentation for defining types
The documentation needs a refresh now that "kinds" are no longer a concept. This revision also adds mentions to a few other new concepts, e.g. traits and interfaces.
Differential Revision: https://reviews.llvm.org/D86182
Brad Smith [Tue, 18 Aug 2020 23:56:19 +0000 (19:56 -0400)]
WCharType and WIntType are always signed int on OpenBSD.
Changpeng Fang [Tue, 18 Aug 2020 23:27:36 +0000 (16:27 -0700)]
AMDGPU: Implement waterfall loop for MIMG instructions with 256-bit SRsrc
Summary:
When the resource descriptor is of vgpr, we need a waterfall loop
to read into a sgpr. In this patchm we generalized the implementation
to work for any regster class sizes, and extend the work to MIMG
instructions.
Fixes: SWDEV-223405
Reviewers:
arsenm, nhaehnle
Differential Revision:
https://reviews.llvm.org/D82603
Mehdi Amini [Tue, 18 Aug 2020 20:01:19 +0000 (20:01 +0000)]
Separate the Registration from Loading dialects in the Context
This changes the behavior of constructing MLIRContext to no longer load globally
registered dialects on construction. Instead Dialects are only loaded explicitly
on demand:
- the Parser is lazily loading Dialects in the context as it encounters them
during parsing. This is the only purpose for registering dialects and not load
them in the context.
- Passes are expected to declare the dialects they will create entity from
(Operations, Attributes, or Types), and the PassManager is loading Dialects into
the Context when starting a pipeline.
This changes simplifies the configuration of the registration: a compiler only
need to load the dialect for the IR it will emit, and the optimizer is
self-contained and load the required Dialects. For example in the Toy tutorial,
the compiler only needs to load the Toy dialect in the Context, all the others
(linalg, affine, std, LLVM, ...) are automatically loaded depending on the
optimization pipeline enabled.
To adjust to this change, stop using the existing dialect registration: the
global registry will be removed soon.
1) For passes, you need to override the method:
virtual void getDependentDialects(DialectRegistry ®istry) const {}
and registery on the provided registry any dialect that this pass can produce.
Passes defined in TableGen can provide this list in the dependentDialects list
field.
2) For dialects, on construction you can register dependent dialects using the
provided MLIRContext: `context.getOrLoadDialect<DialectName>()`
This is useful if a dialect may canonicalize or have interfaces involving
another dialect.
3) For loading IR, dialect that can be in the input file must be explicitly
registered with the context. `MlirOptMain()` is taking an explicit registry for
this purpose. See how the standalone-opt.cpp example is setup:
mlir::DialectRegistry registry;
registry.insert<mlir::standalone::StandaloneDialect>();
registry.insert<mlir::StandardOpsDialect>();
Only operations from these two dialects can be in the input file. To include all
of the dialects in MLIR Core, you can populate the registry this way:
mlir::registerAllDialects(registry);
4) For `mlir-translate` callback, as well as frontend, Dialects can be loaded in
the context before emitting the IR: context.getOrLoadDialect<ToyDialect>()
Differential Revision: https://reviews.llvm.org/D85622
Chuanqi Xu [Tue, 18 Aug 2020 21:30:03 +0000 (14:30 -0700)]
[NFC][StackSafety] Test that StackLifetime looks through stripPointerCasts
StackLifetime class collects lifetime marker of an `alloca` by collect
the user of `BitCast` who is the user of the `alloca`. However, either
the `alloca` itself could be used with the lifetime marker or the `BitCast`
of the `alloca` could be transformed to other instructions. (e.g.,
it may be transformed to all zero reps in `InstCombine` pass).
This patch tries to fix this process in `collectMarkers` functions.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D85399
River Riddle [Tue, 18 Aug 2020 22:59:53 +0000 (15:59 -0700)]
[mlir] Remove the use of "kinds" from Attributes and Types
This greatly simplifies a large portion of the underlying infrastructure, allows for lookups of singleton classes to be much more efficient and always thread-safe(no locking). As a result of this, the dialect symbol registry has been removed as it is no longer necessary.
For users broken by this change, an alert was sent out(https://llvm.discourse.group/t/removing-kinds-from-attributes-and-types) that helps prevent a majority of the breakage surface area. All that should be necessary, if the advice in that alert was followed, is removing the kind passed to the ::get methods.
Differential Revision: https://reviews.llvm.org/D86121
Elliott Hughes [Sat, 11 Apr 2020 00:42:00 +0000 (17:42 -0700)]
ld128 demangle: allow space for 'L' suffix.
Summary:
Caught by HWASAN on arm64 Android (which uses ld128 for long double). This
was running the existing fuzzer.
The specific minimized fuzz input to reproduce this is:
__cxa_demangle("1\006ILeeeEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE", 0, 0, 0);
Reviewers: eugenis, srhines, #libc_abi!
Subscribers: kristof.beyls, danielkiss, libcxx-commits
Tags: #libc_abi
Differential Revision: https://reviews.llvm.org/D77924
Brad Smith [Tue, 18 Aug 2020 22:59:55 +0000 (18:59 -0400)]
Hook up OpenBSD 64-bit RISC-V support
Jonas Devlieghere [Tue, 18 Aug 2020 22:20:46 +0000 (15:20 -0700)]
[lldb] Remove unused function getArchFlag (NFC)
Mehdi Amini [Tue, 18 Aug 2020 22:15:59 +0000 (22:15 +0000)]
Revert "Separate the Registration from Loading dialects in the Context"
This reverts commit
e1de2b75501e5eaf8777bd5248382a7c55a44fd6.
Broke a build bot.
Craig Topper [Tue, 18 Aug 2020 21:52:44 +0000 (14:52 -0700)]
[X86] Add basic support for -mtune command line option in clang
Building on the backend support from D85165. This parses the command line option in the driver, passes it on to CC1 and adds a function attribute.
-Still need to support tune on the target attribute.
-Need to use "generic" as the tuning by default. But need to change generic in the backend first.
-Need to set tune if march is specified and mtune isn't.
-May need to disable getHostCPUName's ability to guess CPU name from features when it doesn't have a family/model match for mtune=native. That's what gcc appears to do.
Differential Revision: https://reviews.llvm.org/D85384
Roman Lebedev [Tue, 18 Aug 2020 22:08:38 +0000 (01:08 +0300)]
[NFC][InstCombine] Aggregate reconstruction: use plain map
Now that we no longer require for this map to have stable iteration order,
we no longer need to pay for keeping the iteration order stable,
so switch from `SmallMapVector` to `SmallDenseMap`.
Nithin Vadukkumchery Rajendrakumar [Tue, 11 Aug 2020 22:05:06 +0000 (00:05 +0200)]
[Analysis] Bug fix for exploded graph branching in evalCall for constructor
Summary:
Make exactly single NodeBuilder exists at any given time
Reviewers: NoQ, Szelethus, vsavchenko, xazax.hun
Reviewed By: NoQ
Subscribers: martong, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D85796
Roman Lebedev [Tue, 18 Aug 2020 21:59:07 +0000 (00:59 +0300)]
[InstCombine] PHI-aware aggregate reconstruction: properly handle duplicate predecessors
While it may seem like we can just "deduplicate" the case where
some basic block happens to be a predecessor more than once,
which happens for e.g. switches, that is not correct thing to do.
We must actually add a PHI operand for each predecessor.
This was initially reported to me by David Major
as a clang crash during gecko build for android.
Amara Emerson [Tue, 18 Aug 2020 21:54:56 +0000 (14:54 -0700)]
Use std::make_tuple instead of initializer lists to make a bot happy:
http://lab.llvm.org:8011/builders/clang-cmake-x86_64-avx2-linux
Sterling Augustine [Tue, 18 Aug 2020 19:05:07 +0000 (12:05 -0700)]
Default to disabling the libunwind frameheader cache.
Although it works fine with glibc, as currently implemented the
frameheader cache is incompatible with certain platforms with
slightly different locking semantics inside dl_iterate_phdr.
Therefore only enable it when it is turned on explicitly with
a configure-time option.
Differential Revision: https://reviews.llvm.org/D86163
Craig Topper [Tue, 18 Aug 2020 20:59:26 +0000 (13:59 -0700)]
[X86] Fix the Predicates on MMX_PSHUFWri/PSHUFWmi to include SSE1 in addition to MMX.
These instructions weren't in the initial version of MMX, but
were added when SSE1 was introduced. We already have the intrinsic
named correctly to include sse and the frontened header enforces
sse. We have one place in the backend where we DAG combine to
this intrinsic, but that's also qualified. So don't know of anything
currently broken unless someone writes their own IR and doesn't
set the sse feature.
Mehdi Amini [Tue, 18 Aug 2020 20:01:19 +0000 (20:01 +0000)]
Separate the Registration from Loading dialects in the Context
This changes the behavior of constructing MLIRContext to no longer load globally
registered dialects on construction. Instead Dialects are only loaded explicitly
on demand:
- the Parser is lazily loading Dialects in the context as it encounters them
during parsing. This is the only purpose for registering dialects and not load
them in the context.
- Passes are expected to declare the dialects they will create entity from
(Operations, Attributes, or Types), and the PassManager is loading Dialects into
the Context when starting a pipeline.
This changes simplifies the configuration of the registration: a compiler only
need to load the dialect for the IR it will emit, and the optimizer is
self-contained and load the required Dialects. For example in the Toy tutorial,
the compiler only needs to load the Toy dialect in the Context, all the others
(linalg, affine, std, LLVM, ...) are automatically loaded depending on the
optimization pipeline enabled.
To adjust to this change, stop using the existing dialect registration: the
global registry will be removed soon.
1) For passes, you need to override the method:
virtual void getDependentDialects(DialectRegistry ®istry) const {}
and registery on the provided registry any dialect that this pass can produce.
Passes defined in TableGen can provide this list in the dependentDialects list
field.
2) For dialects, on construction you can register dependent dialects using the
provided MLIRContext: `context.getOrLoadDialect<DialectName>()`
This is useful if a dialect may canonicalize or have interfaces involving
another dialect.
3) For loading IR, dialect that can be in the input file must be explicitly
registered with the context. `MlirOptMain()` is taking an explicit registry for
this purpose. See how the standalone-opt.cpp example is setup:
mlir::DialectRegistry registry;
mlir::registerDialect<mlir::standalone::StandaloneDialect>();
mlir::registerDialect<mlir::StandardOpsDialect>();
Only operations from these two dialects can be in the input file. To include all
of the dialects in MLIR Core, you can populate the registry this way:
mlir::registerAllDialects(registry);
4) For `mlir-translate` callback, as well as frontend, Dialects can be loaded in
the context before emitting the IR: context.getOrLoadDialect<ToyDialect>()
MaheshRavishankar [Tue, 18 Aug 2020 20:26:29 +0000 (13:26 -0700)]
[mlir][Linalg] Modify callback for getting id/nprocs in
LinalgDistribution options to allow more general distributions.
Changing the signature of the callback to send in the ranges for all
the parallel loops and expect a vector with the Value to use for the
processor-id and number-of-processors for each of the parallel loops.
Differential Revision: https://reviews.llvm.org/D86095
David Blaikie [Tue, 18 Aug 2020 18:06:16 +0000 (11:06 -0700)]
Recommit "PR44685: DebugInfo: Handle address-use-invalid type units referencing non-type units"
Originally committed as
be3ef93bf58aa5546c7baadfb21d43b75fbb4e24.
Reverted by
b4bffdbadfcceb3959aaf231c1542301944e5812 due to bot
failures:
http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-expensive/17380/testReport/junit/LLVM/DebugInfo_X86/addr_tu_to_non_tu_ll/
http://45.33.8.238/win/22216/step_11.txt
MacOS failure due to testing Split DWARF which isn't compatible with
MachO.
Windows failure due to testing type units which aren't enabled on
Windows.
Fix both of these by applying an explicit x86 linux triple to the test.
Zequan Wu [Mon, 17 Aug 2020 22:25:08 +0000 (15:25 -0700)]
[Coverage] Adjust skipped regions only if {Prev,Next}TokLoc is in the same file as regions' {start, end}Loc
Fix a bug if {Prev, Next}TokLoc is in different file from skipped regions' {start, end}Loc
Differential Revision: https://reviews.llvm.org/D86116
Greg Clayton [Tue, 18 Aug 2020 00:26:50 +0000 (17:26 -0700)]
Fix a check that was attempting to see if an object file was in memory.
Checking if an object file is in memory should use the ObjectFile::IsInMemory(), not test ObjectFile::BaseAddress(). ObjectFile::BaseAddress() is designed to be overridden by all classes and is for mach-o, ELF and COFF plug-ins. They find the header base adddress and return that as a section offset address. The default implementation of ObjectFile::BaseAddress() does try and make an Address() from the ObjectFile::m_memory_addr, but I switched it to a correct function call.
Differential Revision: https://reviews.llvm.org/D86122
Sanjay Patel [Tue, 18 Aug 2020 17:44:29 +0000 (13:44 -0400)]
[VectorCombine] add tests for vector loads; NFC
Marius Brehler [Tue, 18 Aug 2020 20:16:00 +0000 (22:16 +0200)]
[mlir] Check libraries linked into standalone-opt
Adds a call to mlir_check_all_link_libraries() to check all libraries
linked into standalone-opt.
Eli Friedman [Mon, 10 Aug 2020 19:23:03 +0000 (12:23 -0700)]
[AArch64][SVE] Add patterns for integer mla/mls.
We probably want to introduce pseudo-instructions at some point, like
we have for binary operations, but this seems okay for now.
One thing I'm not sure about is whether we should be doing this as a
DAGCombine instead of directly pattern-matching it. I don't see any big
downside to doing it this way, though.
Differential Revision: https://reviews.llvm.org/D85681
Eli Friedman [Tue, 4 Aug 2020 21:57:16 +0000 (14:57 -0700)]
[AArch64][SVE] Allow llvm.aarch64.sve.st2/3/4 with vectors of pointers.
This isn't necessaary for ACLE, but could be useful in other situations.
And the change is simple.
Differential Revision: https://reviews.llvm.org/D85251
Eli Friedman [Fri, 31 Jul 2020 00:32:39 +0000 (17:32 -0700)]
[clang codegen] Use IR "align" attribute for static array arguments.
Without the "align" attribute, marking the argument dereferenceable is
basically useless. See also D80166.
Fixes https://bugs.llvm.org/show_bug.cgi?id=46876 .
Differential Revision: https://reviews.llvm.org/D84992
Craig Topper [Tue, 18 Aug 2020 19:29:58 +0000 (12:29 -0700)]
[X86] Don't call SemaBuiltinConstantArg from CheckX86BuiltinTileDuplicate if Argument is Type or Value Dependent.
SemaBuiltinConstantArg has an early exit for that case that doesn't
produce an error and doesn't update the APInt. We need to detect that
case and not use the APInt value.
While there delete the signature of CheckX86BuiltinTileArgumentsRange
that takes a single Argument index to check. There's another version
that takes an ArrayRef and single value is convertible to an ArrayRef.
Mehdi Amini [Tue, 18 Aug 2020 19:03:40 +0000 (19:03 +0000)]
Remove MLIREDSCInterface library which isn't used anywhere (NFC)
Reviewed By: nicolasvasilache, ftynse
Differential Revision: https://reviews.llvm.org/D85042
Jessica Paquette [Tue, 18 Aug 2020 17:37:10 +0000 (10:37 -0700)]
[GlobalISel][CallLowering] NFC: Unify flag-setting from CallBase + AttributeList
It's annoying to have to maintain multiple, nearly identical chains of if
statements which all set the same attributes.
Add a helper function, `addFlagsUsingAttrFn` which performs the attribute
setting.
Then, use wrappers for that function in `lowerCall` and `setArgFlags`.
(Note that the flag-setting code in `setArgFlags` was missing the returned
attribute. There's no selection for this yet, so no test. It's an example of
the kind of thing this lets us avoid, though.)
Differential Revision: https://reviews.llvm.org/D86159
Jessica Paquette [Tue, 18 Aug 2020 16:23:48 +0000 (09:23 -0700)]
[GlobalISel][CallLowering] Don't tail call with non-forwarded explicit sret
Similar to this commit:
faf8065a99817bcb10e6f09b558fe3e0972c35ce
Testcase is pretty much the same as
test/CodeGen/AArch64/tailcall-explicit-sret.ll
Except it uses i64 (since we don't handle the i1024 return values yet), and
doesn't have indirect tail call testcases (because we can't translate those
yet).
Differential Revision: https://reviews.llvm.org/D86148
Siva Chandra Reddy [Tue, 18 Aug 2020 18:04:58 +0000 (11:04 -0700)]
[libc][obvious] Fix link order of math tests.
Tue Ly [Tue, 28 Jul 2020 05:35:18 +0000 (01:35 -0400)]
[libc] Add ULP function to MPFRNumber class to test correctly rounded functions such as SQRT, FMA.
Add ULP function to MPFRNumber class to test correctly rounded functions.
Differential Revision: https://reviews.llvm.org/D84725
Matt Arsenault [Tue, 28 Jul 2020 02:00:50 +0000 (22:00 -0400)]
GlobalISel: Implement fewerElementsVector for G_INSERT_VECTOR_ELT
Add unit tests since AMDGPU will only trigger this for gigantic
vectors, and won't use the annoying odd sized breakdown case.
David Blaikie [Fri, 14 Aug 2020 14:56:29 +0000 (07:56 -0700)]
[WIP][DebugInfo] Lazily parse debug_loclist offsets
Parsing DWARFv5 debug_loclist offsets when a CU is parsed is weighing
down memory usage of symbolizers that don't need to parse this data at
all. There's not much benefit to caching these anyway - since they are
O(1) lookup and reading once you know where the offset list starts (and
can do bounds checking with the offset list size too).
In general, I think it might be time to start paying down some of the
technical debt of loc/loclist/range/rnglist parsing to try to unify it a
bit more.
eg:
* Currently DWARFUnit has: RangeSection, RangeSectionBase, LocSection,
LocSectionBase, LocTable, RngListTable, LoclistTableHeader (be nice if
these were all wrapped up in two variables - one for loclists, one for
rnglists)
* rnglists and loclists are handled differently (see:
LoclistTableHeader, but no RnglistTableHeader)
* maybe all these types could be less stateful - lazily parse what they
need to, even reparsing rather than caching because it doesn't seem
too expensive, for instance. (though admittedly so long as it's
constantcost/overead per compilatiton that's probably adequate)
* Maybe implementing and using a DWARFDataExtractor that can be
sub-ranged (so we could slice it up to just the single contribution) -
though maybe that's not so useful because loc/ranges need to refer to
it by absolute, not contribution-relative mechanisms
Differential Revision: https://reviews.llvm.org/D86110
Tim Keith [Tue, 18 Aug 2020 17:47:52 +0000 (10:47 -0700)]
[flang] Improve error messages for procedures in expressions
When a procedure name was used on the RHS of an assignment we were not
reporting the error. When one was used in an expression the error
message wasn't very good (e.g. "Operands of + must be numeric; have
INTEGER(4) and untyped").
Detect these cases in ArgumentAnalyzer and emit better messages,
depending on whether the named procedure is a function or subroutine.
Procedure names may appear as actual arguments to function and
subroutine calls so don't report errors in those cases. That is the same
case where assumed type arguments are allowed, so rename `isAssumedType_`
to `isProcedureCall_` and use that to decide if it is an error.
Differential Revision: https://reviews.llvm.org/D86107
Amara Emerson [Fri, 14 Aug 2020 09:00:07 +0000 (02:00 -0700)]
[GlobalISel] Add a combine for sext_inreg(load x), c --> sextload x
This is restricted to single use loads, which if we fold to sextloads we can
find more optimal addressing modes on AArch64.
This also fixes an overload the MachineFunction::getMachineMemOperand() method
which was incorrectly using the MF alignment instead of the MMO alignment.
Differential Revision: https://reviews.llvm.org/D85966
Amara Emerson [Fri, 14 Aug 2020 08:58:00 +0000 (01:58 -0700)]
[GlobalISel] Add a combine for ashr(shl x, c), c --> sext_inreg x, c'
By detecting this sign extend pattern early, we can uncover opportunities for
more optimizations.
Differential Revision: https://reviews.llvm.org/D85965
Rob Suderman [Thu, 13 Aug 2020 21:59:58 +0000 (14:59 -0700)]
Added std.floor operation to match std.ceil
There should be an equivalent std.floor op to std.ceil. This includes
matching lowerings for SPIRV, NVVM, ROCDL, and LLVM.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D85940
Arthur Eubanks [Sat, 15 Aug 2020 00:09:23 +0000 (17:09 -0700)]
[gn build] Add support for expensive checks
Reviewed By: hans, MaskRay
Differential Revision: https://reviews.llvm.org/D86007
Simon Pilgrim [Tue, 18 Aug 2020 16:08:49 +0000 (17:08 +0100)]
[X86][AVX] lowerShuffleWithVPMOV - add non-VLX support.
We can efficiently handle non-VLX cases now that we have the getAVX512TruncNode helper.
Arthur Eubanks [Tue, 18 Aug 2020 16:49:05 +0000 (09:49 -0700)]
Revert "[TSan][libdispatch] Add interceptors for dispatch_async_and_wait()"
This reverts commit
d137db80297f286f3a19eacc63d4a980646da437.
Breaks builds on older SDKs.
Mauricio Sifontes [Tue, 18 Aug 2020 16:47:06 +0000 (16:47 +0000)]
Create Optimization Pass Wrapper for MLIR Reduce
Create a reduction pass that accepts an optimization pass as argument
and only replaces the golden module in the pipeline if the output of the
optimization pass is smaller than the input and still exhibits the
interesting behavior.
Add a -test-pass option to test individual passes in the MLIR Reduce
tool.
Reviewed By: jpienaar
Differential Revision: https://reviews.llvm.org/D84783
Fangrui Song [Tue, 18 Aug 2020 16:20:05 +0000 (09:20 -0700)]
[ARM] Fix build after D86087
Mott, Jeffrey T [Fri, 17 Jul 2020 16:50:08 +0000 (09:50 -0700)]
Disable use of _ExtInt with '__atomic' builtins
We're (temporarily) disabling ExtInt for the '__atomic' builtins so we can better design their behavior later. The idea is until we do an audit/design for the way atomic builtins are supposed to work with _ExtInt, we should leave them restricted so they don't limit our future options, such as by binding us to a sub-optimal implementation via ABI.
Example after this change:
$ cat test.c
void f(_ExtInt(64) *ptr) {
__atomic_fetch_add(ptr, 1, 0);
}
$ clang -c test.c
test.c:2:22: error: argument to atomic builtin of type '_ExtInt' is not supported
__atomic_fetch_add(ptr, 1, 0);
^
1 error generated.
Differential Revision: https://reviews.llvm.org/D84049
David Green [Tue, 18 Aug 2020 16:15:45 +0000 (17:15 +0100)]
[ARM] Allow tail predication of VLDn
VLD2/4 instructions cannot be predicated, so we cannot tail predicate
them from autovec. From intrinsics though, they should be valid as they
will just end up loading extra values into off vector lanes, not
effecting the on lanes. The same is true for loads in general where so
long as we are not using the other vector lanes, an unpredicated load
can be converted to a predicated one.
This marks VLD2 and VLD4 instructions as validForTailPredication and
allows any unpredicated load in tail predication loop, which seems to be
valid given the other checks we have.
Differential Revision: https://reviews.llvm.org/D86022
Jan Kratochvil [Tue, 18 Aug 2020 16:09:55 +0000 (18:09 +0200)]
[lldb] [testsuite] Add split-file for check-lldb dependencies
D85968 started to use `split-file` and while buildbots run fine while
doing `make check-lldb` by hand I get:
.../llvm-monorepo-clangassert/tools/lldb/test/SymbolFile/DWARF/Output/DW_AT_declaration-with-children.s.script: line 2: split-file: command not found
failed:
lldb-shell :: SymbolFile/DWARF/DW_AT_declaration-with-children.s
Differential Revision: https://reviews.llvm.org/D86144