Ilia Mirkin [Sun, 31 Jan 2016 06:09:40 +0000 (01:09 -0500)]
mesa: use default geometry's samples when there are no attachments
Whether multisampling is turned on depends, in part, on whether
attachments are themselves multisample surfaces. However when there are
no attachments, we should rely on the default geometry for this.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Sat, 23 Jan 2016 14:27:22 +0000 (09:27 -0500)]
mesa: invalidate framebuffer when changing parameters
This fixes dEQP-GLES31.functional.fbo.completeness.no_attachments
When the width or height are 0, the framebuffer is incomplete. We may
also not have been passing the new state down to the driver when the
widths/heights/etc changed. Make sure to dirty the state so that the
framebuffer state is revalidated at draw time.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Ilia Mirkin [Sun, 31 Jan 2016 05:44:14 +0000 (00:44 -0500)]
mesa: use geometric helper for computing min samples
In case we have a draw buffer without attachments, we should be looking
at the default number of samples.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Ilia Mirkin [Sat, 23 Jan 2016 13:25:35 +0000 (08:25 -0500)]
mesa: the _mesa_geometric_* functions require full types from mtypes.h
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Niels Ole Salscheider [Fri, 29 Jan 2016 21:48:57 +0000 (22:48 +0100)]
winsys/radeon: Do not deinit the pb cache if it was not initialized
This fixes a crash in pb_cache_release_all_buffers.
Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Fri, 8 Jan 2016 23:47:39 +0000 (00:47 +0100)]
tgsi/scan: add tgsi_shader_info::reads_samplemask
Marek Olšák [Sun, 17 Jan 2016 20:13:16 +0000 (21:13 +0100)]
radeonsi: rework RB+ for Stoney
This fixes it.
States which also need to be taken into account:
- SPI color formats - each down-conversion format supports only a limited set
of SPI formats
- whether MSAA resolving and logic op are enabled
These need special handling:
- blending
- disabled channels
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 23 Dec 2015 14:51:25 +0000 (15:51 +0100)]
radeonsi: rename cb_target_mask state to cb_render_state
and rename a variable in the function.
SX_PS_DOWNCONVERT will be emitted here.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 28 Jan 2016 00:35:19 +0000 (01:35 +0100)]
radeonsi: treat intensity render targets exactly like red
The motivation is to simplify the Stoney RB+ code.
Intensity is already treated as red except here.
No piglit regressions.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 29 Jan 2016 23:38:53 +0000 (00:38 +0100)]
tgsi: set correct src type for UP2H
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Connor Abbott [Sun, 15 Nov 2015 01:24:31 +0000 (20:24 -0500)]
util/hash_table: don't compare deleted entries
The equivalent of the last patch for the hash table. I'm not aware of
any issues this fixes.
v2:
- use entry_is_deleted (Timothy)
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Connor Abbott [Sun, 15 Nov 2015 01:20:42 +0000 (20:20 -0500)]
util/set: don't compare against deleted entries
When we delete entries in the hash set, we mark them "deleted" by
setting their key to the deleted_key, which points to a dummy
deleted_key_value. When searching for an entry, we normally skip over
those, but set_add() had some code for searching for duplicate entries
which forgot to skip over deleted entries. This led to a segfault inside
the NIR vectorization pass, since its key comparison function
interpreted the memory where deleted_key_value resides as a pointer and
tried to dereference it.
v2:
- add better commit message (Timothy)
- use entry_is_deleted (Timothy)
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Jordan Justen [Wed, 20 Jan 2016 07:27:22 +0000 (23:27 -0800)]
glsl: Disable tree grafting optimization for shared variables
Fixes:
* dEQP-GLES31.functional.compute.basic.shared_atomic_op_multiple_groups
* dEQP-GLES31.functional.compute.basic.shared_atomic_op_multiple_invocation
* dEQP-GLES31.functional.compute.basic.shared_atomic_op_single_group
* dEQP-GLES31.functional.compute.basic.shared_atomic_op_single_invocation
From https://android.googlesource.com/platform/external/deqp
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jordan Justen [Wed, 20 Jan 2016 07:23:23 +0000 (23:23 -0800)]
glsl: Enable debug prints for do_common_optimization
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Roland Scheidegger [Tue, 2 Feb 2016 14:45:59 +0000 (15:45 +0100)]
Revert "i965: Provide sse2 version for rgba8 <-> bgra8 swizzle"
This reverts commit
ab30426e335116e29473faaafe8b57ec760516ee.
Apparently the memory isn't quite as aligned when this gets called
as it should be, causing crashes. (Albeit this looks independent
from this code, should crash just as well if ssse3 is enabled when
compiling without this patch.)
https://bugs.freedesktop.org/show_bug.cgi?id=93962
Dave Airlie [Tue, 2 Feb 2016 07:54:43 +0000 (17:54 +1000)]
virgl: mark function as static
This is fallout from the previous changes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93961
Signed-off-by: Dave Airlie <airlied@redhat.com>
Roland Scheidegger [Tue, 2 Feb 2016 02:51:22 +0000 (03:51 +0100)]
gallivm: add PK2H/UP2H support
Add support for these opcodes, the conversion functions were already
there albeit need some new packing stuff.
Just like the tgsi version, piglit won't like it for all the same
reasons, so it's disabled (UP2H passes piglit arb_shader_language_packing
tests, albeit since PK2H won't due to those rounding differences I don't
know if that one works or not as the piglit test is rather difficult to
deal with).
Reviewed-by: Brian Paul <brianp@vmware.com>
Roland Scheidegger [Fri, 29 Jan 2016 01:49:22 +0000 (02:49 +0100)]
gallivm: add PK2H/UP2H support
Add support for these opcodes, the conversion functions were already
there albeit need some new packing stuff.
Just like the tgsi version, piglit won't like it for all the same
reasons, so it's disabled (UP2H passes piglit arb_shader_language_packing
tests, albeit since PK2H won't due those rounding differences I don't
know if that one works or not as the piglit test is rather difficult to
deal with).
Roland Scheidegger [Tue, 2 Feb 2016 02:36:19 +0000 (03:36 +0100)]
tgsi: add PK2H/UP2H support
The util functions handle the half-float conversion.
Note that piglit won't like it much due to:
a) The util functions use magic float mul conversion but when run inside
softpipe/llvmpipe, denorms are flushed to zero, therefore when the conversion
is from/to f16 denorm the result will be zero. This is a bug which should be
fixed in these functions (should not rely on denorms being available), but
will happen elsewhere just the same (e.g. conversion to f16 render targets).
b) The util functions use trunc round mode rather than round-to-nearest. This
is NOT a bug (as it is a d3d10 requirement). This will result of rounding not
representable finite values to MAX_F16 rather than INFINITY. My belief is the
piglit tests are wrong here but it's difficult to tell (generally glsl
rounding mode is undefined, however I'm not sure if rounding mode might need
to be consistent for different operations). Nevertheless, for gl it would be
better to use round-to-nearest, but using different rounding for GL and d3d10
is an unsolved problem (as it affects things like conversion to f16 render
targets, clear colors, this shader opcode).
Hence for now don't enable the cap bit (so the code is unused).
(Code is from imirkin, comment from sroland)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmvware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Roland Scheidegger [Tue, 2 Feb 2016 02:14:12 +0000 (03:14 +0100)]
llvmpipe: drop scissor planes early if the tri is fully inside them
If the tri is fully inside a scissor edge (or rather, we just use the
bounding box of the tri for the comparison), then we can drop these
additional scissor "planes" early. We do not even need to allocate
space for them in the tri.
The math actually appears to be slightly iffy due to bounding boxes
being rounded, but it doesn't matter in the end.
Those scissor rects are costly - the 4 planes from the scissor are
already more expensive to calculate than the 3 planes from the tri itself,
and it also prevents us from using the specialized raster code for small
tris.
This helps openarena performance by about 8% or so. Of course, it helps
there that while openarena often enables scissoring (and even moves the
scissor rect around) I have not seen a single tri actually hit the
scissor rect, ever.
v2: drop individual scissor edges, and do it earlier, not even allocating
space for them.
v3: help the compiler a bit with simpler code, suggested by Brian.
Reviewed-by: Brian Paul <brianp@vmware.com>
Roland Scheidegger [Sun, 31 Jan 2016 00:27:09 +0000 (01:27 +0100)]
llvmpipe: minor cleanup of sse2 for calc_fixed_position
Just slightly simpler assembly.
Reviewed-by: Brian Paul <brianp@vmware.com>
Roland Scheidegger [Sun, 31 Jan 2016 00:26:59 +0000 (01:26 +0100)]
llvmpipe: use vector loads for (optimized) tri raster funcs
When we switched to 64bit rasterization, we could no longer use straight
aligned loads for loading the plane data. However, what the code actually
does for loading 3 planes, is 12 scalar loads + 9 unpacks, and then there's
another 8 unpacks for the transpose we need (!).
It would be possible to do the (scalar) loads of course already transposed
(at least saving the additional unpacks), however instead just use
(un)aligned vector loads, and recalculate the eo values, which is much less
instructions (note in case of the triangle_32_3_4 case, the eo values are
not even used, making the scalar loads + unpacks for them all the more
pointless).
This drops execution time of the triangle_32_3_4 function considerably,
albeit it doesn't really make a measurable difference (for small tris we're
essentially limited by vertex throughput in any case), for triangle_32_3_16
it's essentially noise (the loop is more costly than the initial code there).
(I'm thinking about just ditching storing the eo values in the plane data,
so could switch back to using aligned planes, however right now they are
still used in the other raster functions dealing with planes with scalar
code. Also not touching the ppc code, might not be that bad there in any
case.)
Reviewed-by: Brian Paul <brianp@vmware.com>
Roland Scheidegger [Fri, 29 Jan 2016 02:18:36 +0000 (03:18 +0100)]
i965: Provide sse2 version for rgba8 <-> bgra8 swizzle
The existing code used ssse3, and because it isn't compiled in a separate
file compiled with that, it is usually not used (that, of course, could
be fixed...), whereas sse2 is always present at least with 64bit builds.
This should be pretty much as fast as the pshufb version, albeit those
code paths aren't really used on chips without llc in any case.
v2: fix andnot argument order, add comments
v3: use pshuflw/hw instead of shifts (suggested by Matt Turner), cut comments
Reviewed-by: Matt Turner <mattst88@gmail.com>
Roland Scheidegger [Fri, 29 Jan 2016 01:58:29 +0000 (02:58 +0100)]
mesa: fix typo in python scripts
Reviewed-by: Matt Turner <mattst88@gmail.com>
Rob Herring [Fri, 29 Jan 2016 18:52:28 +0000 (12:52 -0600)]
virgl: also build vtest for Android
Enabling swrast on Android causes a link error because vtest is missing.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Rob Herring [Fri, 29 Jan 2016 22:36:29 +0000 (16:36 -0600)]
virgl: fix reference counting of prime handles
The virgl reference counting of buffers is broken for prime fd buffers.
Each prime fd passed into virgl_drm_winsys_resource_create_handle creates
a new resource. The solution requires creating a separate hash table to
track flink names separately from prime handles.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Rob Herring [Fri, 29 Jan 2016 22:36:28 +0000 (16:36 -0600)]
virgl: reuse screen when fd is already open
It is necessary to share the screen between mesa and gralloc to
properly ref count resources. This implements a hash lookup on
the file description to re-use an already created screen. This is
a similar implementation as freedreno and radeon.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Mauro Rossi [Mon, 1 Feb 2016 22:37:42 +0000 (23:37 +0100)]
nouveau/video: wrap assertion within #ifndef NDEBUG
The change is necessary to avoid the following building error in android:
external/mesa/src/gallium/drivers/nouveau/nouveau_vp3_video_bsp.c: In function 'nouveau_vp3_bsp_next':
external/mesa/src/gallium/drivers/nouveau/nouveau_vp3_video_bsp.c:269:14: error: 'bsp_bo' undeclared (first use in this function)
assert(bsp_bo->size >= str_bsp->w0[0] + num_bytes[i]);
^
This matches the declaration of the variables in question.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 29 Jan 2016 19:45:38 +0000 (14:45 -0500)]
st/mesa: treat a write as a read for range purposes
We use this logic to detect live ranges and then do plain renaming
across the whole codebase. As such, to prevent WaW hazards, we have to
treat a write as if it were also a read.
For example, the following sequence was observed before this patch:
13: UIF TEMP[6].xxxx :0
14: ADD TEMP[6].x, CONST[6].xxxx, -IN[3].yyyy
15: RCP TEMP[7].x, TEMP[3].xxxx
16: MUL TEMP[3].x, TEMP[6].xxxx, TEMP[7].xxxx
17: ADD TEMP[6].x, CONST[7].xxxx, -IN[3].yyyy
18: RCP TEMP[7].x, TEMP[3].xxxx
19: MUL TEMP[4].x, TEMP[6].xxxx, TEMP[7].xxxx
While after this patch it becomes:
13: UIF TEMP[7].xxxx :0
14: ADD TEMP[7].x, CONST[6].xxxx, -IN[3].yyyy
15: RCP TEMP[8].x, TEMP[3].xxxx
16: MUL TEMP[4].x, TEMP[7].xxxx, TEMP[8].xxxx
17: ADD TEMP[7].x, CONST[7].xxxx, -IN[3].yyyy
18: RCP TEMP[8].x, TEMP[3].xxxx
19: MUL TEMP[5].x, TEMP[7].xxxx, TEMP[8].xxxx
Most importantly note that in the first example, the second RCP is done
on the result of the MUL while in the second, the second RCP should have
the same value as the first. Looking at the GLSL source, it is apparent
that both of the RCP's should have had the same source.
Looking at what's going on, the GLSL looks something like
float tmin_8;
float tmin_10;
tmin_10 = tmin_8;
... lots of code ...
tmin_8 = tmpvar_17;
... more code that never looks at tmin_8 ...
And so we end up with a last_read somewhere at the beginning, and a
first_write somewhere at the bottom. For some reason DCE doesn't remove
it, but even if that were fixed, DCE doesn't handle 100% of cases, esp
including loops.
With the last_read somewhere high up, we overwrite the previously
correct (and large) last_read with a low one, and then proceed to decide
to merge all kinds of junk onto this temp. Even if that weren't the
case, and there were just some writes after the last read, then we might
still overwrite a merged value with one of those.
As a result, we should treat a write as a last_read for the purpose of
determining the live range.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Cc: mesa-stable@lists.freedesktop.org
Matt Turner [Mon, 25 Jan 2016 19:07:28 +0000 (11:07 -0800)]
i965/gen7+: Use NIR for lowering of pack/unpack opcodes.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Mon, 25 Jan 2016 18:49:15 +0000 (10:49 -0800)]
i965/vec4: Implement nir_op_pack_uvec2_to_uint.
And mark nir_op_pack_uvec4_to_uint unreachable, since it's only produced
by lowering pack[SU]norm4x8 which the vec4 backend does not need.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Mon, 25 Jan 2016 19:07:02 +0000 (11:07 -0800)]
nir: Add lowering support for unpacking opcodes.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Mon, 25 Jan 2016 19:05:52 +0000 (11:05 -0800)]
nir: Add lowering support for packing opcodes.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Thu, 21 Jan 2016 02:56:37 +0000 (18:56 -0800)]
i965/fs: Implement support for extract_word.
The vec4 backend will lower it.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Thu, 21 Jan 2016 17:09:29 +0000 (09:09 -0800)]
nir: Add opcodes to extract bytes or words.
The uint versions zero extend while the int versions sign extend.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Thu, 21 Jan 2016 19:46:22 +0000 (11:46 -0800)]
glsl: Remove 2x16 half-precision pack/unpack opcodes.
i965/fs was the only consumer, and we're now doing the lowering in NIR.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Thu, 21 Jan 2016 23:30:57 +0000 (15:30 -0800)]
i965/fs: Switch from GLSL IR to NIR for un/packHalf2x16 scalarizing.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Thu, 21 Jan 2016 23:46:47 +0000 (15:46 -0800)]
nir: Add lowering of nir_op_unpack_half_2x16.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Thu, 21 Jan 2016 17:30:05 +0000 (09:30 -0800)]
i965: Make separate nir_options for scalar/vector stages.
We'll want to have different lowering options set for scalar/vector
stages.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Thu, 21 Jan 2016 17:19:53 +0000 (09:19 -0800)]
i965: Move brw_compiler_create() to new brw_compiler.c.
A future patch will want to use designated initalizers, which aren't
available in C++, but this is C.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Matt Turner [Thu, 21 Jan 2016 17:54:19 +0000 (09:54 -0800)]
nir: Make argument order of unop_convert match binop_convert.
Strangely the return and parameter types were reversed.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Marta Lofstedt [Tue, 26 Jan 2016 08:48:50 +0000 (09:48 +0100)]
mesa: enable enums for OES_geometry_shader
Enable GL_OES_geometry_shader enums for OpenGL ES 3.1.
V4: EXTRA tokens updated according to comments from Ilia Mirkin.
V5: Account for check_extra does not evaluate "or" lazy. Fix issues
with EXTRA_EXT_FB_NO_ATTACH_CS.
Signed-off-by: Marta Lofstedt <marta.lofstedt@linux.intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
François Tigeot [Sun, 17 Jan 2016 09:10:21 +0000 (10:10 +0100)]
gallium: Add DragonFly support
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Ilia Mirkin [Fri, 29 Jan 2016 23:23:21 +0000 (18:23 -0500)]
nv50/ir: get rid of memory stores with nop values
This happens especially with exports and varying packing, where the last
bits aren't always filled in. We end up trying to do quad-wide stores,
which ends up being a lot of register moves that carefully preserve the
nop value. Instead don't do the stores.
total instructions in shared programs : 6131375 -> 6125267 (-0.10%)
total gprs used in shared programs : 910139 -> 895501 (-1.61%)
total local used in shared programs : 15328 -> 15328 (0.00%)
local gpr inst
helped 0 7442 4693
hurt 0 90 2687
Most of the helped/hurt instruction changes are by one or two ops
because can no longer do quad-wide stores in all cases.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 30 Jan 2016 22:13:33 +0000 (17:13 -0500)]
nv50/ir: fix false global CSE on instructions with multiple defs
If an instruction has multiple defs, we have to do a lot more checks to
make sure that we can move it forward. Among other things, various code
likes to do
a, b = tex()
if () c = a
else c = b
which means that a single phi node will have results pointing at the
same instruction. We obviously can't propagate the tex in this case, but
properly accounting for this situation is tricky. Just don't try for
instructions with multiple defs.
This fixes about 20 shaders in shader-db, including the dolphin efb2ram
shader.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Ilia Mirkin [Sat, 30 Jan 2016 15:02:43 +0000 (10:02 -0500)]
nv50,nvc0: fix buffer clearing to respect engine alignment requirements
It appears that the nvidia render engine is quite picky when it comes to
linear surfaces. It doesn't like non-256-byte aligned offsets, and
apparently doesn't even do non-256-byte strides.
This makes arb_clear_buffer_object-unaligned pass on both nv50 and nvc0.
As a side-effect this also allows RGB32 clears to work via GPU data
upload instead of synchronizing the buffer to the CPU (nvc0 only).
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> # tested on GF108, GT215
Tested-by: Nick Sarnie <commendsarnex@gmail.com> # GK208
Cc: mesa-stable@lists.freedesktop.org
Rob Clark [Wed, 27 Jan 2016 17:05:12 +0000 (12:05 -0500)]
freedreno/ir3: ignore clip-vertex varying
Since we emulate clip-planes, the clip-vertex is used within the VS
itself (thanks to nir_lower_clip). So just ignore it as a VS output.
Fixes a boatload of piglit tests that were asserting on unknown
varying slot.
(Also unrelated spelling/typo fix.)
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sat, 7 Nov 2015 13:46:02 +0000 (08:46 -0500)]
freedreno/ir3: don't ignore local vars
With glsl_to_nir we end up with local variables, instead of global, for
arrays.
Note that we'll eventually have to do something more clever, I think,
when we support multiple functions, but that will probably take some
work in a few places.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 5 Nov 2015 20:38:32 +0000 (15:38 -0500)]
freedreno/ir3: handle tex instrs w/ const offset
Something we start to see with glsl_to_nir.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 5 Nov 2015 18:31:25 +0000 (13:31 -0500)]
freedreno/ir3: support load_front_face intrinsic
With tgsi_to_nir we get this as a normal input with VARYING_SLOT_FACE.
But glsl_to_nir plus nir_lower_system_values this becomes an intrinsic.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Sun, 24 Jan 2016 18:18:39 +0000 (13:18 -0500)]
freedreno: limit string marker to max packet size
Experimentally derived max size.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Sat, 30 Jan 2016 01:28:12 +0000 (20:28 -0500)]
nvc0: avoid crashing when there are holes in vertex array bindings
When using the "shared" vertex array configuration strategy, we bind
each of the buffers as a separate array. However there can be holes in
such vertex buffer lists, so just emit a disable for those.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Ilia Mirkin [Sun, 3 Jan 2016 03:23:44 +0000 (22:23 -0500)]
nvc0: enable atomic counters and ssbo
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sun, 17 Jan 2016 09:34:08 +0000 (04:34 -0500)]
nv50/ir: handle new TGSI MEMBAR opcode
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Mon, 11 Jan 2016 02:47:04 +0000 (21:47 -0500)]
nvc0/ir: fix atomic compare-and-swap arguments
Teach the emitter that the two registers are sequential, and drop the
second arg entirely, in favor of a double-wide first argument.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Tue, 19 Jan 2016 04:34:01 +0000 (23:34 -0500)]
nv50/ir: add support for indirect buffer loading
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Mon, 14 Dec 2015 05:13:34 +0000 (00:13 -0500)]
nv50/ir: add SUQ op by reading the info from driver constbuf
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sun, 3 Jan 2016 03:25:31 +0000 (22:25 -0500)]
nv50/ir: add support for BUFFER accesses
This largely leaves the existing image logic alone. When image support
is added this will have to be harmonized somehow.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Mon, 11 Jan 2016 03:44:32 +0000 (22:44 -0500)]
nvc0: handle shader buffer memory barrier
Issue a MEM_BARRIER. No idea if this is sufficient. As there are no
tests for this, it'll have to do for now.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sun, 3 Jan 2016 03:26:46 +0000 (22:26 -0500)]
nvc0: add state management for shader buffers
(address, length) pairs are uploaded to the driver constbuf as well to
make these values available to the shaders.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sun, 13 Dec 2015 22:07:35 +0000 (17:07 -0500)]
nvc0: double per-shader stage driver constants area
We need to store a lot more info now with per-buffer address/size.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Mon, 9 Nov 2015 12:09:25 +0000 (07:09 -0500)]
trace: add support for set_shader_buffers
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
v1 -> v2: add arg_begin/arg_end around buffer array
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Ilia Mirkin [Mon, 18 Jan 2016 05:13:51 +0000 (00:13 -0500)]
st/mesa: enable ARB_shader_storage_buffer_object when supported
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Mon, 11 Jan 2016 03:39:16 +0000 (22:39 -0500)]
st/mesa: add shader buffer barrier bit
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Sun, 17 Jan 2016 09:32:42 +0000 (04:32 -0500)]
st/mesa: add support for memory barrier intrinsics
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
v1 -> v2: use TGSI_MEMBAR defines
Ilia Mirkin [Mon, 14 Dec 2015 04:04:32 +0000 (23:04 -0500)]
st/mesa: use RESQ to find buffer size
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Ilia Mirkin [Mon, 18 Jan 2016 05:08:24 +0000 (00:08 -0500)]
st/mesa: add support for SSBO binding and GLSL intrinsics
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
v1 -> v2: some 80 char reformatting
Ilia Mirkin [Sat, 20 Sep 2014 00:59:17 +0000 (20:59 -0400)]
st/mesa: add atomic counter support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Mon, 18 Jan 2016 04:57:48 +0000 (23:57 -0500)]
mesa: add PROGRAM_IMMEDIATE, PROGRAM_BUFFER
This makes PROGRAM_IMMEDIATE a first-class gl_register_file type, and
adds PROGRAM_BUFFER to the list. These are used purely inside
glsl_to_tgsi conversion.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Mon, 28 Dec 2015 19:03:50 +0000 (14:03 -0500)]
glsl: keep track of ssbo variable being accessed, add access params
Currently any access params (coherent/volatile/restrict) are being lost
when lowering to the ssbo load/store intrinsics. Keep track of the
variable being used, and bake its access params in as the last arg of
the load/store intrinsics.
If the variable is accessed via an instance block, then 'variable'
points to the instance block variable and not the field inside the
instance block that we are accessing. In order to check access
parameters for the field itself we need to detect this case and keep
track of the corresponding field struct so we can extract the specific
field access information from there instead.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
v1 -> v2: add tracking of struct field
v2 -> v3: minor adjustments based on Iago's feedback
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Ilia Mirkin [Tue, 19 Jan 2016 06:43:40 +0000 (01:43 -0500)]
glsl: always initialize image_* fields, copy them on interface init
Interfaces can have image properties set in case they are buffer
interfaces. Make sure not to lose this information.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Sun, 17 Jan 2016 09:24:49 +0000 (04:24 -0500)]
tgsi: add MEMBAR opcode to handle memoryBarrier* GLSL intrinsics
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
v1 -> v2: add defines for the various bits
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Michel Dänzer [Tue, 26 Jan 2016 07:38:55 +0000 (16:38 +0900)]
winsys/amdgpu: Process RADEON_FLAG_* independently from RADEON_DOMAIN_*
In particular, AMDGPU_GEM_CREATE_CPU_GTT_USWC can affect even BOs created
in VRAM if they get evicted to GTT. In general there's no need to
restrict any of the flags to any particular domains.
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Michel Dänzer [Tue, 26 Jan 2016 07:15:59 +0000 (16:15 +0900)]
winsys/amdgpu: Handle RADEON_FLAG_NO_CPU_ACCESS
Failing to do this was resulting in the kernel driver unnecessarily
leaving open the possibility of CPU access to tiled BOs.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93862
(This change shouldn't be backported to stable branches, because
released versions of xf86-video-amdgpu unnecessarily try to map the
front buffer)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Karol Herbst [Wed, 27 Jan 2016 17:25:08 +0000 (18:25 +0100)]
nv50/ir: optimize mad/fma with third argument 0 to mul
Very modest effect, but it's clearly the right thing to do.
total instructions in shared programs : 6131491 -> 6131398 (-0.00%)
total gprs used in shared programs : 910157 -> 910131 (-0.00%)
total local used in shared programs : 15328 -> 15328 (0.00%)
local gpr inst bytes
helped 0 55 85 85
hurt 0 26 20 20
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Karol Herbst [Wed, 27 Jan 2016 17:25:07 +0000 (18:25 +0100)]
nv50/ir: run DCE backwards
Reduces calls up to 50%
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Karol Herbst [Wed, 27 Jan 2016 17:25:05 +0000 (18:25 +0100)]
nv50/ir: optimize shl(shr(a, c), c) to and(a, ~((1 << c) - 1))
Following shader-db results on GK110:
total instructions in shared programs : 6141510 -> 6131491 (-0.16%)
total gprs used in shared programs : 910187 -> 910157 (-0.00%)
total local used in shared programs : 15328 -> 15328 (0.00%)
local gpr inst bytes
helped 0 18 821 821
hurt 0 0 0 0
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Wed, 27 Jan 2016 18:52:41 +0000 (13:52 -0500)]
glsl: disallow implicit conversions in ESSL shaders
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Axel Davy [Fri, 15 Jan 2016 09:47:42 +0000 (10:47 +0100)]
radeonsi: Add option for SI scheduler
Add a debug option to select the LLVM SI Machine Scheduler.
R600_DEBUG=sisched
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Iglesias Gonsálvez [Tue, 26 Jan 2016 11:47:26 +0000 (12:47 +0100)]
glsl: double-precision values don't support interpolation
ARB_gpu_shader_fp64 spec says:
"This extension does not support interpolation of double-precision
values; doubles used as fragment shader inputs must be qualified as
"flat"."
Fixes the regressions added by commit 781d278:
arb_gpu_shader_fp64-double-gettransformfeedbackvarying
arb_gpu_shader_fp64-tf-interleaved
arb_gpu_shader_fp64-tf-interleaved-aligned
arb_gpu_shader_fp64-tf-separate
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93878
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Eric Anholt [Tue, 26 Jan 2016 18:34:42 +0000 (10:34 -0800)]
vc4: Throttle outstanding rendering after submission.
Just make sure that after we've submitted, we get to at least 5
(global) submits ago before we go on to do more. Prevents up to
seconds of lag with window movement in X with xcompmgr -c. There may
be useful tuning to do in the future, but for now this gets us
usability.
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Eric Anholt [Tue, 26 Jan 2016 18:28:45 +0000 (10:28 -0800)]
vc4: Don't record the seqno of a failed job submit.
On an error return, the returned seqno will probably be unset, so we'd
lose track of what we've submitted so far for waiting on in the
future.
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Ben Widawsky [Tue, 26 Jan 2016 23:44:01 +0000 (15:44 -0800)]
i965/skl: Utilize new 5th bit for gateway messages
Modify comment as spotted by Matt, and Chris Forbes
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Ilia Mirkin [Wed, 27 Jan 2016 18:58:40 +0000 (13:58 -0500)]
glsl: only expose double mod when doubles are available
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Karol Herbst [Tue, 26 Jan 2016 13:36:04 +0000 (14:36 +0100)]
nv50/ir: fix memory corruption when spilling and redoing RA
When RA fails, and we spill, we have to clean everything up before doing
RA again. We were forgetting to reset the hi/lo linked lists - at
least the hi list is guaranteed to still have pointers to now-deleted
RIG nodes.
Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Timothy Arceri [Tue, 26 Jan 2016 05:22:33 +0000 (16:22 +1100)]
glsl: remove old FINISHME
This should have been removed long ago.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Marek Olšák [Tue, 12 Jan 2016 19:08:46 +0000 (20:08 +0100)]
configure.ac: don't require EGL/DRM and GBM if OpenGL is disabled
This allows building VDPAU/OMX/VA drivers without OpenGL and its
dependencies.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Jan Vesely [Thu, 21 Jan 2016 16:17:29 +0000 (11:17 -0500)]
r600,compute: Plug few memory leaks
v2: drop inline keyword
drop radeon_llvm_dispose_kernel_module wrapper
v3: move definitions to .c file
use in radeonsi
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Jan Vesely [Thu, 21 Jan 2016 16:17:28 +0000 (11:17 -0500)]
r600: Typos and whitespace fixes
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 17:52:23 +0000 (18:52 +0100)]
radeonsi: fix clover crash
caused by
ce1e7784d08a14a90e6051915f2622424a54dc6e
Trivial.
Marek Olšák [Sat, 23 Jan 2016 16:00:00 +0000 (17:00 +0100)]
radeonsi: fix shader precompilation for shader-db
The addition of spi_shader_col_format killed all color outputs
in precompiled shaders.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> (v1)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
v2: also set the alpha func (trivial)
Ilia Mirkin [Fri, 22 Jan 2016 18:07:10 +0000 (13:07 -0500)]
glsl: add GL_OES_geometry_point_size and conditionalize gl_PointSize
For now this will be enabled in tandem with GL_OES_geometry_shader.
Should a driver come along that wants to separate them out, another
enable can be added.
Also adds the missed GL_OES_geometry_shader define in glcpp.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marta Lofstedt <marta.lofstedt@intel.com>
Emil Velikov [Mon, 18 Jan 2016 10:16:48 +0000 (12:16 +0200)]
glsl: move to compiler/
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Emil Velikov [Mon, 18 Jan 2016 10:54:03 +0000 (12:54 +0200)]
nir: move to compiler/
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Emil Velikov [Wed, 25 Nov 2015 16:03:26 +0000 (16:03 +0000)]
compiler: move the glsl_types C wrapper alongside their C++ brethren
At a later stage we might want to split out the NIR specific [XXX:
which one was it], as to make things move obvious and rename the files
appropriately. This patch aims to split it out of nir.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Emil Velikov [Mon, 18 Jan 2016 09:35:29 +0000 (11:35 +0200)]
nir: move glsl_types.{cpp,h} to compiler
Allows us to remove the SCons workaround :-)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Emil Velikov [Mon, 18 Jan 2016 08:47:13 +0000 (10:47 +0200)]
nir: move shader_enums.[ch] to compiler
This way one can reuse it in glsl, nir or other infrastructure without
pulling nir as dependency.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Emil Velikov [Mon, 23 Nov 2015 17:03:04 +0000 (17:03 +0000)]
compiler: introduce a libcompiler static library
Currently it's an empty library, although it'll be used to store common
code between GLSL and NIR that is compiler specific (rather than generic
as the one in src/util).
XXX: strictly speaking we could add a python/mako parser to generate the
relevant files instead including builtin_type_macros.h in such a manner.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Nicolai Hähnle [Thu, 21 Jan 2016 21:53:02 +0000 (16:53 -0500)]
gallium/ddebug: add 'verbose' option
This currently just writes out the name of dump files, which can be useful
to easily correlate those files with other log outputs (driver debug output,
apitrace calls, etc.)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 21 Jan 2016 21:46:59 +0000 (16:46 -0500)]
gallium/ddebug: make 'noflush' also affect 'always' mode
This changes the default behavior of 'always' mode to be consistent with
hang detection mode.
I have used this to more easily compare dumped command streams using diff.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>