Rhys Perry [Wed, 26 Oct 2022 20:13:15 +0000 (21:13 +0100)]
aco/gfx11: perform FS input loads in WQM
fossil-db (gfx1100):
Totals from 48184 (35.68% of 135032) affected shaders:
MaxWaves: 1131876 -> 1131960 (+0.01%); split: +0.05%, -0.04%
Instrs:
36755466 ->
36782290 (+0.07%); split: -0.04%, +0.11%
CodeSize:
200812068 ->
200915348 (+0.05%); split: -0.04%, +0.09%
VGPRs: 2163980 -> 2163828 (-0.01%); split: -0.15%, +0.14%
Latency:
484174459 ->
484341018 (+0.03%); split: -0.06%, +0.09%
InvThroughput:
87941284 ->
87944874 (+0.00%); split: -0.04%, +0.04%
VClause: 652984 -> 653085 (+0.02%); split: -0.09%, +0.10%
SClause: 1510995 -> 1528832 (+1.18%); split: -0.40%, +1.58%
Copies: 1997689 -> 2001857 (+0.21%); split: -0.49%, +0.69%
Branches: 676629 -> 676584 (-0.01%); split: -0.02%, +0.01%
PreSGPRs: 2033070 -> 2036725 (+0.18%)
PreVGPRs: 1903922 -> 1903897 (-0.00%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes:
3730be9873d ("aco: mostly implement FS input loads on GFX11")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19370>
Rhys Perry [Thu, 27 Oct 2022 19:32:59 +0000 (20:32 +0100)]
aco: fix typo in branch lowering
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes:
aadb7aef019 ("aco: add VINTERP instruction format")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19370>
Samuel Pitoiset [Thu, 27 Oct 2022 15:11:08 +0000 (17:11 +0200)]
radv: enable VK_EXT_transform_feedback with NGG streamout on GFX11
Untested but it mostly work on GFX10.3.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19435>
Samuel Pitoiset [Tue, 1 Nov 2022 10:20:58 +0000 (11:20 +0100)]
radv: allow to enable NGG streamout with RADV_PERFTEST=ngg_streamout
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19435>
Samuel Pitoiset [Thu, 27 Oct 2022 15:10:35 +0000 (17:10 +0200)]
radv: enable all possible features with NGG streamout
Tested by forcing NGG streamout on GFX10.3.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19435>
Samuel Pitoiset [Tue, 1 Nov 2022 08:11:17 +0000 (09:11 +0100)]
radv: set the correct buffer size for NGG streamout
If the size is passed through CmdBindTransformFeedback() uses that.
This partially fixes dEQP-VK.transform_feedback.simple.multiquery_1
by reporting the correct number of primitives written (the computation
is based on the buffer size). There is still a bug around GDS offsets
that will be fixed later.
Tested on GFX10.3 by forcing NGG streamout.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19433>
Gert Wollny [Sun, 30 Oct 2022 09:20:13 +0000 (10:20 +0100)]
r600/sfn: Handle load_workgroup_size
Fixes:
79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19417>
Samuel Pitoiset [Mon, 31 Oct 2022 12:53:05 +0000 (13:53 +0100)]
radv: fix primitives generated query with NGG only
According to the AMD registers database, SAMPLE_STREAMOUTSTATS no
longer exists on GFX11. This fixes primitives generated query if only
the NGG path is used. Tested on GFX10.3 by forcing NGG everywhere.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19410>
Samuel Pitoiset [Mon, 31 Oct 2022 12:51:00 +0000 (13:51 +0100)]
radv: suspend/resume primitives generated query separately for legacy/NGG
With NGG only, only the GDS query counter will be incremented.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19410>
Samuel Pitoiset [Mon, 31 Oct 2022 12:35:26 +0000 (13:35 +0100)]
radv: use 32-bit GDS counters for primitives generated query with NGG
Do not need to use 64-bit operations.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19410>
Samuel Pitoiset [Mon, 31 Oct 2022 12:29:48 +0000 (13:29 +0100)]
radv: reword an incorrect comment about primitives generated query
This is not the XFB counter.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19410>
Luis Felipe Strano Moraes [Wed, 26 Oct 2022 22:08:22 +0000 (15:08 -0700)]
meson: simplified meson for enabling ray-tracing on Intel
Removed warning about deprecated usage that was not necessary.
Also added information on whether support is enabled or not to the
summary so it is easier to check when building.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19332>
Alyssa Rosenzweig [Sat, 29 Oct 2022 02:46:19 +0000 (22:46 -0400)]
gallium: Default to PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
Supported in all hardware and software drivers. Only that don't support
are virgl and svga, depending on host capabilities. I don't think
there's anything to be done there. This does give fewer places to screw
up the CAPs, though, because everyone wants ARB_buffer_storage.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Ol<C5><A1><C3><A1>k <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19392>
Alyssa Rosenzweig [Sat, 29 Oct 2022 02:40:58 +0000 (22:40 -0400)]
etnaviv: Advertise PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
This CAP only concerns mapping of buffers, not textures. For buffers,
etnaviv does not seem to use any staging resources. In neither case does
etnaviv use explicit syncs or flushes, so persistent/coherent mapping
should come as the implicit default and the cap should be almost free.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19392>
Alyssa Rosenzweig [Sat, 29 Oct 2022 02:39:44 +0000 (22:39 -0400)]
i915g: Advertise PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
Currently buffer_map returns the raw pointer, there is no syncing or
flushing or staging buffers or resource shadowing anywhere. That means
if the driver is currently correct, it is implementing persistent and
coherent behaviour already, so the CAP is trivial.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19392>
Alyssa Rosenzweig [Sat, 29 Oct 2022 02:36:52 +0000 (22:36 -0400)]
softpipe: Advertise PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
It's a software rasterizer, all buffers are necessarily persistent and
coherent. There are no staging buffers in transfer_map and no sync/flush
operations, so this is trivial.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19392>
Frank Binns [Tue, 11 Oct 2022 07:27:28 +0000 (08:27 +0100)]
CODEOWNERS: remove rajnesh-kanwal as an Imagination maintainer
Rajnesh has moved onto other non-graphics things.
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19135>
Nanley Chery [Mon, 10 Oct 2022 21:01:36 +0000 (14:01 -0700)]
iris: Reduce use of RHWO optimization (Wa_1508744258)
Implement Wa_1508744258:
Disable RHWO by setting 0x7010[14] by default except during resolve
pass.
Disable the RCC RHWO optimization at all times except when resolving
single sampled color surfaces. MCS partial resolves are done via
software (i.e., not via a HW bit) and so are not expected to need this
workaround.
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19360>
António Monteiro [Sun, 30 Oct 2022 14:37:33 +0000 (14:37 +0000)]
gallium/util: remove network class
Signed-off-by: António Monteiro <antonio.fmr.monteiro@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19403>
jenneron [Mon, 31 Oct 2022 14:01:36 +0000 (14:01 +0000)]
docs/panfrost: Document Mali-T620 support
This one is already supported
Signed-off-by: Anton Bambura <jenneron@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19415>
Emma Anholt [Mon, 17 Oct 2022 18:46:52 +0000 (11:46 -0700)]
zink: Enable mesa/st frontend shader caching.
This required fixing up the disk cache to hash in stuff that was missing
(like the proper pipeline cache uuid rather than just PCI IDs, and also
zink's build ID). Once we do that, we can just hand the frontend our disk
cache and avoid GLSL->NIR recompiles.
tu asphalt_9 trace perf +3.14859% +/- 1.36891% (n=4)
Fixes: #7513
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19124>
Jesse Natalie [Sat, 29 Oct 2022 14:53:45 +0000 (07:53 -0700)]
d3d12: Advertise PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19396>
Jesse Natalie [Mon, 31 Oct 2022 16:40:45 +0000 (09:40 -0700)]
dzn: Set factory flags before creating device
I got this in d3d12 but missed it in dzn
Fixes:
74d1c72b ("dzn: Support device factories in addition to global device creation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19420>
Konstantin Seurer [Sun, 30 Oct 2022 14:37:04 +0000 (15:37 +0100)]
radv/rt: Set vars.arg in the traversal shader
Fixes: f4270b7 ("radv/rt: create traversal shader independent from main shader")
Closes: #7591
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19402>
Michel Dänzer [Thu, 27 Oct 2022 15:49:35 +0000 (17:49 +0200)]
radeonsi/ci: Test piglit quick_shader profile as well
It's useful for catching regressions, e.g. it would have caught
https://gitlab.freedesktop.org/mesa/mesa/-/issues/7567 .
For the radeonsi-stoney-gl:amd64 job, we can use the "gpu" profile,
which contains quick_gl and quick_shader.
For the radeonsi-raven-piglit-gl:amd64 job, that would almost double
the runtime, and bring it dangerously close to the 30 minutes timeout.
Instead, split it up into radeonsi-raven-piglit-quick_gl:amd64 and
radeonsi-raven-piglit-quick_shader:amd64 jobs.
v2:
* Rebase, drop spec@arb_tessellation_shader@execution flakes and add
one crash instead.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19378>
Rhys Perry [Tue, 25 Oct 2022 14:45:10 +0000 (15:45 +0100)]
radv,aco: don't use lower_to_fragment_fetch_amd on GFX11+
FMask doesn't exist on GFX11. Have txf_ms take the fragment_fetch_amd
path.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19375>
Rhys Perry [Tue, 25 Oct 2022 15:00:10 +0000 (16:00 +0100)]
radv/gfx11: don't create texop_samples_identical
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19375>
Rhys Perry [Tue, 25 Oct 2022 14:55:22 +0000 (15:55 +0100)]
radv/gfx11: don't create fmask copy/expand pipelines
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19375>
Rhys Perry [Tue, 11 Oct 2022 13:00:14 +0000 (14:00 +0100)]
ac/nir: lower gfx11 vertex parameter exports
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19228>
Rhys Perry [Wed, 19 Oct 2022 14:25:51 +0000 (15:25 +0100)]
aco: don't split swizzled store_buffer_amd on GFX9+
This isn't necessary.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19228>
Rhys Perry [Tue, 18 Oct 2022 19:52:53 +0000 (20:52 +0100)]
nir,ac/nir,aco,radv: replace has_input_*_amd with more general intrinsics
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19228>
Samuel Pitoiset [Wed, 26 Oct 2022 13:10:57 +0000 (13:10 +0000)]
radv: do not unconditionally disable NGG streamout lowering in NIR
This is still always disabled because use_ngg_streamout is FALSE
but it will be turned on at some point.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19317>
Samuel Pitoiset [Wed, 26 Oct 2022 12:15:44 +0000 (12:15 +0000)]
radv: lower NIR intrinsics for NGG streamout
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19317>
Samuel Pitoiset [Tue, 25 Oct 2022 07:47:43 +0000 (09:47 +0200)]
radv: call nir_io_add_intrinsic_xfb_info() after IO lowering
This is needed for NGG streamout which gets the XFB info directly
from intrinsics.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19317>
Samuel Pitoiset [Tue, 25 Oct 2022 10:03:18 +0000 (12:03 +0200)]
radv/llvm: prevent emitting streamout outputs for NGG
They are directly emitted from NIR.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19317>
Samuel Pitoiset [Tue, 25 Oct 2022 09:59:42 +0000 (11:59 +0200)]
aco: remove invalid assertions for NGG streamout
Streamout outputs are directly emitted from NIR now.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19317>
Samuel Pitoiset [Tue, 25 Oct 2022 08:49:24 +0000 (10:49 +0200)]
aco: implement NIR intrinsics for NGG streamout
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19317>
Samuel Pitoiset [Tue, 25 Oct 2022 09:30:19 +0000 (11:30 +0200)]
aco: create a new builder variant for ds_add_rtn
This instruction can use 1 definition and 3 operands.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19317>
Bas Nieuwenhuizen [Sun, 30 Oct 2022 15:33:56 +0000 (16:33 +0100)]
radv: Handle attribute ring intrinsic correctly with LLVM.
Again, if we don't set progress to false we get fun stuff.
Fixes:
8bf1aa1b76b ("radv: add lowering for nir_intrinsic_load_ring_attr_{offset}_amd")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19404>
Bas Nieuwenhuizen [Sun, 30 Oct 2022 15:31:04 +0000 (16:31 +0100)]
radv: Handle GSVS ring intrinsic correctly with LLVM.
If we don't set progress to false we get a mess as a replacement is
still attempted.
Fixes:
382831c9865 ("radv,nir: add intrinsics for streamout and GS copy shaders")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19404>
Bas Nieuwenhuizen [Sun, 30 Oct 2022 15:18:15 +0000 (16:18 +0100)]
radv: Use correct types for loading the rings with LLVM.
Ring descriptors are v4i32, not i8.
Fixes:
cb117cdc96c ("radv/llvm: use ac_build_gep0_type to get args types")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19404>
Anton Bambura [Mon, 31 Oct 2022 12:14:20 +0000 (14:14 +0200)]
panfrost: Enable Mali-T620
Support of this GPU is now good enough to enable it
Signed-off-by: Anton Bambura <jenneron@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19408>
Gert Wollny [Wed, 19 Oct 2022 08:03:27 +0000 (10:03 +0200)]
r600: Print MOVA_INT dest on Cayman
On Cayman the index registers can be written too, so print it.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19397>
Gert Wollny [Mon, 10 Oct 2022 16:16:35 +0000 (18:16 +0200)]
r600: Only count ALU registers that are not clause local
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19397>
Gert Wollny [Fri, 7 Oct 2022 14:23:28 +0000 (16:23 +0200)]
r600: declare for counter locally and fix signed/unsigned warning
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19397>
Samuel Pitoiset [Fri, 28 Oct 2022 16:47:07 +0000 (18:47 +0200)]
Revert "radv: add a pointer to radv_shader_binary in radv_shader"
This is actually not necessary because we compile and upload binaries
directly from libraries with GPL. This introduced random double free
crashes because binaries were potentially freed by concurrent threads.
Root cause found by Ishi.
This reverts commit
f8d887527aab641bd291f08850755197b6c2c1d7.
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19383>
Sunil Khatri [Wed, 26 Oct 2022 07:04:02 +0000 (12:34 +0530)]
winsys/amdgpu: clamp up the alignment if zero
Zero alignment buffers is a valid alignment and is
used for the cases when there is no special alignment
enforced due to hardware requirement.
Clamp up the buffer alignment of such buffers to
gart_page_size. Screenshot app uses such buffers
with zero alignment which is returned NULL by winsys
and failed and hence failed to capture.
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19314>
Danylo Piliaiev [Tue, 25 Oct 2022 11:49:32 +0000 (13:49 +0200)]
freedreno/fdl: Increase alignment for UBWC images
From empirical tests (on a660) R8G8 with UBWC enabled requires 256b
alignment, otherwise there would be a GPU fault during blits.
Set alignment to 4096 for all UBWC images since that's what blob does
and this area is heavily undertested.
Fixes GPU fault in Borderlands 3 running through DXVK.
cc: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19298>
Frank Binns [Thu, 20 Oct 2022 17:06:23 +0000 (18:06 +0100)]
pvr: setup buffer and image format feature bits
Note, this also fixes a case where image usage and format feature flags were
being mixed. This was noticed as part of the conversion to format feature 2
flags.
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19372>
Georg Lehmann [Fri, 28 Oct 2022 14:32:12 +0000 (16:32 +0200)]
aco: Use opsel for the third operand.
Foz-DB Navi21:
Totals from 2 (0.00% of 134913) affected shaders:
CodeSize: 7788 -> 7772 (-0.21%)
Instrs: 1305 -> 1303 (-0.15%)
Latency: 7175 -> 7163 (-0.17%)
InvThroughput: 2082 -> 2078 (-0.19%)
Copies: 57 -> 55 (-3.51%)
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19380>
Samuel Pitoiset [Fri, 28 Oct 2022 14:58:52 +0000 (16:58 +0200)]
radv: implement transform feedback queries with NGG streamout
The control bit is written to the upper bits because GDS counters
are 32-bits only, this allows to re-use the existing query shader.
Tested on GFX10.3.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19325>
Tapani Pälli [Fri, 28 Oct 2022 10:06:11 +0000 (13:06 +0300)]
hasvk: remove some unused functions
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19368>
Tapani Pälli [Fri, 28 Oct 2022 10:05:21 +0000 (13:05 +0300)]
anv: remove some unused functions
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19368>
Bas Nieuwenhuizen [Tue, 25 Oct 2022 02:32:55 +0000 (04:32 +0200)]
radv: Speculatively tune RT pipelines for GFX11.
With ACO not supporting VOPD and the high number of SALU instructions,
we're likely better off using wave64 until we can actually benchmark
this and fix these issues.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19288>
Lionel Landwerlin [Sat, 29 Oct 2022 23:24:36 +0000 (02:24 +0300)]
anv: remove shader fp64 inspection after parsing
Unfortunately some crucible tests are using all floating point widths
in a single shader and specializing a variable to select what code
path to use for a particular supported floating point width. This is
reporting errors in the validation layers.
Remove the validation for now.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes
8c4c4c3ee1a2 ("anv: Add softtp64 workaround")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19401>
Yusuf Khan [Thu, 6 Oct 2022 02:38:04 +0000 (21:38 -0500)]
nouveau: enable PIPE_CAP_UMA when appropriate
Signed-off-by: Yusuf Khan <yusisamerican@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18172>
Bas Nieuwenhuizen [Sat, 1 Oct 2022 10:31:47 +0000 (12:31 +0200)]
radv: Use PLOC for BVH building
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>
Bas Nieuwenhuizen [Thu, 29 Sep 2022 09:03:30 +0000 (11:03 +0200)]
radv: Add PLOC shader
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>
Friedrich Vock [Sun, 30 Oct 2022 11:46:44 +0000 (12:46 +0100)]
radv: Add REF as a typename macro to .clang-format
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>
Friedrich Vock [Tue, 25 Oct 2022 15:33:58 +0000 (17:33 +0200)]
radv: Add global sync utilities
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>
Friedrich Vock [Thu, 27 Oct 2022 22:01:51 +0000 (00:01 +0200)]
radv/rt: Track number of inactive leaf nodes
To avoid emitting nodes with only invalid children in PLOC.
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>
Friedrich Vock [Fri, 28 Oct 2022 20:02:07 +0000 (22:02 +0200)]
radv/rt: Dispatch internal converter indirectly
Preparation for using the converter with PLOC.
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>
Friedrich Vock [Fri, 28 Oct 2022 20:01:07 +0000 (22:01 +0200)]
radv/rt: Fix internal converter synchronization
Fixes:
e83e4faf ("radv: Only emit parents from parents that actually end up in the tree.")
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>
Friedrich Vock [Wed, 26 Oct 2022 10:23:04 +0000 (12:23 +0200)]
radv: Add radv_indirect_unaligned_dispatch
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>
Friedrich Vock [Tue, 25 Oct 2022 06:26:06 +0000 (08:26 +0200)]
radv: Use a struct for AABBs
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>
Bas Nieuwenhuizen [Thu, 29 Sep 2022 00:15:39 +0000 (02:15 +0200)]
radv: Make the number of internal nodes be written on the GPU.
Opens the door of algorithms with a variable number of nodes.
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>
Bas Nieuwenhuizen [Wed, 28 Sep 2022 23:40:50 +0000 (01:40 +0200)]
radv: Add BVH IR header.
To include GPU state passed between stages but not in a node.
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>
Friedrich Vock [Tue, 25 Oct 2022 14:10:55 +0000 (16:10 +0200)]
radv: Rename emulated float helpers
Use only conversion functions now.
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19292>
Mauro Rossi [Sat, 29 Oct 2022 10:46:49 +0000 (12:46 +0200)]
util: glsl2spirv.py: ensure '#endif' is printed in new line
Fixes the following building errors:
In file included from ../src/intel/vulkan/anv_pipeline_cache.c:34:
src/intel/vulkan/float64_spv.h:3316:3: error: expected identifier or '('
};#endif // FLOAT64_SPV_H
^
src/intel/vulkan/float64_spv.h:1:2: error: unterminated conditional directive
^
../src/intel/vulkan/anv_pipeline_cache.c:59:17: error: use of undeclared identifier 'anv_shader_bin_serialize'; did you mean 'anv_shader_bin_deserialize'?
.serialize = anv_shader_bin_serialize,
^~~~~~~~~~~~~~~~~~~~~~~~
anv_shader_bin_deserialize
../src/intel/vulkan/anv_pipeline_cache.c:41:1: note: 'anv_shader_bin_deserialize' declared here
anv_shader_bin_deserialize(struct vk_device *device,
^
../src/intel/vulkan/anv_pipeline_cache.c:59:17: error: incompatible pointer types initializing 'bool (*)(struct vk_pipeline_cache_object *, struct blob *)' with an expression of type 'struct vk_pipeline_cache_object *(struct vk_device *, const void *, size_t, struct blob_reader *)' (aka 'struct vk_pipeline_cache_object *(struct vk_device *, const void *, unsigned long, struct blob_reader *)') [-Werror,-Wincompatible-pointer-types]
.serialize = anv_shader_bin_serialize,
^~~~~~~~~~~~~~~~~~~~~~~~
4 errors generated.
Fixes: 9786d9e ("util: Add glsl2spirv.py script")
Reviewed-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19394>
Filip Gawin [Sat, 29 Oct 2022 13:57:36 +0000 (15:57 +0200)]
r300: update r400 tests
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19395>
Mike Blumenkrantz [Fri, 28 Oct 2022 17:54:02 +0000 (13:54 -0400)]
zink: enable renderpass optimizing for turnip jobs
this should catch regressions, at the least
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19077>
Mike Blumenkrantz [Fri, 28 Oct 2022 00:49:43 +0000 (20:49 -0400)]
zink: use tc renderpass tracking to optimize renderpasses
this massively improves performance on tiling gpus
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19077>
Mike Blumenkrantz [Thu, 13 Oct 2022 16:11:29 +0000 (12:11 -0400)]
zink: add a context flag to indicate when blitter is running
...or blitter-like functionality
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19077>
Mike Blumenkrantz [Fri, 14 Oct 2022 15:53:03 +0000 (11:53 -0400)]
util/tc: implement renderpass tracking
this allows tc to track metadata for framebuffer attachments so that
drivers can optimize their renderpasses
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19077>
Mike Blumenkrantz [Fri, 14 Oct 2022 15:48:14 +0000 (11:48 -0400)]
util/tc: split out dsa and fs state cso handling
no functional changes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19077>
Mike Blumenkrantz [Fri, 14 Oct 2022 15:45:39 +0000 (11:45 -0400)]
util/tc: split out flush and deferred flush calls
it's useful to be able to separate these, and deferred flushes can also consume
slightly less memory
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19077>
Jordan Justen [Sat, 29 Oct 2022 18:06:16 +0000 (11:06 -0700)]
ci/d3d12: Update quick_shader results with 24 fixes from !19128
Suggested-by: Jesse Natalie <jenatali@microsoft.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19128>
Francisco Jerez [Mon, 17 Oct 2022 21:05:38 +0000 (14:05 -0700)]
nir/lower_int64: Implement lowering of 64-bit integer to 64-bit float conversions.
This involves computing the significand with a 64-bit precision type,
and implementing the normalization and packing manually instead of
relying on u2f32, since the significand can no longer be represented
as a 32-bit integer. This fixes 64-bit integer to 64-bit float
conversions on devices that support 64-bit float natively but lack
64-bit integer support, like Intel MTL hardware.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> (v1)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19128>
Francisco Jerez [Mon, 17 Oct 2022 21:00:59 +0000 (14:00 -0700)]
nir/lower_int64: Enable lowering of 64-bit float to 64-bit integer conversions.
The existing code for this appears to work okay for conversions
involving 64-bit floats, relax the assert and enable the lowering
path. This fixes 64-bit float to 64-bit integer integer conversions
on devices that have native support for 64-bit floats but lack 64-bit
integer support, like Intel MTL hardware.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19128>
Alyssa Rosenzweig [Mon, 24 Oct 2022 02:21:20 +0000 (22:21 -0400)]
asahi: Identify counts for compute kernels
In the same place as for vertex/fragment.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19265>
Marek Olšák [Sat, 22 Oct 2022 00:30:41 +0000 (20:30 -0400)]
radeonsi: force the MSAA resolve shader to use 1 clause for MSAA loads
LLVM can't keep consecutive loads in a clause.
Using the optimization barrier for sample indices produces the optimal code.
Deduced by trial and error.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19243>
Marek Olšák [Sat, 22 Oct 2022 00:29:31 +0000 (20:29 -0400)]
nir: add nir_intrinsic_optimization_barrier_vgpr_amd for LLVM
We need this for the MSAA resolve shader.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19243>
Alyssa Rosenzweig [Thu, 27 Oct 2022 21:48:02 +0000 (17:48 -0400)]
panfrost: Add lots of perf_debug annotations
Should make it easier to diagnose performance issues in the future.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19358>
Alyssa Rosenzweig [Thu, 27 Oct 2022 20:29:37 +0000 (16:29 -0400)]
panfrost: Enable rendering to 16-bit and 32-bit
Bifrost onwards handle this in hardware, and the Midgard lowering isn't
too terrible. Enable the format, otherwise desktop GL apps such as
Hacknet try to render to the format and get an incomplete framebuffer.
Cc stable because apparently we've been advertising this format
unintentionally as a result of some other interaction? Unclear how
Hacknet is hitting this, maybe it's an app bug. Shrug, it's not a big
deal regardless.
Additionally, we need to restrict texturing from 32-bit normalized due
to a restriction added with the v7 pixel format fiasco. That means
restricting rendering to 32-bit normalized on v7 onwards.
Closes: #7251
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Tested-by: Dang Huynh <danct12@disroot.org>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19358>
Alyssa Rosenzweig [Sat, 29 Oct 2022 17:36:02 +0000 (13:36 -0400)]
panfrost/ci: Disable trace-based testing
Trace-based testing has not worked for Panfrost. It was a neat
experiment, and I'm glad we tried it, but the results have been mostly
negative for the driver. Disable the trace-based tests.
For testing that specific API features work correctly, we run the
conformance tests (dEQP), which are thorough for OpenGL ES. For big GL
features, we run Piglit, and if there are big GL features that we are
not testing adequately, we should extend Piglit for these. For
fine-grained driver correctness, we are already covered.
Where trace-based testing can fit in is as a smoke test, ensuring that
the overall rendering of complex scenes does not regress. In principle,
that's a lovely idea, but the current implementation has not worked out
for Panfrost thus far. The crux of the issue is that the trace based
tests are based on checksums, not fuzzy-compared reference images. That
requires updating checksums any time rendering changes. However, a
rendering change to a trace is NOT a regression. The behaviour of OpenGL
is specified very loosely. For a given trace, there are many different
valid checksums. That means that correct changes to core code frequently
fail CI after running through the rest of CI, only because a checksum
changed in a still correct way. That's a pain to deal with, exacerbated
by rebase pains, and provides negative value to the project. Some recent
examples of this I've hit in the past two weeks alone:
panfrost: Enable rendering to 16-bit and 32-bit
4b49241f7d7 ("panfrost: Use proper formats for pntc varying")
ac2964dfbd1 ("nir: Be smarter fusing ffma")
The last example were virgl traces, but were especially bad: due to a
rebase fail, I had to update traces /twice/, wasting two full runs of
pre-merge CI across *all* hardware. This was extremely wasteful.
The value of trace-based testing is as a smoke test to check that traces
still render correctly. That is useful, but it turns out that checksums
are the wrong way to go about it. A better implementation would be
storing only a single reference image from a software rasterizer per
trace. No driver-specific references would be stored. That reference
image must never change, provided the trace never changes. CI would then
check rendered results against that image with tolerant fuzzy
comparisons. That tolerance matches with the fuzzy comparison that the
human eye would do when investigating a checksum change anyway. Yes, the
image comparison JavaScript will now report that
0 pixels changed within the tolerance, but there's nothing a human eye
can do with that information other than an error prone copypaste of new
checksums back in the yaml file and kicking it back to CI, itself a
waste of time.
Finally, in the time we've had trace-based testing alongside the
conformance tests, I cannot remember a single actual regression in one
of my commits the trace jobs have identified that the conformance tests
have not also identified. By contrast, the conformance test coverage has
prevented the merge of a number of actual regressions, with very few
flakes or xfail changes, and I am grateful we have that coverage. That
means the value added from the trace jobs is close to zero, while the
above checksum issues means that the cost is tremendous, even ignoring
the physical cost of the extra CI jobs.
If you work on trace-based testing and would like to understand how it
could adapted to be useful for Panfrost, see my recommendations above.
If you work on CI in general and would like to improve Panfrost's CI
coverage, what we need right now is not trace-based testing, it's
GLES3.1 conformance runs on MediaTek MT8192 or MT8195. That hardware is
already in the Collabora LAVA lab, but it's not being used for Mesa CI
as the required kernel patches haven't made their way to mainline yet
and nobody has cherry-picked them to the gfx-ci kernel. If you are a
Collaboran and interested in improving Panfrost CI, please ping
AngeloGioacchino for information on which specific patches need to be
backported or cherry-picked to our gfx-ci kernel. Thank you.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19358>
Rob Clark [Fri, 28 Oct 2022 17:22:27 +0000 (10:22 -0700)]
nir: Add way to create passthrough TCS without VS nir
In the case of disk-cache hits, radeonsi no longer has the nir shader
around. So add a way to create a passthrough TCS with just the VS
output locations.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7567
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19382>
Rob Clark [Fri, 28 Oct 2022 20:59:10 +0000 (13:59 -0700)]
docs: Update features.txt
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19388>
Alyssa Rosenzweig [Thu, 9 Jun 2022 13:45:37 +0000 (09:45 -0400)]
gallium: Only use Asahi's software path on macOS
On macOS, we don't have DRM or any real WSI, so Asahi has to pretend to be a
software rasterizer to load. On Linux, we do have DRM and proper WSI, so we
don't want that. For faking Asahi devices on Linux, we should use drm-shim
instead. This makes sure we don't accidentally load Asahi on non-M1 Linux.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15940>
Alyssa Rosenzweig [Thu, 9 Jun 2022 12:50:44 +0000 (08:50 -0400)]
gallium: Stub support for Asahi + DRM
Copy-paste a pile of winsys code from panfrost and find-and-replace the name to
asahi. This should contain all the glue code needed for asahi+kmsro.
The kernel driver is under way (led by Asahi Lina, not me), but it's not
wred up here. My goal was rather to run shader-db, which expects a
render node, which means drm-shim, which means DRM loader support. With
this patch and a trivial drm-shim, shader-db runs.
In general I am reticent to touch UABI related code when the UABI hasn't been
finalized upstream, or started design at all, hence the RFC. Realistically this
patch assumes the following about the future UABI:
0. It will be a DRM driver. This is nonnegotiable.
1. The render node will be named "asahi". The other reasonable name would be
"apple", which I'm using for the display controller (not yet upstream, but
getting close).
2. Display and rendering will be split in the kernel, requiring kmsro in
userspace, as agreed in past discussions.
The 3D accelerator (AGX) and the display controller (DCP) are completely
orthogonal blocks with separate lineages. True, Apple A14 (~= M1) has AGX and
DCP together, and it seems like all the chips that will get upstream support
will have this for the forseeable future. Nevertheless, it's a historical
coincidence. Apple A12 had an AGX block with a pre-DCP Apple display
controller, which would use a completely different display driver. Older SoCs
had a PowerVR block with an Apple shader core, with a pre-DCP Apple display
controller. Even older SoCs had a pure PowerVR block (+ Apple display).
The AGX and DCP kernel drivers are not expected to share any nontrivial code.
We don't gain anything by bundling them together. Likewise, the many
codec blocks are completely orthogonal. This is all standard practice
for Arm SoCs.
It is true that AGX has never been used with a non-Apple display
controller; it is highly unlikely this would change (either by AGX
licensing out or something like Mali-DP getting licensed in). But
an extra kmsro user doesn't actually add more complexity to Mesa, so
shrug.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com> [meson, ack on gallium]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15940>
Gert Wollny [Wed, 26 Oct 2022 20:13:31 +0000 (22:13 +0200)]
r600/sfn: Add .clang-format file and apply style
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19379>
Karol Herbst [Fri, 28 Oct 2022 11:55:17 +0000 (13:55 +0200)]
nir/algebraic: add vec8/16 cmp lowering
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19150>
Karol Herbst [Fri, 28 Oct 2022 11:38:56 +0000 (13:38 +0200)]
nir/algebraic: generalize vector_cmp lowering
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19150>
Karol Herbst [Mon, 17 Oct 2022 23:18:04 +0000 (01:18 +0200)]
nir/algebraic: support CL vector accessors
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19150>
Karol Herbst [Sun, 25 Sep 2022 14:42:15 +0000 (16:42 +0200)]
nir/algebraic: add 8 and 64 bit urol and uror lowering
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19150>
Alyssa Rosenzweig [Thu, 27 Oct 2022 15:23:53 +0000 (11:23 -0400)]
panfrost,asahi: Support ARB_buffer_storage
After a great deal of spec lawyering in #dri-devel, I am convinced this
is probably okay for the same reasons as v3d and freedreno. The batch
reordering and flush deferral optimizations are seemingly still ok. The
requirement that writes are visible "immediately" in the spec actually
means "in the subsequent [OpenGL] command" for the CPU -> GPU direction,
which avoids pitfalls where PERSISTENT|COHERENT could be used as a
"doorbell". With that understanding, the extension doesn't actually
require anything special for tilers other than coherency at GPU submit
boundaries, which is true for any driver that does not use a sync ioctl.
After this commit, the remaining drivers that don't set the CAP are
d3d12, softpipe, etnaviv, and i915g. I am unsure about d3d12, but the
latter 3 could probbaly enable it trivially for the same reason.
v2: Don't use copy_resource path for persistent mappings (Emma). Emma
explained on GitLab:
I don't think you should have the copy_resource path taken for
PIPE_RESOURCE_FLAG_MAP_PERSISTENT BOs. Imagine the user has a
general-purpose BO they're streaming stuff into and doing draws that
they keep persistently mapped until wrapping. They call some GL
function on the same buffer that does a fallback write map on the BO
(u_default_buffer_subdata, util_resource_copy_region, whatever) -- the
buffer is in use, copy triggers, allocates a new BO. Whoops, the user's
pointer for streaming writes is now freed.
Closes: #7570
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19351>
Yusuf Khan [Thu, 27 Oct 2022 06:31:02 +0000 (01:31 -0500)]
gallium/util: add a helper for get_timestamp
Signed-off-by: Yusuf Khan <yusisamerican@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19334>
Rhys Perry [Thu, 27 Oct 2022 11:49:09 +0000 (12:49 +0100)]
aco: insert waitcnt before/after ds_ordered_count
The LLVM backend does this when lowering ordered_xfb_counter_add_amd. I
guess there is some missing dependency checking or something.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19345>
Rhys Perry [Thu, 27 Oct 2022 13:49:31 +0000 (14:49 +0100)]
aco: add storage_gds
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19345>
Emma Anholt [Mon, 17 Oct 2022 21:39:44 +0000 (14:39 -0700)]
zink: Lazily allocate the dummy surfaces.
glmark2 -b texture --fullscreen drops from 141MB of BOs to 85MB on turnip.
Still 29MB more than freedreno (due to a pile of extra fullscreen rgba8
images)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19126>
Emma Anholt [Mon, 17 Oct 2022 22:00:11 +0000 (15:00 -0700)]
zink: No need to use a 2-sample dummy image for bindless without null descs.
This appears to be some leftover copy and paste or something, should be
1-sample just like other dummy usages.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19126>
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