Qiang Yu [Mon, 17 Oct 2022 09:01:35 +0000 (17:01 +0800)]
radeonsi: implement nir_load_ring_gsvs_amd
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
Emma Anholt [Thu, 12 Jan 2023 00:07:05 +0000 (16:07 -0800)]
ci: Enable building the testing drivers with perfetto.
We've talked about being able to capture perfetto traces from CI jobs for
a while, and this would be a step toward that. Mostly it's that we
occasionally break the perfetto build, so let's make sure we don't do
that.
Acked-by: Rob Clark <robdclark@chromium.org>
Acked-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20660>
Emma Anholt [Thu, 12 Jan 2023 00:32:00 +0000 (16:32 -0800)]
freedreno/pps: Fix a signed/unsigned complaint.
../src/freedreno/ds/fd_pps_driver.cc:656:44: error: comparison of integer expressions of different signedness: '__gnu_cxx::__alloc_traits<std::allocator<int>, int>::value_type' {aka 'int'} and 'const unsigned int' [-Werror=sign-compare]
656 | assert(d->assigned_counters[i] < g->num_counters);
cc1plus: all warnings being treated as errors
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20660>
Emma Anholt [Tue, 17 Jan 2023 23:51:36 +0000 (15:51 -0800)]
ci/freedreno: Add glx-swap-event-async as a flake.
It's only happened a few times in the last year (used to be more popular),
but it just took out a merge.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20660>
Emma Anholt [Wed, 18 Jan 2023 00:07:28 +0000 (16:07 -0800)]
freedreno: Skip CPU/GPU timestamp sync when not supported.
Fixes immediate segfaults in perfetto-enabled builds on pre-a6xx.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20660>
Emma Anholt [Tue, 17 Jan 2023 22:01:18 +0000 (14:01 -0800)]
ci/zink: Add more blit conversion xfails for a618.
Popular cases in this group recently:
1 dEQP-GLES3.functional.fbo.blit.conversion.r16ui_to_r16ui
1 dEQP-GLES3.functional.fbo.blit.conversion.r16ui_to_rgb10_a2ui
1 dEQP-GLES3.functional.fbo.blit.conversion.rgb5_a1_to_rgb5_a1
3 dEQP-GLES3.functional.fbo.blit.conversion.rgba4_to_r32f
4 dEQP-GLES3.functional.fbo.blit.conversion.rgb565_to_rgba8
5 dEQP-GLES3.functional.fbo.blit.conversion.rgba4_to_rg16f
There's pretty clearly something common with blitting from 16-bit.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20759>
Emma Anholt [Tue, 17 Jan 2023 21:51:55 +0000 (13:51 -0800)]
ci/iris: Generalize the 8888_pbuffer EGL known flakes and share with GLK.
It seems to be this whole group of tests, on both boards that run EGL
tests by default (aml-y is manual-only). Make them a regex until someone
comes up with a fix.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20759>
Emma Anholt [Tue, 17 Jan 2023 21:51:27 +0000 (13:51 -0800)]
ci/iris: Add known flakes for skqp.
We've had a lot more jobs run since I landed the CI, and these seem to be
the common flakes.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20759>
Emma Anholt [Tue, 17 Jan 2023 21:43:02 +0000 (13:43 -0800)]
ci/llvmpipe: Drop dEQP-EGL.functional.sharing.*.link.7 flakes.
These appear to have been resolved by !20458 -- went from typically
multiple per day to none since then. The link.19 fails to seem to still
happen, though.
Closes: #7759
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20759>
Jason Ekstrand [Mon, 16 Jan 2023 22:03:11 +0000 (16:03 -0600)]
gallium,util: Pull u_indices and u_primconvert back into gallium
This was moved in !13741 but doing so created a link-time dependency
between util and gallium which causes problems for Vulkan drivers.
Meanwhile, having mesa/main depend on gallium is fine now that we don't
have any classic drivers. It's a bit circular but should be harmless.
Fixes:
97ba2f2fd486 ("move util/indices to core util")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8098
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20734>
Ikshwaku Chauhan [Thu, 5 Jan 2023 15:55:00 +0000 (21:25 +0530)]
radeonsi: Fix distortion for yuv422 format for GFX10.
For yuv422 format camera show blur output for GFX10.
Signed-off-by: Ikshwaku Chauhan <ikshwaku.chauhan@amd.com>
Reviewed-by: Marek Olšák marek.olsak@amd.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20610>
Corentin Noël [Tue, 17 Jan 2023 09:33:37 +0000 (10:33 +0100)]
ci/venus: Remove failure now passing
It has been fixed either in the CTS or in llvmpipe itself but this now passes when running
in CI.
We haven't seen it in CI yet as we are only running a subset of the Vulkan CTS.
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20743>
Mike Blumenkrantz [Mon, 9 Jan 2023 18:51:16 +0000 (13:51 -0500)]
zink: prune old swapchains on present
pruning old swapchains is challenging because there's no way to definitively
know when to destroy them without VK_EXT_swapchain_maintenance1 which isn't
supported yet
initially, I handled it by only pruning on shutdown and whenever a new swapchain
was created since those are both safe points, but this leads to scenarios where
a dead swapchain can exist for the entire lifetime of an application
if the swapinterval is changed
to avoid such ballooning, check whether the current swapchain has ever presented
on each present queue and then prune based on this
fixes #7529
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20588>
Emma Anholt [Thu, 12 Jan 2023 18:43:06 +0000 (10:43 -0800)]
dri2: Fix exposing robustness with swkms.
In the original change I noticed that missing robustness on swkms seemed
to be an oversight, since it was enabled on sw-non-kms, so I exposed the
ext based on the underlying pipe query. However it turns out that there
is a dri_screen flag for allowing robust contexts that exists to do error
checking for GLX, which was under an !swkms check. So we would expose the
ext, but then throw an error if you tried to create one.
Fixes:
e6285ea55fb2 ("egl: Replace the robustness DRI2 ext check with a pipe cap query.")
Closes: #8066
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20679>
Jesse Natalie [Tue, 10 Jan 2023 17:19:50 +0000 (09:19 -0800)]
dzn: Remove cmdbuf query 'wait' list
From the Vulkan spec, the WAIT flag on vkCmdCopyQueryPoolResults only
serves to increase the first synchronization scope to include query end
commands, but either way, the synchronization scope only includes
commands that occur earlier in submission order. In other words, we
don't need to enforce queue ordering, a pipeline barrier is all that's
needed.
Fixes deadlocks in the timestamp.misc_tests.two_cmd_buffers_primary test.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
Jesse Natalie [Tue, 10 Jan 2023 16:15:12 +0000 (08:15 -0800)]
dzn: Fix format support checks for storage/uniform texel buffers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
Jesse Natalie [Tue, 10 Jan 2023 00:46:14 +0000 (16:46 -0800)]
dzn: Disable depth when the rasterizer is disabled due to no position output
D3D considers the rasterizer enabled if there's a pixel shader *or* if
depth is enabled, since you can do depth-only rendering. After parsing
shaders, if we find that there was supposed to be a pixel shader, but
we removed it because there was no output position, disable depth too.
Also, store this info in the cache, since we might not even load the
nir shaders if we'd seen this pipeline before.
Fixes dEQP-VK.synchronization.internally_synchronized_objects.pipeline_cache_graphics
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
Jesse Natalie [Tue, 10 Jan 2023 00:45:45 +0000 (16:45 -0800)]
dzn: Add a zeroed zsa state when depth or raster is disabled
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
Jesse Natalie [Tue, 10 Jan 2023 00:44:02 +0000 (16:44 -0800)]
dzn: Always align cached pipeline header size to input element align
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
Jesse Natalie [Mon, 9 Jan 2023 20:43:46 +0000 (12:43 -0800)]
dzn: Support unnormalized coordinate samplers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
Jesse Natalie [Mon, 9 Jan 2023 20:43:16 +0000 (12:43 -0800)]
dzn: Support root signature 1.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
Jesse Natalie [Mon, 9 Jan 2023 20:41:46 +0000 (12:41 -0800)]
dzn: Define a symbol that was present in older D3D headers
D3D12_BARRIER_SYNC_INPUT_ASSEMBLER was renamed to D3D12_BARRIER_SYNC_INDEX_INPUT,
so conditionally define the old name based on the version of the headers that are
being used.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
EmperorPenguin18 [Mon, 16 Jan 2023 01:48:03 +0000 (20:48 -0500)]
v3d: expose more drm formats with SAND128 modifier
Adds four more PIPE_FORMATs that expose BROADCOM_SAND128. This allows mpv
to do hardware decoding on the Raspberry Pi 4.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7944
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20510>
Rob Clark [Sat, 7 Jan 2023 16:01:27 +0000 (08:01 -0800)]
freedreno/a6xx: Rework barrier handling
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
Rob Clark [Sat, 7 Jan 2023 19:28:20 +0000 (11:28 -0800)]
freedreno: Don't re-install a flushed batch
The compute path does this save/restore dance with the current batch, so
various things called to emit state can assume ctx->batch is the current
thing. But during resource tracking, which could have flushed what was
previously the current batch. Fixes a problem that surfaces in the next
patch when we stop just flushing batches for all the barriers.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
Rob Clark [Fri, 6 Jan 2023 15:37:37 +0000 (07:37 -0800)]
freedreno/a6xx: Workaround for no pos/psize
The hw seems unhappy if there are zero outputs from the last geometry
stage. So add a dummy varying as a workaround. Turnip got a similar
workaround in commit
d6d75fcd915 ("tu: Fix hangs for DS with no output")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
Rob Clark [Tue, 3 Jan 2023 22:23:28 +0000 (14:23 -0800)]
freedreno: Fix tracking of enabled SSBOs
Clearing all of the modified bits an relying on OR'ing the needed bits
back in the loop below doesn't quite work out, Because of early continue
if the SSBO has not changed.
Fixes:
0ed053f03d9 ("freedreno: simplify fd_set_shader_buffers(..)")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
Rob Clark [Fri, 6 Jan 2023 19:51:32 +0000 (11:51 -0800)]
freedreno/drm: Remove assert
We can hit this scenario if there is a GPU hang before the userspace
fence writeback happens. Since we have asserts enabled in CI, just
remove this assert.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
Gert Wollny [Tue, 17 Jan 2023 08:31:16 +0000 (09:31 +0100)]
r600/sfn: Do a bit of cleanup with the secondary read port validation
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20739>
Gert Wollny [Tue, 17 Jan 2023 08:03:26 +0000 (09:03 +0100)]
r600/sfn: Fix readport check
We have to take multi-slot instructions into account, and we don't fail
when there are still possible bank swizzle values to be checked.
For clarity also rename the bank swizzle iterator iterator.
Fixes:
79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20739>
Rhys Perry [Wed, 16 Nov 2022 20:08:22 +0000 (20:08 +0000)]
radv/gfx11: expose shaderBufferFloat32AtomicAdd
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
Rhys Perry [Tue, 17 Jan 2023 16:19:58 +0000 (16:19 +0000)]
radv: load ssbo_atomic_fadd descriptor
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
Rhys Perry [Wed, 16 Nov 2022 20:08:07 +0000 (20:08 +0000)]
aco: add support for fp32 addition atomics
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
Rhys Perry [Wed, 16 Nov 2022 20:07:53 +0000 (20:07 +0000)]
ac/llvm: add support for fp32 addition atomics
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
José Roberto de Souza [Mon, 22 Aug 2022 21:12:46 +0000 (14:12 -0700)]
anv: Move anv_device_check_status() code to i915/anv_device.c
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
José Roberto de Souza [Fri, 2 Sep 2022 13:55:22 +0000 (06:55 -0700)]
anv: Split i915 code from anv_batch_chain.c
There is no change in behavior here.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
José Roberto de Souza [Mon, 21 Nov 2022 19:45:21 +0000 (11:45 -0800)]
anv: Export anv_exec_batch_debug() and chain_command_buffers()
This functions will be used by i915 and Xe KMD.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
José Roberto de Souza [Wed, 5 Oct 2022 18:01:32 +0000 (11:01 -0700)]
anv: Start to move i915 specific code from anv_device to i915/anv_device
More code re-organization to separate i915_drm.h specific code from
the rest.
No behavior changes here.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
Gert Wollny [Tue, 17 Jan 2023 11:27:57 +0000 (12:27 +0100)]
virgl: drop the separable flag for cases that can't be handled
The host can't assign more than 32 locations explicitly, and we
exhaust this already when we handle patches and generics. So
drop the separable flag in cases when we have other IO that
uses generated names that will have to be matched by name.
v2: skip tests for VS input and FS outputs
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20738>
Rob Clark [Tue, 17 Jan 2023 16:00:54 +0000 (08:00 -0800)]
freedreno/ci: Add an a618 flake
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20749>
Rob Clark [Tue, 17 Jan 2023 15:28:11 +0000 (07:28 -0800)]
Revert "freedreno/ci: Switch a630 jobs over to manual"
This reverts commit
0cc3701338178bf45f4e6d2d496646b6dec7b297.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20749>
Rob Clark [Tue, 17 Jan 2023 15:27:51 +0000 (07:27 -0800)]
Revert "freedreno/ci: Switch also performance a630 job to manual"
This reverts commit
3be7a28b24256e4bdc4fe4ba6428ef767c7bd287.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20749>
Lionel Landwerlin [Wed, 21 Dec 2022 17:22:46 +0000 (19:22 +0200)]
intel: use a shared UUID with other drivers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20408>
Tapani Pälli [Mon, 16 Jan 2023 11:09:23 +0000 (13:09 +0200)]
intel/compiler: add cpp_std=c++17 when building tests
Otherwise build fails:
"../src/intel/compiler/brw_private.h:40:4: note:
‘std::variant’ is only available from C++17 onwards"
Fixes:
6c194ddd18f ("intel/compiler: Prepare SIMD selection helpers to handle different prog_datas")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20725>
Gert Wollny [Thu, 24 Nov 2022 16:09:42 +0000 (17:09 +0100)]
virgl: Request setting the atomic offset in the range_base
With that NTT can encode the array base of atomic arrays separately
so that the host driver can address the arrays correctly.
Fixes GL-CTS: KHR-Single-GL43.arrays_of_arrays_gl.AtomicUsage
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
Gert Wollny [Thu, 24 Nov 2022 12:26:17 +0000 (13:26 +0100)]
virgl: lower image variable offsets into the intrinsic range_base value
With that we get the correct base offset when accessing image arrays.
This is required if there a various images with different access
specifiers, because only with the correct base offset the host driver is
able to pick the right array.
Fixes GL-CTS: KHR-GL43.shading_language_420pack.binding_image_array
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
Gert Wollny [Thu, 24 Nov 2022 16:08:18 +0000 (17:08 +0100)]
ntt: Make use of the range_base offset when translating atomics in NTT
v2: Unconditionally add teh range base, it is properly initialized.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
Gert Wollny [Thu, 24 Nov 2022 12:23:50 +0000 (13:23 +0100)]
ntt: handle the image intrinsic range_base when translating to TGSI
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
Gert Wollny [Thu, 24 Nov 2022 16:03:38 +0000 (17:03 +0100)]
nir: Add range_base to atomic_counter and an option to use it
Some drivers may encode constant offsets in the instruction, so
make it possible for the drivers to request lowering the atomic
uniform offset into the range_base variable of the intrinsic.
v2: drop patch to use build-in array offset evaluation, it makes
problems with zink, and update the code accordingly
v3: always initialize range base
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
Gert Wollny [Thu, 24 Nov 2022 12:23:06 +0000 (13:23 +0100)]
nir: Add possibility to store image var offset in range_base
Add the intrinsic range_base value to the image intrinsics and add
the option to store the image array offset into range_base instead
of adding it to the image array index if the driver requests it.
v2: Always initialize range_base
v3: fix for bindless intrinsics
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
Jesse Natalie [Sat, 7 Jan 2023 00:37:38 +0000 (16:37 -0800)]
dzn: Use typeless format for creation of depth-only or stencil-only D24S8
When querying capabilities or creating views using a scoped aspect
mask, we want to return the format for the correct single-channel
format, but when actually creating the resource (aspect mask 0),
we want to use the typeless format, since the single-channel formats
don't report multisampling support.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Fri, 6 Jan 2023 22:45:34 +0000 (14:45 -0800)]
dzn: Set MultisampleEnable to enable MSAA lines
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Fri, 6 Jan 2023 21:17:10 +0000 (13:17 -0800)]
dzn: Storage buffer sizes need to be 4-byte-aligned
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 23:39:16 +0000 (15:39 -0800)]
dzn: Support int border colors
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 17:49:25 +0000 (09:49 -0800)]
dzn: Use R24G8_TYPELESS for 24/8 depth resources
This is the same that was already being done for R32G8X24, not sure
why it was missed for R24G8.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 17:22:21 +0000 (09:22 -0800)]
dzn: When changing root signature, dirty descriptors too
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Wed, 4 Jan 2023 21:22:18 +0000 (13:22 -0800)]
dzn: Support alpha blend factor
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Wed, 4 Jan 2023 21:22:10 +0000 (13:22 -0800)]
dzn: Get options13
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 19:30:33 +0000 (11:30 -0800)]
spirv2dxil: Replace not-provided inputs with zero instead of undef
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 19:30:29 +0000 (11:30 -0800)]
spirv2dxil: Allow killing position as an undef varying
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 17:38:17 +0000 (09:38 -0800)]
spirv2dxil: When removing unused inputs, make sure they're actually inputs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 00:01:49 +0000 (16:01 -0800)]
spirv2dxil: For removing unused vars, consider the whole I/O var size
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 19:02:57 +0000 (11:02 -0800)]
microsoft/compiler: Set num_components to 4 when updating pos write instructions
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 18:36:27 +0000 (10:36 -0800)]
microsoft/compiler: Use nir info.fs.uses_sample_shading to force sample-rate
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 18:19:29 +0000 (10:19 -0800)]
microsoft/compiler: Re-work the logic for adding SV_SampleIndex to force sample-rate
Only add SV_SampleIndex if there exists a sample-rate var that has either flat
interpolation or centroid (and therefore can't force sample rate implicitly),
unless there is also a sample-rate var that doesn't have those properties.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 00:01:12 +0000 (16:01 -0800)]
microsoft/compiler: Always emit float types in the I/O signature for structs
There's VK tests that have mismatching interpolation specifiers between FS
and the previous stage. For structs, that resulted in different types, which
breaks DXIL validation.
We could link the shaders and have that overwrite the interpolation field from
the previous shader, but we could also just not care and always use float.
I don't see any regressions from that.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 00:00:44 +0000 (16:00 -0800)]
microsoft/compiler: Remove arrays when testing for structs in I/O
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Wed, 4 Jan 2023 23:06:54 +0000 (15:06 -0800)]
microsoft/compiler: Implement texture sample count query
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Wed, 4 Jan 2023 22:52:35 +0000 (14:52 -0800)]
microsoft/compiler: Lower pack_[u/s]norm_2x16
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Simon Fels [Thu, 29 Sep 2022 09:32:44 +0000 (11:32 +0200)]
virgl/vtest: allow socket being specified by env variable
Signed-off-by: Simon Fels <simon.fels@canonical.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20736>
Simon Fels [Thu, 29 Sep 2022 09:33:37 +0000 (11:33 +0200)]
venus: allow vtest socket being specified by env variable
Signed-off-by: Simon Fels <simon.fels@canonical.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20736>
Illia Polishchuk [Mon, 16 Jan 2023 07:36:36 +0000 (09:36 +0200)]
hasvk: Add extra memory types for hasvk driver instead of a single one
Replicates a fix from Anv.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7360
Tested-by: Matti Hämäläinen <ccr@tnsp.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20720>
Illia Polishchuk [Fri, 13 Jan 2023 18:54:44 +0000 (20:54 +0200)]
ANV: Add extra memory types for ANV driver instead of a single one
Some game engines can't handle single type well
And Intel on Windows uses 3 types so it's better to add extra one here
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7360
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20693>
Dave Airlie [Wed, 11 Jan 2023 01:02:26 +0000 (11:02 +1000)]
ci: bump vk cts to 1.3.3.1 + and a crash fix.
With the video changes some crashes were introduced in CTS,
apply the fix.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20629>
Thong Thai [Mon, 16 Jan 2023 16:05:14 +0000 (11:05 -0500)]
gallium/auxiliary/vl: clean-up progressive shader
Add the progressive shader to the vl_compositor_cs_cleanup_shaders
function.
Signed-off-by: Thong Thai <thong.thai@amd.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8086
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8088
Tested-by: Mark Herbert <mark.herbert42@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20730>
Alyssa Rosenzweig [Thu, 27 Oct 2022 02:51:06 +0000 (22:51 -0400)]
pan/mdg: Remove MSGS debug
These should all be unreachable and what's left is dead-code.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19350>
Alyssa Rosenzweig [Thu, 27 Oct 2022 02:43:32 +0000 (22:43 -0400)]
pan/mdg: Scalarize LUT instructions in NIR
Simpler. Small shaderdb regressions from using IR registers instead of
SSA, but that's probably what we needed for correctness (given that SSA
is violated otherwise) hence the Cc.
total instructions in shared programs: 1520220 -> 1518127 (-0.14%)
instructions in affected programs: 167437 -> 165344 (-1.25%)
helped: 662
HURT: 206
helped stats (abs) min: 1.0 max: 46.0 x̄: 3.65 x̃: 2
helped stats (rel) min: 0.18% max: 22.22% x̄: 2.43% x̃: 1.71%
HURT stats (abs) min: 1.0 max: 7.0 x̄: 1.56 x̃: 1
HURT stats (rel) min: 0.17% max: 8.33% x̄: 2.66% x̃: 2.33%
95% mean confidence interval for instructions value: -2.65 -2.18
95% mean confidence interval for instructions %-change: -1.45% -0.99%
Instructions are helped.
total bundles in shared programs: 649844 -> 649345 (-0.08%)
bundles in affected programs: 59278 -> 58779 (-0.84%)
helped: 577
HURT: 249
helped stats (abs) min: 1.0 max: 39.0 x̄: 1.56 x̃: 1
helped stats (rel) min: 0.26% max: 30.00% x̄: 3.13% x̃: 2.19%
HURT stats (abs) min: 1.0 max: 12.0 x̄: 1.61 x̃: 1
HURT stats (rel) min: 0.58% max: 25.00% x̄: 5.25% x̃: 4.00%
95% mean confidence interval for bundles value: -0.78 -0.43
95% mean confidence interval for bundles %-change: -0.98% -0.23%
Bundles are helped.
total quadwords in shared programs: 1136767 -> 1134956 (-0.16%)
quadwords in affected programs: 141780 -> 139969 (-1.28%)
helped: 744
HURT: 311
helped stats (abs) min: 1.0 max: 9.0 x̄: 3.13 x̃: 2
helped stats (rel) min: 0.14% max: 26.67% x̄: 2.77% x̃: 2.13%
HURT stats (abs) min: 1.0 max: 8.0 x̄: 1.68 x̃: 1
HURT stats (rel) min: 0.35% max: 10.00% x̄: 3.17% x̃: 1.69%
95% mean confidence interval for quadwords value: -1.89 -1.54
95% mean confidence interval for quadwords %-change: -1.27% -0.77%
Quadwords are helped.
total registers in shared programs: 90461 -> 90273 (-0.21%)
registers in affected programs: 2833 -> 2645 (-6.64%)
helped: 250
HURT: 82
helped stats (abs) min: 1.0 max: 2.0 x̄: 1.08 x̃: 1
helped stats (rel) min: 6.67% max: 33.33% x̄: 14.06% x̃: 12.50%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 6.67% max: 50.00% x̄: 13.90% x̃: 12.50%
95% mean confidence interval for registers value: -0.67 -0.47
95% mean confidence interval for registers %-change: -8.62% -5.69%
Registers are helped.
total threads in shared programs: 55685 -> 55686 (<.01%)
threads in affected programs: 76 -> 77 (1.32%)
helped: 20
HURT: 17
helped stats (abs) min: 1.0 max: 2.0 x̄: 1.30 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
HURT stats (abs) min: 1.0 max: 2.0 x̄: 1.47 x̃: 1
HURT stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: -0.47 0.52
95% mean confidence interval for threads %-change: 5.81% 56.35%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 1387 -> 1379 (-0.58%)
spills in affected programs: 283 -> 275 (-2.83%)
helped: 5
HURT: 1
total fills in shared programs: 5256 -> 5176 (-1.52%)
fills in affected programs: 557 -> 477 (-14.36%)
helped: 5
HURT: 1
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19350>
Alyssa Rosenzweig [Fri, 13 Jan 2023 17:30:00 +0000 (12:30 -0500)]
pan/mdg: Use special NIR ops for trig scaling
Otherwise the lowering is fundamentally unsound due to incorrect constant
folding, even though it worked by chance with the old pass ordering. We're about
to change slightly the way we handle fsin/fcos, which was enough to trigger this
unsoundness.
shader-db results are mostly a toss-up.
total instructions in shared programs: 1520675 -> 1520220 (-0.03%)
instructions in affected programs: 96841 -> 96386 (-0.47%)
helped: 397
HURT: 3
helped stats (abs) min: 1.0 max: 4.0 x̄: 1.15 x̃: 1
helped stats (rel) min: 0.22% max: 6.25% x̄: 1.15% x̃: 0.40%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 0.58% max: 2.08% x̄: 1.08% x̃: 0.58%
95% mean confidence interval for instructions value: -1.19 -1.08
95% mean confidence interval for instructions %-change: -1.26% -1.01%
Instructions are helped.
total bundles in shared programs: 650088 -> 649844 (-0.04%)
bundles in affected programs: 31132 -> 30888 (-0.78%)
helped: 229
HURT: 23
helped stats (abs) min: 1.0 max: 4.0 x̄: 1.21 x̃: 1
helped stats (rel) min: 0.49% max: 7.14% x̄: 1.28% x̃: 0.71%
HURT stats (abs) min: 1.0 max: 3.0 x̄: 1.48 x̃: 1
HURT stats (rel) min: 0.83% max: 8.33% x̄: 2.38% x̃: 1.85%
95% mean confidence interval for bundles value: -1.08 -0.86
95% mean confidence interval for bundles %-change: -1.15% -0.74%
Bundles are helped.
total quadwords in shared programs: 1137388 -> 1136767 (-0.05%)
quadwords in affected programs: 71826 -> 71205 (-0.86%)
helped: 367
HURT: 17
helped stats (abs) min: 1.0 max: 8.0 x̄: 1.80 x̃: 1
helped stats (rel) min: 0.31% max: 17.24% x̄: 2.27% x̃: 0.96%
HURT stats (abs) min: 1.0 max: 6.0 x̄: 2.29 x̃: 2
HURT stats (rel) min: 0.44% max: 11.11% x̄: 2.18% x̃: 1.47%
95% mean confidence interval for quadwords value: -1.76 -1.47
95% mean confidence interval for quadwords %-change: -2.36% -1.78%
Quadwords are helped.
total registers in shared programs: 90483 -> 90461 (-0.02%)
registers in affected programs: 890 -> 868 (-2.47%)
helped: 67
HURT: 44
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 8.33% max: 25.00% x̄: 10.52% x̃: 9.09%
HURT stats (abs) min: 1.0 max: 2.0 x̄: 1.02 x̃: 1
HURT stats (rel) min: 9.09% max: 50.00% x̄: 31.15% x̃: 33.33%
95% mean confidence interval for registers value: -0.39 -0.01
95% mean confidence interval for registers %-change: 1.75% 10.25%
Inconclusive result (value mean confidence interval and %-change mean confidence interval disagree).
total threads in shared programs: 55694 -> 55685 (-0.02%)
threads in affected programs: 21 -> 12 (-42.86%)
helped: 1
HURT: 5
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
HURT stats (abs) min: 2.0 max: 2.0 x̄: 2.00 x̃: 2
HURT stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: -2.79 -0.21
95% mean confidence interval for threads %-change: -89.26% 39.26%
Inconclusive result (%-change mean confidence interval includes 0).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19350>
Alyssa Rosenzweig [Fri, 13 Jan 2023 17:33:24 +0000 (12:33 -0500)]
nir: Optimize vendored sin/cos the same way
As we've done for the AMD one, to prevent any codegen regression from switching
the Midgard lowering.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19350>
Alyssa Rosenzweig [Fri, 13 Jan 2023 17:29:14 +0000 (12:29 -0500)]
nir: Add Midgard-specific fsin/fcos ops
NIR has a fsin instruction that takes an argument in radians. Midgard instead
has an fsinpi argument that takes an argument in multiples of pi. So, we had a
NIR pass that would change fsin(x) to fsin(x / pi) and then map fsin to fsinpi
in the backend.
But that's invalid! In NIR, the opcode fsin is well-defined. fsin(x) means
something very different than fsin(x / pi). They won't usually be equal. The
transform fsin(x) -> fsin(x / pi) is fundamentally unsound.
It did work before, by accident. Most NIR passes don't care about the semantics
of ALU instructions. fsin(x) and fsin(x / pi) are both well-defined but
fundamentally different NIR shaders. So while rewriting is wrong -- the NIR we
get out is not equivalent to the NIR we put in, and the Midgard ops we generate
are not equivalent to the NIR -- but if we don't run any passes that care about
the definition of fsin the two wrongs will cancel out to make a right.
However, some NIR passes do care about the definitions of ALU instructions,
instead of treating them as named black boxes. In particular, constant folding
(nir_opt_constant_fold) evaluates ALU instructions when their inputs are
constants, according to the definition in nir_opcodes.py. So our little charade
will only work if we don't call nir_opt_constant_fold, or if all the fsin
instructions have non-constant inputs. At the beginning of this series, that is
the case. With the later scalarization change, that's no longer the case, and
the unsoundness translates to real failing tests rather than a quibble of NIR's
semantics.
To mitigate, we define a new NIR opcode with the semantics we want and translate
fsin(x) = fsin_mdg(x / pi), where that equivalence does hold mathematically. So
the new translation is sound and doesn't rely on lucky pass ordering.
This matches the approach already used for AMD and AGX, which have fsin_amd and
fsin_agx opcodes respectively.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19350>
Pavel Ondračka [Wed, 5 Oct 2022 19:22:05 +0000 (21:22 +0200)]
r300: remove backend input range transformation for sin and cos
We already do this in NIR since
a04aa4bc08df2c3772fc7dda6766f76ef3a5dfb4
and
3f97306b956f707d637da6b76dd9465fcabfc451 so there is no effect
for the mesa state tracker now that it can not emit TGSI any more.
This leaves only nine when RADEON_DEBUG=use_tgsi is set. D3D9 however
requires that sin and cos inputs already have the proper range.
This is super important when the nine shader uses relative adressing
and therefore needs all 256 constants we have. If we add our extra
constants for the fixup, we get over the limit and fail compilation.
v2: vertex shaders only
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18933>
Pavel Ondračka [Mon, 16 Jan 2023 09:48:42 +0000 (10:48 +0100)]
r300: skip sin/cos input range transformation for nine and ntt
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18933>
Pavel Ondračka [Thu, 12 Jan 2023 10:21:11 +0000 (11:21 +0100)]
r300: update rv515 ci failures list
This fix missed in
421bf657bf33200b1aa97d7ae887971e561ef556 where it was
updated only for R480.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20666>
Timur Kristóf [Sat, 6 Aug 2022 07:40:44 +0000 (09:40 +0200)]
aco/optimizer: Optimize p_extract + v_mul_u32_u24 to v_mad_u32_u16.
This should perform the same but removes SDWA from the address
calculations in NGG culling shaders for example.
This is done because SDWA is no longer available on GFX11.
Fossil DB stats on GFX1100:
Totals from 36 (0.03% of 134913) affected shaders:
CodeSize: 300968 -> 300884 (-0.03%); split: -0.04%, +0.01%
Instrs: 60955 -> 60863 (-0.15%); split: -0.15%, +0.00%
Latency: 426809 -> 426819 (+0.00%); split: -0.06%, +0.06%
InvThroughput: 39076 -> 39025 (-0.13%); split: -0.14%, +0.01%
VClause: 1440 -> 1443 (+0.21%)
Copies: 5714 -> 5725 (+0.19%)
Fossil DB stats on GFX1100 with NGG culling enabled:
Totals from 60953 (45.18% of 134913) affected shaders:
VGPRs: 2273172 -> 2273160 (-0.00%)
CodeSize:
186401864 ->
186403036 (+0.00%); split: -0.00%, +0.00%
Instrs:
37038048 ->
36977353 (-0.16%); split: -0.16%, +0.00%
Latency:
146466770 ->
146350172 (-0.08%); split: -0.08%, +0.00%
InvThroughput:
15342790 ->
15228585 (-0.74%); split: -0.74%, +0.00%
VClause: 669662 -> 669665 (+0.00%)
Copies: 2972380 -> 2972482 (+0.00%); split: -0.01%, +0.01%
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17924>
Timur Kristóf [Mon, 9 Jan 2023 19:57:05 +0000 (20:57 +0100)]
aco/optimizer: Add missing v_lshlrev condition to can_apply_extract.
This was already handled by apply_extract but missing from
can_apply_extract, therefore may not be properly applied everywhere.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17924>
Adam Jackson [Wed, 11 Jan 2023 18:40:34 +0000 (13:40 -0500)]
wsi/x11: Support depth 16 visuals
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7846
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20673>
Adam Jackson [Fri, 13 Jan 2023 19:24:50 +0000 (14:24 -0500)]
wsi/x11: Infer the default surface format from the root window's visual
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20673>
Adam Jackson [Wed, 11 Jan 2023 18:37:11 +0000 (13:37 -0500)]
wsi/x11: Make get_sorted_vk_formats handle varying channel widths
Depths 24 and 30 happen to have uniform bpc but 16 does not. Pull the
real channel width out of the format description instead. This is still
a bit ignorant of channel order though.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20673>
Rhys Perry [Tue, 13 Dec 2022 15:08:58 +0000 (15:08 +0000)]
ac/nir: use store_buffer_amd's base index
This allows ACO to combine the addition into the store without checking
for wraparound.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20296>
Rhys Perry [Mon, 5 Dec 2022 19:11:42 +0000 (19:11 +0000)]
aco: restore semantic_can_reorder for GS output stores
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20296>
Rhys Perry [Mon, 5 Dec 2022 17:32:15 +0000 (17:32 +0000)]
radv,aco: use ac_nir_lower_legacy_gs
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20296>
Rhys Perry [Mon, 5 Dec 2022 17:28:51 +0000 (17:28 +0000)]
radv: implement GS load_ring_gsvs_amd/load_ring_gs2vs_offset_amd
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20296>
Alyssa Rosenzweig [Fri, 13 Jan 2023 01:57:38 +0000 (20:57 -0500)]
panfrost: Document render_condition_check contract
This was implicit before, leading to the bug fixed in the previous commit.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20689>
Alyssa Rosenzweig [Fri, 13 Jan 2023 01:56:23 +0000 (20:56 -0500)]
panfrost: Fix clears with conditional rendering
batch can be invalidated by the render condition check.
Fixes nv_conditional_render-clear.
Fixes:
638b22354e7 ("panfrost: Clear with a quad to avoid flushing")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20689>
Alyssa Rosenzweig [Sat, 14 Jan 2023 02:05:43 +0000 (21:05 -0500)]
panfrost: Remove unused debug parameter
We removed this path.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20707>
Alyssa Rosenzweig [Sat, 14 Jan 2023 01:57:50 +0000 (20:57 -0500)]
panfrost: Remove PAN_MESA_DEBUG=deqp
Now unused.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20707>
Alyssa Rosenzweig [Sat, 14 Jan 2023 01:56:57 +0000 (20:56 -0500)]
panfrost: Stop testing CAP_INT16
This doesn't look like it'll be fixed any time soon. No point running dEQP with
different flags than production, IMO.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20707>
Lucas Stach [Fri, 6 Jan 2023 18:14:18 +0000 (19:14 +0100)]
etnaviv: don't drop TS capability on GPUs with MMUv2
Currently etnaviv disables TS on all MC1.0 GPUs, since the TS unit
doesn't properly take into account the linear window offset with
MC1.0, creating address aliases on MMUv1 that aren't properly dealt
with.
MMUv2 however doesn't have a linear window, so we can safely enable
TS on those GPUs.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20552>
Juston Li [Mon, 24 Oct 2022 20:03:56 +0000 (20:03 +0000)]
util/fossilize_db: add runtime RO foz db loading via FOZ_DBS_DYNAMIC_LIST
Add a new environment varible
MESA_DISK_CACHE_READ_ONLY_FOZ_DBS_DYNAMICE_LIST that specifies a text
file containing a list of RO fossilize caches to load. The list file
is modifiable at runtime to allow for loading RO caches after
initialization unlike MESA_DISK_CACHE_READ_ONLY_FOZ_DBS.
The implementation spawns an updater thread that uses inotify to monitor
the list file for modifications, attempting to load new foz dbs added to
the list. Removing files from the list will not evict a loaded cache.
MESA_DISK_CACHE_READ_ONLY_FOZ_DBS_DYNAMIC_LIST takes an absolute path.
The file must exist at initialization for updating to occur.
File names of foz dbs in the list file are new-line separated and take
relative paths to the default cache directory like
MESA_DISK_CACHE_READ_ONLY_FOZ_DBS.
The maximum number of RO foz dbs is kept to 8 and is shared between
MESA_DISK_CACHE_READ_ONLY_FOZ_DBS_DYNAMIC_LIST and
MESA_DISK_CACHE_READ_ONLY_FOZ_DBS.
The intended use case for this feature is to allow prebuilt caches
to be downloaded and loaded asynchronously during app runtime.
Prebuilt caches be large (several GB) and depending on network
conditions would otherwise present extended wait time for caches
to be availible before app launch.
This will be used in Chrome OS.
Signed-off-by: Juston Li <justonli@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19328>
Juston Li [Mon, 31 Oct 2022 18:55:22 +0000 (18:55 +0000)]
utils/fossilize_db: refactor out loading RO foz dbs
Move loading of RO foz dbs into its own load_ro_foz_dbs() function
Signed-off-by: Juston Li <justonli@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19328>