xingyu.wu [Sat, 7 May 2022 03:10:44 +0000 (11:10 +0800)]
drivers:timer:Fix warning by checkpatch.pl
Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
andy.hu [Sat, 7 May 2022 02:11:30 +0000 (02:11 +0000)]
Merge branch 'CR_942_SPI_warning_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'
dts:starfive: Fix spi and qspi compilation warning
See merge request sdk/sft-riscvpi-linux-5.10!50
xingyu.wu [Fri, 6 May 2022 07:52:26 +0000 (15:52 +0800)]
dts:starfive: Fix spi and qspi compilation warning
Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
andy.hu [Sat, 7 May 2022 01:27:56 +0000 (01:27 +0000)]
Merge branch 'CR_939_PWMDAC_curry.zhang' into 'jh7110_fpga_dev_5.15'
[Audio: PWMDAC] Adjust code style
See merge request sdk/sft-riscvpi-linux-5.10!55
curry.zhang [Fri, 6 May 2022 09:44:30 +0000 (02:44 -0700)]
[Audio: PWMDAC] Adjust code style
Signed-off-by: curry.zhang <curry.zhang@starfivetech.com>
andy.hu [Fri, 6 May 2022 13:51:43 +0000 (13:51 +0000)]
Merge branch 'CR_941_PWM_hal.feng' into 'jh7110_fpga_dev_5.15'
pwm: pwm-starfive-ptc: Fix compiler warnings and improve coding style
See merge request sdk/sft-riscvpi-linux-5.10!54
Hal Feng [Fri, 6 May 2022 08:54:54 +0000 (16:54 +0800)]
pwm: pwm-starfive-ptc: Fix compiler warnings and improve coding style
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
andy.hu [Fri, 6 May 2022 11:59:09 +0000 (11:59 +0000)]
Merge branch 'CR_937_DRM_keith.zhao' into 'jh7110_fpga_dev_5.15'
DTS:DRM
See merge request sdk/sft-riscvpi-linux-5.10!53
andy.hu [Fri, 6 May 2022 11:57:40 +0000 (11:57 +0000)]
Merge branch 'CR_930_V4L2_changhuang.liang' into 'jh7110_fpga_dev_5.15'
V4L2: fixed code warning!
See merge request sdk/sft-riscvpi-linux-5.10!52
andy.hu [Fri, 6 May 2022 11:56:06 +0000 (11:56 +0000)]
Merge branch 'CR_938_PDM_warning_walker.chen' into 'jh7110_fpga_dev_5.15'
Audio PDM: remove warning message and clean up code
See merge request sdk/sft-riscvpi-linux-5.10!51
andy.hu [Fri, 6 May 2022 11:55:29 +0000 (11:55 +0000)]
Merge branch 'CR_907_GPU_shanlong.li' into 'jh7110_fpga_dev_5.15'
driver:GPU: fix compile warnings
See merge request sdk/sft-riscvpi-linux-5.10!48
andy.hu [Fri, 6 May 2022 09:40:50 +0000 (09:40 +0000)]
Merge branch 'CR_940_PCIE_mason.huo' into 'jh7110_fpga_dev_5.15'
PCI: plda: Fix kernel compile warnings
See merge request sdk/sft-riscvpi-linux-5.10!49
shanlong.li [Fri, 6 May 2022 06:47:08 +0000 (23:47 -0700)]
driver:GPU: fix compile warnings
fix compile warnings
Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
andy.hu [Fri, 6 May 2022 09:07:07 +0000 (09:07 +0000)]
Merge branch 'CR_935_pinctrl_warning_jianlong' into 'jh7110_fpga_dev_5.15'
fix warning about pinctrl-starfive-jh7110.c
See merge request sdk/sft-riscvpi-linux-5.10!47
keith.zhao [Fri, 6 May 2022 08:52:09 +0000 (01:52 -0700)]
DTS:DRM
fix build warning in drm dts node
Signed-off-by: keith <keith.zhao@statfivetech.com>
jianlonghuang [Fri, 6 May 2022 08:40:01 +0000 (16:40 +0800)]
modify code format base on checkpatch.pl
Signed-off-by: jianlonghuang <jianlong.huang@starfivetech.com>
Walker Chen [Fri, 6 May 2022 08:30:03 +0000 (16:30 +0800)]
Audio PDM: remove warning message and clean up code
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
changhuang.liang [Fri, 6 May 2022 08:07:52 +0000 (16:07 +0800)]
V4L2: fixed code warning!
V4L2: add m31 dphy reset support!
dts/starfive: add m31 dphy reset configure!
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
andy.hu [Fri, 6 May 2022 08:03:21 +0000 (08:03 +0000)]
Merge branch 'CR_858_SEC_william.qiu' into 'jh7110_fpga_dev_5.15'
Cr 858 sec william.qiu
See merge request sdk/sft-riscvpi-linux-5.10!46
mason.huo [Fri, 6 May 2022 07:35:59 +0000 (15:35 +0800)]
PCI: plda: Fix kernel compile warnings
Remove the unused functions.
Adjust the dts configuration.
Signed-off-by: mason.huo <mason.huo@starfivetech.com>
jianlonghuang [Fri, 6 May 2022 05:43:40 +0000 (13:43 +0800)]
fix warning about pinctrl-starfive-jh7110.c
Signed-off-by: jianlonghuang <jianlong.huang@starfivetech.com>
william.qiu [Thu, 5 May 2022 09:15:27 +0000 (17:15 +0800)]
dt-bingings:crypto: add dma support for crypto.
add dma support for crypto, so it can choose cpu/dma boot.
Signed-off-by: william.qiu <william.qiu@starfivetech.com>
william.qiu [Thu, 5 May 2022 06:26:08 +0000 (14:26 +0800)]
crypto:starfive:fix format problem
Fix the problem that some parameters in the header file are not aligned
Signed-off-by: william.qiu <william.qiu@starfivetech.com>
andy.hu [Thu, 5 May 2022 13:59:58 +0000 (13:59 +0000)]
Merge branch 'CR_875_SPDIF_curry.zhang' into 'jh7110_fpga_dev_5.15'
[Audio: SPDIF] Add standard system clock tree API
See merge request sdk/sft-riscvpi-linux-5.10!42
andy.hu [Thu, 5 May 2022 13:59:35 +0000 (13:59 +0000)]
Merge branch 'CR_738_PWMDAC_curry.zhang' into 'jh7110_fpga_dev_5.15'
[Audio: PWMDAC] Add clock tree and modify driver for 7110 platform
See merge request sdk/sft-riscvpi-linux-5.10!39
andy.hu [Thu, 5 May 2022 13:58:54 +0000 (13:58 +0000)]
Merge branch 'CR_874_I2S_curry.zhang' into 'jh7110_fpga_dev_5.15'
[Audio] I2S and WM8960
See merge request sdk/sft-riscvpi-linux-5.10!40
andy.hu [Thu, 5 May 2022 13:40:05 +0000 (13:40 +0000)]
Merge branch 'CR_850_TDM_Walker.Chen' into 'jh7110_fpga_dev_5.15'
Cr 850 tdm walker.chen
See merge request sdk/sft-riscvpi-linux-5.10!43
curry.zhang [Wed, 4 May 2022 06:13:49 +0000 (23:13 -0700)]
[Audio: PWMDAC] Add standard system clock tree api
Signed-off-by: curry.zhang <curry.zhang@starfivetech.com>
WalkerChenL [Thu, 5 May 2022 10:14:31 +0000 (18:14 +0800)]
Audio:tdm: Add clock/reset/pinctrl initialization
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
andy.hu [Thu, 5 May 2022 13:24:02 +0000 (13:24 +0000)]
Merge branch 'CR_878_SBI_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'
spi: Add clock, reset and pinctrl
See merge request sdk/sft-riscvpi-linux-5.10!41
andy.hu [Thu, 5 May 2022 13:10:57 +0000 (13:10 +0000)]
Merge branch 'CR_868_USB-HOST_yanhong.wang' into 'jh7110_fpga_dev_5.15'
Cr 868 usb host yanhong.wang
See merge request sdk/sft-riscvpi-linux-5.10!44
andy.hu [Thu, 5 May 2022 12:58:57 +0000 (12:58 +0000)]
Merge branch 'CR_849_PDM_Walker.Chen' into 'jh7110_fpga_dev_5.15'
Cr 849 pdm walker.chen
See merge request sdk/sft-riscvpi-linux-5.10!45
Walker Chen [Thu, 5 May 2022 12:16:58 +0000 (20:16 +0800)]
Audio pdm: add clock/reset/pinctrl initialization
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
yanhong.wang [Thu, 5 May 2022 09:23:58 +0000 (17:23 +0800)]
usb:cdns3:cdns3-starfive: Add StarFive wrapper driver for CDNS USB3 controller
Add driver to handle StarFive specific wrapper for Cadence USB3 controller
present on JH7110 SoC.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
yanhong.wang [Thu, 5 May 2022 09:18:39 +0000 (17:18 +0800)]
dt-bingings:usb: Add usb device node
Add usb device node configuration for JH7110 SoC platform.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
curry.zhang [Thu, 5 May 2022 08:47:47 +0000 (01:47 -0700)]
[Audio: SPDIF] Add standard system clock tree API
Signed-off-by: curry.zhang <curry.zhang@starfivetech.com>
xingyu.wu [Thu, 5 May 2022 07:31:51 +0000 (15:31 +0800)]
spi: Add clock, reset and pinctrl
driver:spi: Add reset handle.
dts:starfive:dtsi: Add clock and reset node.
dts:starfive:pinctrl: Modify spi gpio and Add pinctrl.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
curry.zhang [Wed, 4 May 2022 08:03:41 +0000 (01:03 -0700)]
[Audio] I2S and WM8960
1) Add standard system clock tree API
2) Modify wm8960 and I2S drivers
Signed-off-by: curry.zhang <curry.zhang@starfivetech.com>
andy.hu [Fri, 29 Apr 2022 12:36:28 +0000 (12:36 +0000)]
Merge branch 'CR_833_VDEC_samin.guo' into 'jh7110_fpga_dev_5.15'
pmu:starfive:jh7110: Fix some errors and standardize variable naming
See merge request sdk/sft-riscvpi-linux-5.10!38
samin [Fri, 29 Apr 2022 07:29:14 +0000 (15:29 +0800)]
pmu:starfive:jh7110: Fix some errors and standardize variable naming
Fixed interrupt enabler logic error, fixed PMU_HARD_EVENT definition
error, changed some variable names, for better code style.
Note:
This is an interim version of the pmu driver that provides the
power_domian switch function.
It can be used in modules such as VPU/JPU/GPU/ISP/VOUT.
/* do not upstram */
Signed-off-by: samin <samin.guo@starfivetech.com>
andy.hu [Thu, 28 Apr 2022 13:04:03 +0000 (13:04 +0000)]
Merge branch 'CR_907_GPU_shanlong.li' into 'jh7110_fpga_dev_5.15'
Cr 907 gpu shanlong.li
See merge request sdk/sft-riscvpi-linux-5.10!37
andy.hu [Thu, 28 Apr 2022 11:48:10 +0000 (11:48 +0000)]
Merge branch 'CR_873_HIFI4_henry.qin' into 'jh7110_fpga_dev_5.15'
Cr 873 hifi4 henry.qin
See merge request sdk/sft-riscvpi-linux-5.10!31
andy.hu [Thu, 28 Apr 2022 11:38:27 +0000 (11:38 +0000)]
Merge branch 'CR_845_FPGA-V1.0-VIN_update_changhuang.liang' into 'jh7110_fpga_dev_5.15'
Cr 845 fpga v1.0 vin update changhuang.liang
See merge request sdk/sft-riscvpi-linux-5.10!35
andy.hu [Thu, 28 Apr 2022 11:35:45 +0000 (11:35 +0000)]
Merge branch 'CR_737_CLOCK_TREE_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'
clk:starfive: Add isp clock tree driver
See merge request sdk/sft-riscvpi-linux-5.10!32
shanlong.li [Wed, 27 Apr 2022 11:06:17 +0000 (04:06 -0700)]
driver:GPU: add gpu driver
add gpu driver
use clk/rst api and pmu api
Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
shanlong.li [Wed, 27 Apr 2022 11:04:37 +0000 (04:04 -0700)]
driver:pmu : add turn off mask api
add turn off mask api
Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
andy.hu [Thu, 28 Apr 2022 11:01:41 +0000 (11:01 +0000)]
Merge branch 'CR_858_SEC_william.qiu' into 'jh7110_fpga_dev_5.15'
disable sec drvier
See merge request sdk/sft-riscvpi-linux-5.10!36
henry.qin [Thu, 28 Apr 2022 05:36:45 +0000 (13:36 +0800)]
HIFI4: Add hifi4 clk and rst, del unused code, resolve code review
problems, change file access mode.
Signed-off-by: henry.qin <henry.qin@starfivetech.com>
william.qiu [Thu, 28 Apr 2022 10:25:09 +0000 (18:25 +0800)]
crypto:starfive: disable crypto default on fpga.
For most fpga bitfile has no crypto, so disable it for better linux boot.
Signed-off-by: william.qiu <william.qiu@starfivetech.com>
xingyu.wu [Thu, 28 Apr 2022 10:18:17 +0000 (18:18 +0800)]
clk:starfive: Add definition instead of numbers
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
xingyu.wu [Wed, 27 Apr 2022 07:49:49 +0000 (15:49 +0800)]
clk:starfive: Add isp clock tree driver
Clock references refer to include/dt-bindings/clock/starfive-jh7110-isp.h
Enable the isp clock tree driver in dts file if use it.
If the fpga is not connetted with isp board, the isp clock tree must be disabled.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
shanlong.li [Wed, 27 Apr 2022 11:02:06 +0000 (04:02 -0700)]
driver:GPU: add gpu config
add gpu config
Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
shanlong.li [Wed, 27 Apr 2022 10:57:25 +0000 (03:57 -0700)]
dt-bingings:GPU: add clk/rst single
add clk/rst single
Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
andy.hu [Thu, 28 Apr 2022 07:29:42 +0000 (07:29 +0000)]
Merge branch 'CR_846_FPGA-V1.0-VOUT_update_keith.zhao' into 'jh7110_fpga_dev_5.15'
riscv:linux:driver:DC8200
See merge request sdk/sft-riscvpi-linux-5.10!33
andy.hu [Thu, 28 Apr 2022 07:24:53 +0000 (07:24 +0000)]
Merge branch 'CR_858_SEC_william.qiu' into 'jh7110_fpga_dev_5.15'
Cr 858 sec william.qiu
See merge request sdk/sft-riscvpi-linux-5.10!34
william.qiu [Wed, 27 Apr 2022 11:18:11 +0000 (19:18 +0800)]
crypto:starfive:jh7110: add crypto driver for starfive jh7110 soc.
add crypto driver for starfive jh7110 soc.
Signed-off-by: william.qiu <william.qiu@starfivetech.com>
william.qiu [Wed, 27 Apr 2022 07:34:02 +0000 (15:34 +0800)]
crypto:starfive: Write the security clock tree and reset description file
Write the security clock tree and reset description file
Signed-off-by: william.qiu <william.qiu@starfivetech.com>
william.qiu [Wed, 27 Apr 2022 09:05:03 +0000 (17:05 +0800)]
defconfig: add crypto defconfig support.
add defconfig for jh7110 crypto.
Signed-off-by: william.qiu <william.qiu@starfivetech.com>
william.qiu [Wed, 27 Apr 2022 10:04:03 +0000 (18:04 +0800)]
dt-bingings:crypto: add crypto node for jh7110 soc.
add support for jh7110 crypto.
Signed-off-by: william.qiu <william.qiu@starfivetech.com>
william.qiu [Wed, 27 Apr 2022 09:57:36 +0000 (17:57 +0800)]
dmaengine:pl080: add support for starfive jh7110 soc sec.
dd support for starfive jh7110 soc sec.
Signed-off-by: william.qiu <william.qiu@starfivetech.com>
william.qiu [Wed, 27 Apr 2022 09:03:14 +0000 (17:03 +0800)]
crypto: add patch for 5.15
crypto need this patch to work.
Signed-off-by: william.qiu <william.qiu@starfivetech.com>
andy.hu [Thu, 28 Apr 2022 01:10:43 +0000 (01:10 +0000)]
Merge branch 'CR_880_MBX_shanlong.li' into 'jh7110_fpga_dev_5.15'
Cr 880 mbx shanlong.li
See merge request sdk/sft-riscvpi-linux-5.10!25
changhuang.liang [Wed, 27 Apr 2022 15:08:16 +0000 (23:08 +0800)]
v4l2: add isp clk tree support
v4l2: delete isp top clk configure
riscv:dts:starfive: vin add isp clk handle
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
keith.zhao [Wed, 27 Apr 2022 14:45:33 +0000 (22:45 +0800)]
riscv:linux:driver:DC8200
for DC8200 drm driver,update clk reset pinctrl and syscon api
Signed-off-by: keith.zhao<keith.zhao@statfivetech.com>
changhuang.liang [Mon, 25 Apr 2022 08:24:44 +0000 (16:24 +0800)]
V4L2: clk and reset use bulk get
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
changhuang.liang [Thu, 21 Apr 2022 07:41:13 +0000 (15:41 +0800)]
v4l2: mipi channel add reset control suppurt
changhuang.liang [Tue, 19 Apr 2022 02:16:29 +0000 (10:16 +0800)]
v4l2: external modules resource use ioremap
changhuang.liang [Mon, 18 Apr 2022 11:38:38 +0000 (19:38 +0800)]
v4l2: sc2235 sensor use pinctrl set power
changhuang.liang [Sat, 16 Apr 2022 06:42:30 +0000 (14:42 +0800)]
v4l2: add sys clk tree support
changhuang.liang [Sat, 16 Apr 2022 05:48:40 +0000 (13:48 +0800)]
v4l2: add reset control support
changhuang.liang [Sat, 16 Apr 2022 01:53:16 +0000 (09:53 +0800)]
dts: modify sc2235 name
changhuang.liang [Sat, 16 Apr 2022 01:47:58 +0000 (09:47 +0800)]
v4l2: add pinctrl support
changhuang.liang [Sat, 16 Apr 2022 01:08:40 +0000 (09:08 +0800)]
v4l2: fixed sys_crg ioremap error!
shanlong.li [Mon, 25 Apr 2022 11:42:22 +0000 (04:42 -0700)]
e24:driver: add e24 drever , use clk/rst api ,syscon spi
add e24 drever, use clk/rst api, syscon spi
Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
shanlong.li [Mon, 25 Apr 2022 11:36:08 +0000 (04:36 -0700)]
dt-bingings:e24: add e24 devicetree, use clk/rst/syscon.
add e24 devicetree, use clk/rst/syscon.
Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
shanlong.li [Mon, 25 Apr 2022 11:29:36 +0000 (04:29 -0700)]
mailbox:starfive: use clk/rst API.
1) use clk/rst api
2) fix coding style.
Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
shanlong.li [Mon, 25 Apr 2022 11:25:50 +0000 (04:25 -0700)]
dt-bingings:mailbox: Add clk/rst single.
Add clk/rst single for mailbox.
Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
andy.hu [Mon, 25 Apr 2022 10:11:34 +0000 (10:11 +0000)]
Merge branch 'CR_854_RTC_hal.feng' into 'jh7110_fpga_dev_5.15'
rtc: starfive: Use stardand clock and reset apis for initialization
See merge request sdk/sft-riscvpi-linux-5.10!30
andy.hu [Mon, 25 Apr 2022 10:10:23 +0000 (10:10 +0000)]
Merge branch 'CR_853_TRNG_hal.feng' into 'jh7110_fpga_dev_5.15'
Cr 853 trng hal.feng
See merge request sdk/sft-riscvpi-linux-5.10!29
andy.hu [Mon, 25 Apr 2022 10:09:25 +0000 (10:09 +0000)]
Merge branch 'CR_871_PWM_hal.feng' into 'jh7110_fpga_dev_5.15'
Cr 871 pwm hal.feng
See merge request sdk/sft-riscvpi-linux-5.10!28
Hal Feng [Wed, 20 Apr 2022 14:25:31 +0000 (22:25 +0800)]
rtc: starfive: Use stardand clock and reset apis for initialization
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
andy.hu [Mon, 25 Apr 2022 02:19:57 +0000 (02:19 +0000)]
Merge branch 'CR_786_CAN_clivia.cai' into 'jh7110_fpga_dev_5.15'
Cr 786 can clivia.cai
See merge request sdk/sft-riscvpi-linux-5.10!24
andy.hu [Mon, 25 Apr 2022 01:56:54 +0000 (01:56 +0000)]
Merge branch 'CR_886_I2C_hal.feng' into 'jh7110_fpga_dev_5.15'
riscv: dts: starfive: Add clock and reset for i2c
See merge request sdk/sft-riscvpi-linux-5.10!27
Hal Feng [Fri, 22 Apr 2022 07:05:40 +0000 (15:05 +0800)]
riscv: dts: starfive: Add clock and reset for i2c
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng [Thu, 21 Apr 2022 07:58:44 +0000 (15:58 +0800)]
hw_random: starfive-trng: Use stardand clock and reset apis for initialization
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng [Thu, 21 Apr 2022 06:57:10 +0000 (14:57 +0800)]
hw_random: starfive-trng: Follow linux coding style
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
andy.hu [Sun, 24 Apr 2022 13:55:18 +0000 (13:55 +0000)]
Merge branch 'CR_877_Timer_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'
risv:dts:starfive:Add timer clocktree
See merge request sdk/sft-riscvpi-linux-5.10!26
Hal Feng [Wed, 20 Apr 2022 03:46:57 +0000 (11:46 +0800)]
pwm: pwm-starfive-ptc: Use standard clock, reset, pinctrl framework for initialization
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng [Wed, 20 Apr 2022 03:31:58 +0000 (11:31 +0800)]
riscv: dts: starfive: Fix string mismatch problem of ptc (pwm)
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng [Wed, 20 Apr 2022 02:51:14 +0000 (10:51 +0800)]
pwm: pwm-starfive-ptc: Follow linux coding style
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
xingyu.wu [Sun, 24 Apr 2022 13:27:33 +0000 (21:27 +0800)]
risv:dts:starfive:Add timer clocktree
1.Modify the clock tree driver to make timer clock ignore disabled_unused.
2.Add different 'clock-frequency' node in fpga, evb and visionfive dts file.
Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
samin.guo [Sun, 24 Apr 2022 13:44:57 +0000 (09:44 -0400)]
Update ipms-can.yaml
andy.hu [Sun, 24 Apr 2022 11:12:29 +0000 (11:12 +0000)]
Merge branch 'CR_865_GMAC_yanhong.wang' into 'jh7110_fpga_dev_5.15'
Cr 865 gmac yanhong.wang
See merge request sdk/sft-riscvpi-linux-5.10!23
andy.hu [Sun, 24 Apr 2022 10:54:47 +0000 (10:54 +0000)]
Merge branch 'CR_872_PCIE_mason.huo' into 'jh7110_fpga_dev_5.15'
Cr 872 pcie mason.huo
See merge request sdk/sft-riscvpi-linux-5.10!15
andy.hu [Sun, 24 Apr 2022 10:53:29 +0000 (10:53 +0000)]
Merge branch 'CR_785_PCIE_mason.huo' into 'jh7110_fpga_dev_5.15'
Cr 785 pcie mason.huo
See merge request sdk/sft-riscvpi-linux-5.10!13
Clivia.Cai [Sun, 24 Apr 2022 06:35:09 +0000 (23:35 -0700)]
dt-bingings:can:Add syscon register config
Add the syscon register config for can/canfd dt-bindings.
In addition, Redefine some attribute names.
Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
Clivia.Cai [Sun, 24 Apr 2022 10:19:52 +0000 (03:19 -0700)]
dt-bingings:can:Modify reference
Modify the reference of ipmscanx to canx
Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
Clivia.Cai [Sun, 24 Apr 2022 06:31:39 +0000 (23:31 -0700)]
dt-bindings:net:can:ipms-can: update ipms-can.yaml references
Update CAN/CANFD binding documentation for jh7110 SoC.
Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
Clivia.Cai [Sun, 24 Apr 2022 06:15:25 +0000 (23:15 -0700)]
can:ipms_can: Driver code optimization
Use the syscon framework to manage the syscon registers.
In addition, Use devm_reset_control_array_get_exclusive API to manage a list of reset controllers
Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
mason.huo [Sat, 23 Apr 2022 02:07:56 +0000 (10:07 +0800)]
riscv: dts: jh7110: Fix syscon indentation issue
Remove additional tabs of syscon configurations.
Signed-off-by: mason.huo <mason.huo@starfivetech.com>
projects / platform / kernel / linux-starfive.git / log