Scott D Phillips [Fri, 5 Jan 2018 18:52:27 +0000 (10:52 -0800)]
.gitignore: Ignore new generated files
New generated files from:
bb1e6ff161c ("spirv: Add a prepass to set types on vtn_values")
65fc16c9741 ("autotools: set XA versions in configure.ac and configure header file")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Dylan Baker [Tue, 9 Jan 2018 01:43:45 +0000 (17:43 -0800)]
Meson: ensure variable defined
A gallium driver is undefined if passing -Dgallium-drivers=''
Fixes:
e0b037d6979b2 ("meson: Build SWR driver")
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Dylan Baker [Tue, 9 Jan 2018 01:31:55 +0000 (17:31 -0800)]
meson: Fix typo in clover build
The leading space breaks things.
fixes:
42ea0631f108d ("meson: build clover")
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Dylan Baker [Fri, 8 Dec 2017 23:29:59 +0000 (15:29 -0800)]
meson: set opencl flags for r600
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Dylan Baker [Fri, 8 Dec 2017 23:26:00 +0000 (15:26 -0800)]
meson: build clover
This has only been compile tested.
v2: - Have a single option for opencl (Eric E)
- fix typo "tgis" -> "tgsi" (Curro)
- Don't add "lib" to pipe loader libraries, which matches the
autotools behavior
v3: - Remove trailing whitespace
- Make PIPE_SEARCH_DIR an absolute path
v4: - add trailing / to LIBCLC defines
Acked-by: Curro Jerez <currojerez@riseup.net>
Tested-by: Jan Vesely <jan.vesely@rutgers.edu>
cc: Aaron Watry <awatry@gmail.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Dylan Baker [Thu, 30 Nov 2017 01:53:54 +0000 (17:53 -0800)]
meson: Turn on swr for relevant targets
Currently that's dri, libgl-xlib, and osmesa.
v2: - put drivers on a separate line from normal dependencies (Eric E)
cc: George Kyriazis <george.kyriazis@intel.com>
cc: Tim Rowley <timothy.o.rowley@intel.com>
cc: Bruce Cherniak <bruce.cherniak@intel.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Thu, 30 Nov 2017 01:50:05 +0000 (17:50 -0800)]
meson: Build SWR driver
This enables the SWR driver, but doesn't actually hook it up to any of
the targets yet. I felt like this patch was big and complicated enough
without adding that.
v2: - Fix typo 'delemeited' -> 'delimited' (Eric E)
- Fix type 'errror' -> 'error' (Eric E)
- Use variables to hold files instead of looking above the current
meson build (Eric E)
- Use foreach loops to reduce the number of unique generators
- Add comment about why some generators have names and some are just
added to a list
v3: - Remove trailing whitespace
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Timothy Arceri [Mon, 8 Jan 2018 06:41:24 +0000 (17:41 +1100)]
ac: rework emit_barrier() to not segfault on radeonsi
nir_to_llvm_context will always be NULL for radeonsi so we need
work around this.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Mon, 11 Dec 2017 05:16:30 +0000 (16:16 +1100)]
ac: add load_tess_level() to the abi
Fixes the following piglit tests in radeonsi:
vs-tcs-tes-tessinner-tessouter-inputs-quads.shader_test
vs-tcs-tes-tessinner-tessouter-inputs-tris.shader_test
vs-tes-tessinner-tessouter-inputs-quads.shader_test
vs-tes-tessinner-tessouter-inputs-tris.shader_test
v2: make use of si_shader_io_get_unique_index_patch()
via the helper in the previous patch rather than
shader_io_get_unique_index()
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Mon, 11 Dec 2017 03:48:41 +0000 (14:48 +1100)]
radeonsi: add load_tess_level() helper
This will be shared by the tgsi and nir backends.
v2: move si_shader_io_get_unique_index_patch() call inside
the helper.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Jason Ekstrand [Wed, 3 Jan 2018 17:26:18 +0000 (09:26 -0800)]
spirv: Do implicit conversions of uint to bool in OpStore
Technically, the GLSLang bug related to this can also affect SSBO writes
where the bool -> uint conversion is missing. However, the only known
shipping application with an old enough version of GLSLang to cause
issues with this is the new DOOM game so we keep the workaround as small
as possible.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104424
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 2 Jan 2018 04:00:02 +0000 (20:00 -0800)]
spirv: Loosen the validation for load/store type matching
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104338
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104424
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 3 Jan 2018 17:05:31 +0000 (09:05 -0800)]
spirv: Require a storage type for OpStore destinations
This rules out things such as trying to store a pointer to a local
variable.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 2 Jan 2018 15:45:42 +0000 (07:45 -0800)]
spirv: Add a vtn_types_compatible helper
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 3 Jan 2018 16:41:42 +0000 (08:41 -0800)]
spirv: Store the id of the type in vtn_type
Previously, we were storing a pointer to the vtn_value because we use it
to look up decorations when we create input/output variables. This
works, but it also may be useful to have the id itself so we may as well
store that instead.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 2 Jan 2018 03:55:33 +0000 (19:55 -0800)]
spirv: Add a mechanism for dumping failing shaders
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 12 Dec 2017 17:44:59 +0000 (09:44 -0800)]
spirv: Rework asserts in var_decoration_cb
Now that higher levels are enforcing decoration sanity, we don't need
the vtn_asserts here. This function *should* be safe but we still want
a few well-placed regular asserts in case something goes awry.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 12 Dec 2017 16:47:56 +0000 (08:47 -0800)]
spirv: Rework error checking for decorations
This reworks the error checking on our generic handling of decorations.
The objective is to validate all of the SPIR-V assumptions we make
up-front and convert redundant checks to compiled-out asserts. The most
important part of this is to ensure that member decorations only occur
on OpTypeStruct and that the member is never out-of-bounds. This way
later code can assume that the member is sane and not have to worry
about OOB array access due to a misplaced OpMemberDecorate.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 12 Dec 2017 07:03:58 +0000 (23:03 -0800)]
spirv: Add better type validation to OpTypeImage
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 12 Dec 2017 06:42:26 +0000 (22:42 -0800)]
spirv: Switch on vtn_base_type in OpComposite(Extract|Insert)
This is a bit simpler since we have fewer enum values in the case. It's
also a bit more efficient because we're making fewer glsl_get_* calls.
While we're at it, add better type validation.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 12 Dec 2017 06:25:09 +0000 (22:25 -0800)]
spirv: Refactor Op[Spec]ConstantComposite and add better validation
Now that vtn_base_type is a real and full base type, we can switch on
that instead of the GLSL base type which is a lot fewer cases in our
switch.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 12 Dec 2017 06:15:04 +0000 (22:15 -0800)]
spirv: Add better validation to Op[Spec]Constant
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 12 Dec 2017 06:13:33 +0000 (22:13 -0800)]
spirv: Remove a pointless assignment in SpvOpSpecConstant
We re-assign later inside the bit_size switch
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 12 Dec 2017 06:09:02 +0000 (22:09 -0800)]
spirv: Unify boolean constants and add better validation
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 12 Dec 2017 06:04:04 +0000 (22:04 -0800)]
spirv/info: Add spirv_op_to_string
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 12 Dec 2017 05:52:22 +0000 (21:52 -0800)]
spirv: Make 'info' a local array spirv_info_c.py
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 12 Dec 2017 05:42:34 +0000 (21:42 -0800)]
spirv: Add better error messages in vtn_value helpers
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Caio Marcelo de Oliveira Filho [Mon, 8 Jan 2018 18:46:16 +0000 (10:46 -0800)]
spirv: Import 1.2 rev 3 headers and grammar from Khronos
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Samuel Pitoiset [Fri, 5 Jan 2018 18:18:13 +0000 (19:18 +0100)]
radv: get InstanceID from VGPR1 (or VGPR2 for tess) instead of VGPR3
VGPR1 = InstanceID / StepRate0; // StepRate0 can be set to 1
Ported from RadeonSI.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 5 Jan 2018 17:20:06 +0000 (18:20 +0100)]
radv: avoid PS partial flushes when viewports/scissors don't change
For Vega10 and Raven that need a special workaround for the
scissor bug.
This seems to give a minor boost for Talos and Dota 2, at least.
To reduce the cost of memcmp, the driver checks if it's
really useful to do the comparison.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 5 Jan 2018 17:00:31 +0000 (18:00 +0100)]
radv: add has_scissor_bug for Vega10 and Raven
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 5 Jan 2018 16:18:52 +0000 (17:18 +0100)]
radv/gfx9: do not load VGPR1 when GS uses points or lines
VGPR1 is only needed for topology that needs 3 offsets like
triangles or quads.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 4 Jan 2018 14:19:47 +0000 (15:19 +0100)]
radv: make shader BOs read-only for the GPU
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 5 Dec 2017 13:22:17 +0000 (14:22 +0100)]
radv: make descriptor BOs read-only for the GPU
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 5 Dec 2017 13:20:50 +0000 (14:20 +0100)]
radv: make the indirect GFX config BO read-only for the GPU
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 5 Dec 2017 13:28:46 +0000 (14:28 +0100)]
radv/winsys: make IBs read-only for the GPU
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 5 Dec 2017 12:57:07 +0000 (13:57 +0100)]
radv/winsys: add RADEON_FLAG_READ_ONLY
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 5 Dec 2017 12:51:46 +0000 (13:51 +0100)]
radv/winsys: rework radv_amdgpu_bo_va_op()
Needed for the following commit.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Igor Gnatenko [Mon, 1 Jan 2018 21:49:00 +0000 (22:49 +0100)]
link mesautil with pthreads
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `u_thread_setname':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:66: undefined reference to `pthread_setname_np'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `thrd_join':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../include/c11/threads_posix.h:336: undefined reference to `pthread_join'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `u_thread_create':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:48: undefined reference to `pthread_sigmask'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `thrd_create':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../include/c11/threads_posix.h:296: undefined reference to `pthread_create'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `u_thread_create':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:50: undefined reference to `pthread_sigmask'
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:50: undefined reference to `pthread_sigmask'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `call_once':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../include/c11/threads_posix.h:96: undefined reference to `pthread_once'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function `u_thread_get_time_nano':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:84: undefined reference to `pthread_getcpuclockid'
collect2: error: ld returned 1 exit status
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Igor Gnatenko <ignatenko@redhat.com>
Alex Smith [Fri, 5 Jan 2018 11:09:19 +0000 (11:09 +0000)]
anv: Allow PMA optimization to be enabled in secondary command buffers
This was never enabled in secondary buffers because hiz_enabled was
never set to true for those.
If the app provides a framebuffer in the inheritance info when beginning
a secondary buffer, we can determine if HiZ is enabled and therefore
allow the PMA optimization to be enabled within the command buffer.
This improves performance by ~13% on an internal benchmark on Skylake.
v2: Use anv_cmd_buffer_get_depth_stencil_view().
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Florian Will [Fri, 5 Jan 2018 14:33:31 +0000 (15:33 +0100)]
glsl: Respect std430 layout in lower_buffer_access
Respect the std430 rules for determining offset and size of struct
members when using a std430 buffer. std140 rules lead to wrong buffer
offsets in that case.
Fixes my test case attached in Bugzilla. No piglit changes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104492
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Karol Herbst [Sun, 7 Jan 2018 20:42:19 +0000 (21:42 +0100)]
nir: fix st_nir_assign_var_locations for patch variables
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Ilia Mirkin [Sat, 24 Jun 2017 04:51:13 +0000 (00:51 -0400)]
nvc0: enable bindless on kepler
All the functionality is in. Maxwell will take a little bit more
enablement work.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 24 Jun 2017 04:44:35 +0000 (00:44 -0400)]
nvc0: add bindless image support for kepler
A part of the driver constbuf area is allocated for bindless images. Any
update requires uploading to all driver constbufs. This also extends the
driver constbuf to 64KB, up from 2KB.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Thu, 22 Jun 2017 03:13:20 +0000 (23:13 -0400)]
nvc0: add support for bindless textures on kepler+
This keeps a list of resident textures (per context), and dumps that
list into the active buffer list when submitting. We also treat bindless
texture fetches slightly differently, wrt the meaning of indirect, and
not requiring the SAMPLER file to be used.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 24 Jun 2017 00:44:56 +0000 (20:44 -0400)]
nv50/ir: use the image info in the instruction rather than decl
In preparation for bindless images, we have to retrieve the
target/format info from the instruction directly, as there will be no
declaration. Furthermore, for bound images, this information is still
available in the instruction, so we can drop the declaration-based
mechanism entirely.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 8 Apr 2017 04:05:18 +0000 (00:05 -0400)]
nvc0/ir: safen up lowering logic against overwriting reused values
I'm fairly sure both of the changed sites are OK as-is, but they're
fragile, so this is just safening them up. Since this is happening
pre-ssa, we don't want to be overwriting values that may potentially get
used later on.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Sat, 30 Dec 2017 06:07:30 +0000 (01:07 -0500)]
nvc0: update tic in-place when buffer address changes
This is helpful for bindless, where changing TIC id's is undesirable.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Mon, 1 Jan 2018 19:54:17 +0000 (14:54 -0500)]
nvc0: ensure that pushbuf keeps ref to old text/tls bos
If we free the bo, then the PTE may get deallocated immediately. We have
to make sure that the submission includes a ref to the old bo so that it
remains mapped for the duration of the command execution.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Kenneth Graunke [Fri, 5 Jan 2018 20:27:41 +0000 (12:27 -0800)]
i965: Torch public intel_batchbuffer_emit_dword/float helpers.
intel_batchbuffer_emit_float is dead code, it should go.
intel_batchbuffer_emit_dword only had one user, which had bungled using
them by forgetting to call intel_batchbuffer_require_space first. So it
seems wise to delete these unsafe helpers.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Fri, 5 Jan 2018 20:07:20 +0000 (12:07 -0800)]
i965: Require space for MI_BATCHBUFFER_END.
intel_batchbuffer_emit_dword doesn't reserve space for the DWord it
emits. In the past, we had some reserved batch space to ensure this
worked. With the switch to growing batches, we need to actually request
space so that we grow if necessary.
Fixes:
2c46a67b4138631217141f (i965: Delete BATCH_RESERVED handling.)
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Sun, 7 Jan 2018 01:32:04 +0000 (17:32 -0800)]
i965: Shut up a few unused variable warnings.
If asserts are disabled, you get pointless warnings about devinfo
being used (it's used to assert on devinfo->gen).
Marek Olšák [Tue, 2 Jan 2018 02:59:43 +0000 (03:59 +0100)]
ac: add ac_build_fmin/fmax helpers
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Wed, 13 Dec 2017 18:14:36 +0000 (19:14 +0100)]
mesa: remove dd_function_table::GetCompressedTexSubImage and clean it up
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Neil Roberts [Fri, 5 Jan 2018 10:38:58 +0000 (11:38 +0100)]
mesa: Tidy up the 4.6 section of GL4x.xml
The enums are moved to the top and indented like the rest of the file.
Comments are added to split up the function aliases by corresponding
extension. This should make no functional difference.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Samuel Pitoiset [Fri, 5 Jan 2018 09:03:03 +0000 (10:03 +0100)]
radv: remove unused radv_color_buffer_info::cb_clear_valueX
Found by inspection.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas nieuwenhuizen <bas@basnieuwenhuizen.nl>
Alex Smith [Thu, 4 Jan 2018 18:01:45 +0000 (18:01 +0000)]
anv: Take write mask into account in has_color_buffer_write_enabled
If we have a color attachment, but its writes are masked, this would
have still returned true. This is inconsistent with how HasWriteableRT
in 3DSTATE_PS_BLEND is set, which does take the mask into account.
This could lead to PixelShaderHasUAV not being set in 3DSTATE_PS_EXTRA
if the fragment shader does use UAVs, meaning the fragment shader may
not be invoked because HasWriteableRT is false. Specifically, this was
seen to occur when the shader also enables early fragment tests: the
fragment shader was not invoked despite passing depth/stencil.
Fix by taking the color write mask into account in this function. This
is consistent with how things are done on i965.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Neil Roberts [Fri, 24 Nov 2017 15:53:15 +0000 (16:53 +0100)]
mesa: Add GL4.6 aliases of functions from GL_ARB_indirect_parameters
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Samuel Pitoiset [Thu, 28 Dec 2017 21:55:27 +0000 (22:55 +0100)]
radv: enable denorms for 64-bit and 16-bit floats
Similar to RadeonSI.
This fixes:
dEQP-VK.image.texel_view_compatible.graphic.basic.attachment_read.bc*r16g16b16a16_sfloat
dEQP-VK.image.extended_usage_bit.attachment_write.r16_sfloat
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:57:35 +0000 (20:57 +0100)]
amd/common: correctly detect if we need ring buffers
When allocate_user_sgprs() was called, ctx->stage was actually
unset and 0 is for the vertex shader. This doesn't change
anything for now because of the spill support thing.
Though, the number of user SGPRs has to be fixed for merged
shaders on GFX9. It was broken before anyway.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 4 Jan 2018 15:24:22 +0000 (16:24 +0100)]
amd/common: use ac_image_load when lod is zero
This might decrease VGPR spilling, because we no longer
have to use v4i32 for 2D fetches when level == 0. We now
use v2i32 for those cases.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Thu, 4 Jan 2018 15:24:51 +0000 (16:24 +0100)]
radv: limit the scissor bug workaround to Vega 10 and Raven
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Alejandro Piñeiro [Thu, 4 Jan 2018 16:13:07 +0000 (17:13 +0100)]
glsl/standalone: set MaxTransformFeedbackBuffers
Using 4, as it is the default value on mesa. See mesa/main/config.h
and the following commit that introduced the value:
15ac66e331abdab12e882d80a6b4f647bc905298
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Alejandro Piñeiro [Thu, 4 Jan 2018 16:04:33 +0000 (17:04 +0100)]
glsl/standalone: set MaxVertexStreams
ARB_transform_feedback3 sets a minimum of 1, ARB_gpu_shader5 a minimum
of 4. It shouldn't matter too much, so choosing the later.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Alejandro Piñeiro [Thu, 4 Jan 2018 15:51:19 +0000 (16:51 +0100)]
glsl/standalone: set MaxUniformBufferBindings
Used to handle how many ubo you can define on the context. Minimimum
defined as 36 on ARB_uniform_buffer_object spec, up to 84 on OpenGL
4.6 (12 per stage at each moment).
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Alejandro Piñeiro [Thu, 4 Jan 2018 15:38:00 +0000 (16:38 +0100)]
glsl/standalone: point which arguments are mandatory
Every now and then I execute the standalone compiler, get the
non-version error, and need to remember what I'm doing wrong
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Timothy Arceri [Wed, 13 Dec 2017 07:46:56 +0000 (18:46 +1100)]
ac: rework ac_llvm_extract_elem()
Simplifies the logic a little and asserts index is 0.
Suggested-by: Nicolai Hähnle <nhaehnle@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 6 Dec 2017 02:32:17 +0000 (13:32 +1100)]
st/glsl_to_nir/radeonsi: enable tessellation shaders
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Mon, 11 Dec 2017 00:45:09 +0000 (11:45 +1100)]
gallium/tgsi: add patch support to tgsi_get_gl_varying_semantic()
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Thu, 7 Dec 2017 02:11:32 +0000 (13:11 +1100)]
radeonsi: add dummy implementation of si_nir_scan_tess_ctrl()
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 6 Dec 2017 06:34:32 +0000 (17:34 +1100)]
ac/radeonsi: add load_tess_coord() to the abi
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 6 Dec 2017 06:02:30 +0000 (17:02 +1100)]
radeonsi: make si_llvm_emit_tcs_epilogue compatible with emit_outputs abi
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 6 Dec 2017 05:02:34 +0000 (16:02 +1100)]
radeonsi/nir: gather tess properties
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 6 Dec 2017 03:36:11 +0000 (14:36 +1100)]
ac/radeonsi: add tcs_rel_ids to the abi
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 6 Dec 2017 03:18:34 +0000 (14:18 +1100)]
radeonsi: add unpack_llvm_param() helper
This allows us to pass the llvm param directly rather than looking
it up.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 6 Dec 2017 02:30:33 +0000 (13:30 +1100)]
ac: add {tcs,tes}_patch_id to the abi
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 6 Dec 2017 01:04:02 +0000 (12:04 +1100)]
radeonsi: add nir support for tcs outputs
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Mon, 11 Dec 2017 01:54:47 +0000 (12:54 +1100)]
ac: move some helpers to ac_llvm_build.c
We will call these from the radeonsi NIR backend.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 6 Dec 2017 00:51:51 +0000 (11:51 +1100)]
ac: add store_tcs_outputs() to the abi
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Tue, 5 Dec 2017 01:56:12 +0000 (12:56 +1100)]
radeonsi: add si_nir_load_input_tcs()
V2: drop type param and just use ctx->i32
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Mon, 11 Dec 2017 02:14:49 +0000 (13:14 +1100)]
radeonsi: add get_dw_address_from_generic_indices() helper
This will be used by both the tgsi and nir backends.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Tue, 5 Dec 2017 01:04:05 +0000 (12:04 +1100)]
ac: call load_tcs_input() via the abi
This also enables some code sharing with tes.
V2: drop type param and just use ctx->i32
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Mon, 4 Dec 2017 23:31:49 +0000 (10:31 +1100)]
ac: add load_tes_inputs() to the abi
V2: drop type param and just use ctx->i32
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Thu, 23 Nov 2017 02:04:46 +0000 (13:04 +1100)]
radeonsi: add si_nir_load_input_tes()
V2: drop type param and just use ctx->i32
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tim Rowley [Thu, 4 Jan 2018 16:08:48 +0000 (10:08 -0600)]
swr/rast: fix invalid sign masks in avx512 simdlib code
Should be 0x80000000 instead of 0x8000000.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Bas Nieuwenhuizen [Thu, 4 Jan 2018 01:11:51 +0000 (02:11 +0100)]
radv: Use correct flush bits for flushing L2 during CB/DB flushes.
Copied from radeonsi.
Putting in the correct metadata flush commands for eventually not
flushing L2 on CB/DB switch.
Does not remove the need for V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT
at the moment.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Thu, 4 Jan 2018 00:45:15 +0000 (01:45 +0100)]
radv: Invalidate L1 for VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT.
These are just shaders reads, so we need to invalidate L1.
Fixes:
6dbb0eaccc "radv: handle subpass cache flushes"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Wed, 20 Dec 2017 19:56:57 +0000 (20:56 +0100)]
radv/gfx9: reduce the number of input VGPRs for the GS stage
This can still be improved, but let's start with this.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 20 Dec 2017 19:56:56 +0000 (20:56 +0100)]
amd/common: scan if gl_PrimitiveID is used before translating to LLVM
It makes more sense to move all scan stuff in the same place.
Also, we don't really need to duplicate the uses_primid field
for each stages.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Wed, 20 Dec 2017 19:56:55 +0000 (20:56 +0100)]
amd/common: scan if gl_InvocationID is used
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rob Herring [Wed, 3 Jan 2018 16:16:23 +0000 (10:16 -0600)]
egl/android: Fix build break with dri2_initialize_android _EGLDisplay parameter
Commit
2f421651aca9 ("egl: let each platform decided how to handle
LIBGL_ALWAYS_SOFTWARE") broke the build due to copy-n-paste of misnamed
function parameter.:
src/egl/drivers/dri2/platform_android.c:1183:8: error: use of undeclared identifier 'disp'
Rather than just fixing 'disp', rename the function parameter 'dpy' to
'disp' to align with the other EGL platforms' implementations.
Fixes:
2f421651aca9 ("egl: let each platform decided how to handle LIBGL_ALWAYS_SOFTWARE")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Alex Smith [Thu, 4 Jan 2018 11:28:46 +0000 (11:28 +0000)]
anv: Add missing unlock in anv_scratch_pool_alloc
Fixes hangs seen due to the lock not being released here.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ilia Mirkin [Sat, 30 Dec 2017 05:28:51 +0000 (00:28 -0500)]
mesa/bindless: fix missing image _Layer initialization
Some later code relies on _Layer to set first/last_layer. Make sure it's
always initialized.
Detected by valgrind's conditional jump/move with uninit value logic.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Józef Kucia [Sun, 31 Dec 2017 09:19:15 +0000 (10:19 +0100)]
radeonsi: fix alpha-to-coverage if color writes are disabled
If alpha-to-coverage is enabled, we have to compute alpha
even if color writes are disabled.
Signed-off-by: Józef Kucia <joseph.kucia@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Bas Nieuwenhuizen [Wed, 3 Jan 2018 23:19:41 +0000 (00:19 +0100)]
ac: rename has_sync_file to has_fence_to_handle.
sync_files are in linux since 4.7, while the amdgpu fence_to_handle
ioctl is only in 4.15.
In particular we don't need it for sync_file in radv, because
everything happens via syncobjs, which got support earlier than
fence_to_handle.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bas Nieuwenhuizen [Mon, 1 Jan 2018 23:04:14 +0000 (00:04 +0100)]
ac/nir: Handle loading data from compact arrays.
Fixes:
f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Tue, 2 Jan 2018 02:32:14 +0000 (03:32 +0100)]
radv: Allow writing 0 scissors.
When rasterization is disabled we can have that few.
Fixes:
76603aa90b8 "radv: Drop the default viewport when 0 viewports are given."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Wed, 3 Jan 2018 20:58:49 +0000 (21:58 +0100)]
radv: Use correct HTILE expanded words.
Seems like users are actually hitting 0xFFFFFFFF actually making
things broken for them, and the mad max regression is fixed, so
lets put this in once more.
v2: Use 0xf for depth-only htile. (Dave)
Fixes:
af2844116fd "radv: Revert HTILE reset word to 0xFFFFFFFF."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Marek Olšák [Thu, 28 Dec 2017 14:59:19 +0000 (15:59 +0100)]
ac: rename has_syncobj_wait -> has_syncobj_wait_for_submit
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Eric Anholt [Fri, 29 Dec 2017 18:45:28 +0000 (10:45 -0800)]
braodcom/vc5: Fix internal type/bpp for RGB10_A2UI images.
I found that we were getting GPU hangs on most tests rendering to them,
and the simulator was assertion failing.