draw: use uint32_t instead of uint

In these cases we actually want uint32_t, because we're doing 32-bit
things to them.

The hwinfo-bit is only being used by i915, and should probably be
moved to i915 instead. But it shoukd *also* be converted, so let's do
that now.

While we're at it, fixup the bit-setting as well.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23833>

draw: use enum for tgsi-semantic

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23833>

cso: use enum for render-conditions

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23833>

radv/amdgpu: add a helper to get a new IB

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23727>

radv/amdgpu: rename old_ib_buffers to ib_buffers

No need to prefix with 'old' actually because this is just an array
of IB buffers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23727>

radv/amdgpu: use cs_finalize() when growing a CS

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23727>

radv/amdgpu: use the array of IB buffers for the chained IB path

For executing IB on the compute queue (ie. IB2 isn't supported), we
will need to break chaining, this is a first step towards this.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23727>

radv/amdgpu: do not set the IB size when ending a CS with RADV_DEBUG=noibs

This was only necessary for preambles/postambles, let's clarify this
by determining the IB info from the first IB in the array instead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23727>

radv/amdgpu: rework growing a CS with the chained IB path slightly

This should allow us to use cs_finalize().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23727>

radv/amdgpu: use the correct IB size when growing a CS with RADV_DEBUG=noibs

The current IB size is copied when radv_amdgpu_cs_add_old_ib_buffer()
is called, which might not be the real IB size because we might still
pad the CS with NOP packets after.

Found by inspection.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23727>

pvr: Advance entry pointer in pvr_setup_vertex_buffers()

Fixes: dEQP-VK.robustness.robustness1_vertex_access
  .out_of_bounds_stride_0
  .out_of_bounds_stride_16_single_buffer
  .out_of_bounds_stride_30_middle_of_buffer
  .out_of_bounds_stride_8_middle_of_buffer_separate

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23834>

compiler: Allow the explicit_stride of aoa types to be zero

The explicit stride doesn't have to be defined to aoa and therefore can be
zero in some cases, like in arrays of arrays of uniform blocks.

Resolves crash with spec@arb_gl_spirv@execution@ubo@aoa-2.shader_test piglit test for virgl.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23648>

anv: fix to set predicted weight tables correctly.

Fixes: 8d519eb5f ("anv: add initial video decode support for h265")
Closes: mesa/mesa#9214

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23790>

intel/genxml: changes the type for predicted weight to unsigned.

Turned out to be unsigned here after some experiments.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23790>

vulkan/video: keep delta weight and offsets of predicted weight tables in h265 slice parsing

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23790>

vulkan: Update XML and headers to 1.3.255

Acked-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23837>

vulkan: Add NV suffix to VK_NV_cooperative_matrix feature names

In the new Vulkan Headers, VK_KHR_cooperative_matrix gets added and the feature
names are the same.

Acked-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23837>

rusticl/program: skip linking compiled binaries

Applications can do their own caching, but are in any case required to
properly "compiler" the binaries via clBuildProgram or clCompileProgram +
clLinkPrograms.

In any case, there is no point building something if we already have the
result.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Nora Allen <blackcatgames@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23847>

rusticl: bump bindgen requirement

Apparently on some ARM systems any older bindgen version crashes.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Nora Allen <blackcatgames@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23840>

nir: Add function nir_function_set_impl

This function is added for create strong relationship between
nir_function_impl and nir_function.

So that nir_function->impl->function == nir_function is always true when
(nir_function->impl != NULL && nir_function->impl != NIR_SERIALIZE_FUNC_HAS_IMPL)

And indeed this invariant is already done in functions validate_function and validate_function_impl
of nir_validate

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23820>

vtn: Do not assign main_entry_point->impl twice

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23820>

draw: Update the comment and function name to match the type

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23845>

draw: Replace usage of ubyte/ushort/uint with uint8_t/uint16_t/uint32_t in draw_pt_vsplit.c

This can not be done with tools, so do it manually

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23845>

draw: Replace usage of boolean/TRUE/FALSE with bool/true/false in draw_pt_vsplit*

These change can not be done with tools, so do it manually

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23845>

rusticl/mesa: create proper build-id hash for the disk cache

Without generating a proper timestamp for the disk cache, we pull old
binaries out of the disk cache, potentially being buggy or simply
outdated.

Once meson 1.2 lands we can easily pull in LLVM functions.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Nora Allen <blackcatgames@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21612>

rusticl/meson: extract common bindgen rust args

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Nora Allen <blackcatgames@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21612>

rusticl: generate bindings for build-id stuff

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Nora Allen <blackcatgames@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21612>

rusticl: structurize and reorder mesa binding args

It became quite a mess, I had enough 🙃

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Nora Allen <blackcatgames@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21612>

v3dv: replace boolean and uint with bool and size_t

There's no reason to use the gallium `p_compiler.h` types in vulkan code.

Inspired by https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577,
but using `size_t` for `ulist_data_size` because its two users are
`blob_read_bytes()` and `memcpy()`, both of which expect a `size_t`.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23795>

docs/coding-style: add pre-commit hook fallback for clang-format

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23722>

docs/coding-style: add example emacs config for clang-format

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23722>

docs/coding-style: add example vim config for clang-format

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23722>

r300: properly count maximum used register index

The problem is when we have DP2 or DP3 instruction that writes a w
channel like here:

DP3 temp[148].w, -temp[147].xyz_, temp[57].xyz_;

will get pair-converted to

src0.xyz = temp[147], src1.xyz = temp[57]
DP3, -src0.xyz, src1.xyz
DP3 temp[148].w, -src0._, src0._

where the alpha instruction is a basically just a replicate of the
result from the RGB sub intruction. However the destination register
index in the RBG slot is also 148. Now we pair-schedule and regalloc

src0.xyz = temp[13], src1.xyz = temp[3]
DP3, -src0.xyz, src1.xyz
DP3 temp[3].w, -src0._, src0._

We properly regalloc the alpha channel, but we obviously skip the rgb,
because the writemask is empty there. However when we emit the shader
later, we actually check the number of used regs based on the maximum
used register index and we don't consider the writemasks, so we would
think we use 149 temps. AFAIK the shader would be still completelly OK.
But we would think it hits the HW limits and used a dummy one instead.

Fix this by checking for empty writemasks when marking the registers as
used.

GAINED: shaders/glmark/1-22.shader_test FS

This is also needed to prevent another lost Trine shader from
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089

Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23838>

anv: Only expose video decode bits with KHR_video_decode_queue

This fixes dEQP-VK.api.info.format_properties.g8_b8r8_2plane_420_unorm
in combination with the CTS fix from
https://gerrit.khronos.org/c/vk-gl-cts/+/12191

Fixes: 93614817806 ("anv: add video format features for the one supported video output format")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8263
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23776>

anv: Pipe anv_physical_device to anv_get_image_format_features2

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23776>

nv50/ir/nir: set numBarriers if we emit an OP_BAR

Even though the field is called `numBarriers` we set it to 1 just like
we do with TGSI. It's unknown on what's the proper behavior here is. But
without this set the GPU will complain to us loudly, so this silences at
least that.

Fixes: a2d7a4f9788 ("nv50/ir: convert to scoped_barrier")
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23749>

nvc0: fix printing shaders

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23749>

rusticl/program: add debugging option to disable SPIR-V validation

This is useful for running applications known to pass in invalid SPIR-V.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Nora Allen <blackcatgames@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23818>

rusticl/program: add debugging for OpenCL C compilation

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Nora Allen <blackcatgames@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23818>

docs: document CLC_DEBUG

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Nora Allen <blackcatgames@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23818>

intel: Initialize FF_MODE2 on all Gfx12 platforms

On Alchemist, the FF_MODE2 documentation says that we must set the
FF_MODE2 timer values for GS and HS to 224.  The hardware performance
tuning guide also recommends setting the TDS timer to 4.

On Tigerlake, i915 applies workarounds to set the GS timer to 224
(failing to do so can cause HS/DS unit hangs), and the TDS timer to 4
(for performance).  It doesn't currently apply a HS timer there, and
I'm not sure if it's strictly necessary, but given that Alchemist
needed it, and the other two settings matched, let's assume that it
ought to match as well.

Unfortunately, there has been a bug in the i915 workarounds
infrastructure for non-masked context registers where writing one
field of the register zeroes out all the others.  So, I believe the
Tigerlake TDS timer value of 4 isn't being applied correctly there,
though the register is also not readable on that platform which
makes it hard to verify.  So, this may also speed up tessellation.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9233
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23839>

intel/gfx12.5: Enable L3 partial write merging for compressible surfaces among other cases.

This enables L3 partial write merging for a number of cases that seem
to be getting accidentally disabled by the kernel, which was causing a
serious performance bottleneck on DG2 and MTL platforms.  The
"Compressible Partial Write Merge Enable", "Coherent Partial Write
Merge Enable" and "Cross-Tile Partial Write Merge Enable" bits in
L3SQCREG5 were expected to be enabled by default (and confusingly,
they even read off as enabled if you ran 'intel_reg read 0xb158' on an
idle system), but they are getting clobbered during 3D context
initialization by an i915 workaround.

Enabling L3 partial write merging of compressible surfaces in
particular seems to increase rendering fillrate by over 3x in some
cases (e.g. the
"VulkanFillRate/FillRateGPU/resolution:1[0-3]/format:*/blend:0"
fillrate-bound microbenchmarks).  Significant improvements can also be
reproduced in most real-world workloads we've tested so far,
e.g. Counter Strike GO improves by ~11%, Shadow Of the Tomb Raider
improves by ~5.5%, and AztecRuins-VK improves by ~6.5% on DG2-512 --
Thanks a lot to Caleb Callaway for these figures.  No regressions have
been observed so far.

Even though this patch might strike as surprisingly simple for such a
large payoff, it's the result of Felix DeGrood and I trying to
root-cause the rendering performance gap of DG2 on Linux vs Windows on
and off during the last year, and some of the OA statistics captured
by Felix early this month were greatly helpful for me to connect the
last few dots, so Felix deserves a big chunk of the credit for this
work.

Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23783>

ci/fastboot: use gzipped Image to avoid compressing on the runner

Faster download, one less step. Win-win.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23816>

frontends/va: fix some coverity scan reported issues

Added some checks for NULL pointer dereferencing and loop bounds.
v2: Use ARRAY_SIZE instead of magic numbers (@jenatali)

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23598>

meson: Explicitly add "check : false" to a couple instances of run_command

In both cases there's code right after the execution to check the result and
give a proper message.

This gets rid of meson warning

```
WARNING: You should add the boolean check kwarg to the run_command call.
         It currently defaults to false,
         but it will default to true in future releases of meson.
         See also: https://github.com/mesonbuild/meson/issues/9300
```

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23821>

amd/drm-shim: use fixed-width types

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9221
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23725>

agx: Implement vector live range splitting

The SSA killer feature is that, under an "optimal" allocator, the number of
registers used (register demand) is *equal* to the number of registers required
(register pressure, the maximum number of variables simultaneously live at any
point in the program). I put "optimal" in scare quotes, because we don't need to
use the exact minimum number of registers as long as we don't sacrifice thread
count or introduce spilling, and using a few extra registers when possible can
help coalesce moves. Details-shmetails.

The problem is that, prior to this commit, our register allocator was not
well-behaved in certain circumstances, and would require an arbitrarily large
number of registers. In particular, since different variables have different
sizes and require contiguous allocation, in large programs the register file may
become fragmented, causing the RA to use arbitrarily many registers despite
having lots of registers free.

The solution is vector live range splitting. First, we calculate the register
pressure (the minimum number of registers that it is theoretically possible to
allocate successfully), and round up to the maximum number of registers we will
actually use (to give some wiggle room to coalesce moves). Then, we will treat
this maximum as a *bound*, requiring that we don't use more registers than
chosen. In the event that register file fragmentation prevents us from finding a
contiguous sequence of registers to allocate a variable, rather than giving up
or using registers we don't have, we shuffle the register file around
(defragmenting it) to make room for the new variable. That lets us use a
few moves to avoid sacrificing thread count or introducing spilling, which is
usually a great choice.

Android GLES3.1 shader-db results are as expected: some noise / small
regressions for instruction count, but a bunch of shaders with improved thread
count. The massive increase in register demand may seem weird, but this is the
RA doing exactly what it's supposed to: using more registers if and only if they
would not hurt thread count. Notice that no programs whatsoever are hurt for
thread count, which is the salient part.

   total instructions in shared programs: 1781473 -> 1781574 (<.01%)
   instructions in affected programs: 276268 -> 276369 (0.04%)
   helped: 1074
   HURT: 463
   Inconclusive result (value mean confidence interval includes 0).

   total bytes in shared programs: 12196640 -> 12201670 (0.04%)
   bytes in affected programs: 1987322 -> 1992352 (0.25%)
   helped: 1060
   HURT: 513
   Bytes are HURT.

   total halfregs in shared programs: 488755 -> 529651 (8.37%)
   halfregs in affected programs: 295651 -> 336547 (13.83%)
   helped: 358
   HURT: 9737
   Halfregs are HURT.

   total threads in shared programs: 18875008 -> 18885440 (0.06%)
   threads in affected programs: 64576 -> 75008 (16.15%)
   helped: 82
   HURT: 0
   Threads are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

agx/lower_parallel_copy: Lower 64-bit copies

To 32-bit. This way we don't get into bad situations where we need to eg swap
unaligned 64-bit values or something funny like that.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

agx: Validate predecessor information

Including the new loop header? flag.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

agx: Add loop header? flag

This is useful for deciding whether we need to fix up phis in RA.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

agx: Recollect stored vectors at their use

This is Timur's cheesy solution to split-hell.shader_test. Seems to work ok
here.

Before: 94 inst, 588 bytes, 165 halfregs, 1 threads, 0 loops, 0:0 spills:fills
After: 63 inst, 454 bytes, 129 halfregs, 1 threads, 0 loops, 0:0 spills:fills

On Android GLES3.1 shader-db, a few shaders are helped a lot:

   total instructions in shared programs: 1781706 -> 1781473 (-0.01%)
   instructions in affected programs: 4284 -> 4051 (-5.44%)
   helped: 16
   HURT: 2
   Instructions are helped.

   total bytes in shared programs: 12197854 -> 12196640 (<.01%)
   bytes in affected programs: 29526 -> 28312 (-4.11%)
   helped: 20
   HURT: 2
   Bytes are helped.

   total halfregs in shared programs: 489007 -> 488755 (-0.05%)
   halfregs in affected programs: 945 -> 693 (-26.67%)
   helped: 7
   HURT: 0
   Halfregs are helped.

   total threads in shared programs: 18873216 -> 18875008 (<.01%)
   threads in affected programs: 5376 -> 7168 (33.33%)
   helped: 7
   HURT: 0
   Threads are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

agx: Extract coordinate register size calculation

It will be used for image writes too, not just reads.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

asahi: Pass through surface sample count

This makes PIPE_CAP_SURFACE_SAMPLE_COUNT do something, namely, explode
with lots of fireworks. We'll have to figure out what's wrong, but at
least now we aren't just not trying at all. Should not break anything as
long as PIPE_CAP_SURFACE_SAMPLE_COUNT is not flipped on.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

asahi: Disable PIPE_CAP_SURFACE_SAMPLE_COUNT

This never worked, disable it.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

asahi: Revert "Advertise ARB_texture_barrier"

This reverts commit 9e67d3f23780a818b9fc764105f39c6d595c6530.

We do not, in fact, implement texture barriers. Texture barriers are
supposed to allow non-overlapping rendering feedback loops. We cannot
support that at non-tile boundaries when texture compression is enabled
without some kind of downgrade path or other special handling.

Fixes Emacs corruption on X/Glamor.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

agx: Fix discards

Switch our frontends from generating sample_mask_agx to discard_agx, and
switching from legalizing sample_mask_agx to lowering discard_agx to
sample_mask_agx. This is a much easier problem and is done here in a way that is
simple (and inefficient) but obviously correct.

This should fix corruption in Darwinia.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

agx: Update explanation of sample_mask behaviour

We discovered today that these (probably) trigger depth/stencil testing, which
has significant implications for the correct/performant use.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

nir: Add discard_agx intrinsic

sample_mask_agx corresponds directly to the hardware's 2-source instruction, but
it's hard to use correctly and even harder to legalize after the fact, since
it's responsible for not only discard but also late depth/stencil testing. For
our various high-level lowering passes, it's easier to use a one-source discard
(where we don't have to worry about sample masks), which the compiler will
internally lower to the two-source instruction. Introduce such an instruction.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23832>

radv: adjust alignment of the preprocess buffer with DGC

The preprocess buffer is the buffer used to generate the cmdbuf. It
was aligned to 256 bytes but the correct alignment is actually
ac_gpu_info::ib_alignment.

Otherwise, if a DGC IB is executed like a IB1, this hits an assertion
in radv_amdgpu_cs_submit() because the alignment is incorrect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23764>

radv: only dirty the active push constant stages with DGC

It's unnecessary to dirty all stages.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23761>

radv: only dirty the index type when necessary with DGC

This should only be needed for non-indexed draws and it's already
dirty if the DGC binds an index buffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23761>

radv/amdgpu: dump all cs with RADV_DEBUG=noibs

It was only dumping the oldest.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23646>

radv/amdgpu: fix dumping cs with RADV_DEBUG=noibs

The ib_buffer is NULL now.

Fixes: 50e6b16855d ("radv/amdgpu: Use fallback submit for queues that can't use IBs.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23646>

pvr: Correctly read dynamic state setup during blend constant setup

Somewhat counterintuitively, dynamic_state.set contains the bits that
have been loaded from static state, i.e. those that are _not_ dynamic.

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23590>

radeonsi: disable H264HIGH10 profile

Issue: H.264 high 10 profile is currently not supported, but is shown as
supported in vainfo.

Reason: Kernel reported capabilities for video encoder/decode doesn't
consider the actual profile (only using reduced profile).

Solution: Use kernel reported capabilities only for basic H.264/HEVC
profiles. Other profiles (e.g. 10 bits) should be checked based on HW.

Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9242

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23824>

radv: reserve more space in CS for SQTT

Otherwise, it can hit an assertion.

Fixes: 7893040f807 ("radv: Add stricter space checks.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23826>

aco: Drop NIR parallel copy handling

Backends never see these instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Suggested-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23831>

aco: Remove unneeded stage related info fields.

Cleanup of various fields with redundant information.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23597>

aco: Use aco_shader_info::hw_stage instead of guessing.

With this change, ACO is going to rely on the caller to set
the HW stage and will no longer guess it from the input shaders.

This will help enable compiling merged shaders separately,
but that will need further changes in instruction selection.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23597>

radv: Set aco_shader_info::hw_stage

ACO will rely on this field instead of guessing
the stage internally.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23597>

radeonsi: Set aco_shader_info::hw_stage

ACO will rely on this field instead of guessing
the stage internally.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23597>

aco: Add hw_stage field to aco_shader_info.

Unused in this commit, but this is going to replace the shader
stage selection inside ACO after the drivers set it correctly.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23597>

aco: Use ac_hw_stage instead of aco-specific HWStage.

The new ac_hw_stage is going to be used by drivers as well.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23597>

ac: Add ac_hw_stage enum.

This is going to be shared between RADV, RadeonSI and ACO.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23597>

treewide: spelling fixes

Debian's lintian tool flagged some spelling issues:
assumtion -> assumption
unkown -> unknown
memeber -> member
sucess -> success
perfomance -> performance

Signed-off-by: Diederik de Haas <didi.debian@cknow.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23618>

anv: fix utrace batch allocation

The introduction of a workaround adding lots of MI_NOOPs broke our
computation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b9aa66d5d0 ("anv: disable preemption for 3DPRIMITIVE during streamout")
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23792>

freedreno/decode: Correctly handle chip_id

gpu_id is not decodable from chip_id in general case,
so we should use chip_id to search for fd_dev_info and get
GPU generation from that.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23828>

freedreno,ir3: Don't call fd_dev_64b more than necessary

fd_dev_64b calls fd_dev_gen which after the last commit calls
fd_dev_info that may scan through all hw definitions.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23828>

freedreno: Decouple GPU gen from gpu_id/chip_id

gpu_id is obsolete, chip_id doesn't encode the GPU generation.
Thus we have to manually specify the GPU gen instead of inferring it.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23828>

freedreno/perfcntrs: Link with libfreedreno_common

Header from freedreno/common is used without linking with its
implementation. It worked before because all called functions
were header only, which would change soon.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23828>

ci: Upref virglrenderer

Update expectation too.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23768>

virgl/ci: Drop duplicate runs

CTS GL 3.2 includes all the tests of previous versions.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23768>

vulkan: Migrate shader module hash to BLAKE3.

Shaders are the largest thing we hash now, so they benefit from a faster
hash.

Change the field name from `sha1` to `hash` to avoid tying the definition
to a particular algorithm. This doubles down as a precaution against
callers still assuming a 20-byte hash (in which case the compilation will
error out).

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22571>

util/blake3: Add blake3_hash typedef.

This is more ergonomic than unsigned char hash[BLAKE3_OUT_LEN].

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22571>

Revert "egl: return correct error for EGL_KHR_image_pixmap"

This reverts commit 5db031bf3ea3e37983f3ab17f2b550e1949d95a9.

It crashes X after logging in on Ubuntu 20.04.

Fixes: 5db031bf3ea3e3 - egl: return correct error for EGL_KHR_image_pixmap

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23740>

r600/sfn: Don't clear clear group flag on vec4 that comes from TEX or FETCH

If we consider clearing the group flag of a vec4 register that is used as
source for some instruction we have to take into account that the parent
of the register element may also be part of a group in the parent instruction.
In this case we must not clear the group flag.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9118

Fixes:  f3415cb26a (r600/sfn: copy propagate register load chains)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23813>

anv/video: fix to set U/V offset correctly.

Fixes: 98c58a16ef1a ("anv: add initial video decode support for h264.")

Closes: mesa/mesa#9227

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23819>

glsl: call nir_opt_find_array_copies() when linking

shader-db results IRIS (BDW):

total instructions in shared programs: 17883388 -> 17859658 (-0.13%)
instructions in affected programs: 48100 -> 24370 (-49.33%)
helped: 6
HURT: 0
helped stats (abs) min: 1450 max: 7028 x̄: 3955.00 x̃: 3387
helped stats (rel) min: 40.31% max: 51.92% x̄: 47.07% x̃: 48.96%
95% mean confidence interval for instructions value: -6613.28 -1296.72
95% mean confidence interval for instructions %-change: -52.73% -41.40%
Instructions are helped.

total cycles in shared programs: 866961809 -> 863521521 (-0.40%)
cycles in affected programs: 9179396 -> 5739108 (-37.48%)
helped: 6
HURT: 0
helped stats (abs) min: 252584 max: 972430 x̄: 573381.33 x̃: 495130
helped stats (rel) min: 21.80% max: 48.65% x̄: 35.01% x̃: 34.58%
95% mean confidence interval for cycles value: -917157.00 -229605.67
95% mean confidence interval for cycles %-change: -47.61% -22.40%
Cycles are helped.

total spills in shared programs: 20417 -> 15521 (-23.98%)
spills in affected programs: 6966 -> 2070 (-70.28%)
helped: 6
HURT: 0

total fills in shared programs: 25151 -> 21005 (-16.48%)
fills in affected programs: 4374 -> 228 (-94.79%)
helped: 6
HURT: 0

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9055
Fixes: d75a36a9eeb1 ("glsl: remove do_copy_propagation_elements() optimisation pass")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23737>

nir/load_libclc: run some opt passes for everybody

Cuts down serialized size from 2850288 to 1377780 bytes.

Reduces clinfo with Rusticl time by 40% for debug builds.

(Old data, but the point stands)

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15996>

rusticl/device: create helper context before loading libclc

Some drivers (llvmpipe) postpone some screen initialization until the
first context is created.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15996>

venus: Fix detection of push descriptor set

- Fix null deref. VkPipelineLayoutCreateInfo::pSetLayouts is allowed to
  contain VK_NULL_HANDLE.
- The loop 'break' was misplaced.

Fixes crash in
dEQP-VK.pipeline.pipeline_library.graphics_library.fast.0_00_11_11 after
VK_EXT_graphics_pipeline_library is enabled in a later patch.

Fixes: 91966f2eff1 ("venus: extend lifetime of push descriptor set layout")
Signed-off-by: Lina Versace <linyaa@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23810>

nir/opt_if: Use block_ends_in_jump

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23782>

nir: Remove integer and 64-bit modifiers

Now that Intel and R600 both do their own modifier propagation, the only
backends that still lower modifiers in NIR are:

* nir-to-tgsi
* lima
* etnaviv
* a2xx

The latter 3 backends do not support integers, and certainly do not support
fp64. So they don't use these.

TGSI in theory supports integer negate modifiers but NTT doesn't use them, so
they're unused there too.

Since they're unused, we remove NIR support for integer and 64-bit modifiers,
leaving only 16/32-bit float modifiers. This will reduce the scope needed for a
replacement to NIR modifiers, being pursued in !23089.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23782>

venus: Advertise 1.3 in ICD file

It was still advertising 1.2.

Signed-off-by: Lina Versace <linyaa@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23808>

venus: suballocate feedback slot with feedback buffer alignment

Venus sync feedback design relies on concurrent host device resource
access. To avoid device flush overwriting host writes, we must
suballocate the slots with a minimum size of the buffer alignment.

Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23633>

docs: update calendar for 23.1.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23805>

docs/relnotes: add sha256sum for 23.1.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23805>

docs: add release notes for 23.1.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23805>

anv: align buffers to a cache line

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9217
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23794>

r300: add partial CMP support on R5xx

VE_COND_MUX_GTE4 is a nice match for the TGSI CMP opcode, however
there is a big limitation due to the general shortcoming of the
vertex shader engine that any instruction can read only two different
temporary registers. So we still have to lower in some cases.

Shader-db RV530:
total instructions in shared programs: 130872 -> 130333 (-0.41%)
instructions in affected programs: 29854 -> 29315 (-1.81%)
helped: 294
HURT: 83
total temps in shared programs: 16747 -> 16775 (0.17%)
temps in affected programs: 407 -> 435 (6.88%)
helped: 10
HURT: 38

Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23691>