Mike Blumenkrantz [Thu, 2 Jun 2022 20:57:16 +0000 (16:57 -0400)]
zink: tu ci updates
734
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16844>
Mike Blumenkrantz [Thu, 2 Jun 2022 18:04:04 +0000 (14:04 -0400)]
zink: force queries to start/end out of renderpass
spec requires queries to either start and end in the same renderpass
or start and end outside of renderpass, so do the latter since it's
easier to track
cc: mesa-stable
fixes #6579
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16844>
Alyssa Rosenzweig [Fri, 3 Jun 2022 00:27:41 +0000 (20:27 -0400)]
pan/bi: Fix clper_xor on Mali-G31
Mali-G31 has the old CLPER instruction, not the new one, which means we don't
get to specify a custom lane op. But the clper_xor helper incorrectly checked
the arch, not the implementation quirk.
Fixes:
c00e7b729fe ("pan/bi: Optimize abs(derivative)")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-by: Icecream95 <ixn@disroot.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16846>
Emma Anholt [Thu, 2 Jun 2022 22:59:43 +0000 (15:59 -0700)]
i915g: Ignore the new SEPARABLE_PROGRAM property.
We didn't need to know about it before, and we still don't.
Fixes:
b63403054237 ("tgsi: Add SEPARABLE_PROGRAM property")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16845>
Paulo Zanoni [Fri, 8 Apr 2022 22:48:05 +0000 (15:48 -0700)]
intel/compiler: call ordered_unit() only once at update_inst_scoreboard()
Call it once instead of calling the very same function for each source
and destination. This should make those ternary operators a little
easier to read, IMHO.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15835>
Paulo Zanoni [Mon, 21 Mar 2022 20:17:30 +0000 (13:17 -0700)]
intel/compiler: split handling of 64 bit floats and ints
In opt_algebraic(), handle TYPE_DF in a different check than TYPE_Q. We have a
separate flag for each type, use separate checks so platforms where one is true
and the other is not can work properly.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15835>
Paulo Zanoni [Thu, 10 Mar 2022 00:56:08 +0000 (16:56 -0800)]
intel/compiler: compute int64_options based on devinfo->has_64bit_int
Don't compute it based on devinfo->has_64bit_float. Othwerwise we may
end up emitting 64bit-int (Q) instructions on platforms with 64bit
floats but not 64bit integers.
Right now, the only platforms where has_64bit_int is different from
has_64bit_float are the platforms that use GFX7_FEATURES.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15835>
Kenneth Graunke [Thu, 2 Jun 2022 09:11:15 +0000 (02:11 -0700)]
intel/compiler: Fix uncompaction of signed word immediates on Tigerlake
This expression accidentally performs a 32-bit sign-extension when
processing the second half of the expression (the low 16 bits).
Consider -7W, which is represented as 0xfff9fff9 in our encoding (the
16-bit word is replicated to both halves of the 32-bit dword).
Tigerlake's compaction stores the low 11-bits of an immediate as-is,
and replicates the 12th bit. So here, compacted_imm will be 0xff9.
( (int)(0xff9 << 20) >> 4) |
((short)(0xff9 << 4) >> 4))
0xfff90000 | (0xff90 >> 4)
0xfff90000 | 0xfffffff9 ...oops...
0xfffffff9
By casting the second line of the expression to unsigned short, we
prevent the sign-extension when it combines both parts, so we get:
0xfff90000 | 0x0000fff9
0xfff9fff9
Fixes:
12d3b11908e ("intel/compiler: Add instruction compaction support on Gen12")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16833>
Mike Blumenkrantz [Thu, 2 Jun 2022 19:52:37 +0000 (15:52 -0400)]
zink: fix radv piglit fails
I deleted the wrong one by accident
fixes
0c4a65ef34521b47fda4c5b59acfc4a8e97703f5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16843>
Yonggang Luo [Wed, 1 Jun 2022 21:31:14 +0000 (05:31 +0800)]
ci/vs2019: Clear CI_COMMIT_MESSAGE and CI_COMMIT_DESCRIPTION for please meson
Fixes https://gitlab.freedesktop.org/lygstate/mesa/-/jobs/
23444155/raw
https://gist.github.com/lygstate/
201dd9d2db3d411668f7bbdc17daf74a
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16825>
Renato Pereyra [Fri, 27 May 2022 01:22:16 +0000 (18:22 -0700)]
venus: Add driconf option to enable implicit fencing
Signed-off-by: Renato Pereyra <renatopereyra@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16735>
Mike Blumenkrantz [Wed, 11 May 2022 14:29:16 +0000 (10:29 -0400)]
mesa: throw a log warning any time a fallback texture is used
this generally means an app is broken in some way, so throw a log
message to be helpful
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16821>
Alyssa Rosenzweig [Mon, 9 May 2022 14:18:13 +0000 (10:18 -0400)]
pan/bi: Rework Valhall register alignment
Because we lower SPLIT and COLLECT before RA, we need to consider offsets when
determining the dimensions of vectors, in order to align properly. Lowering
COLLECT post-RA would avoid this special case.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16780>
Alyssa Rosenzweig [Sun, 13 Mar 2022 23:27:32 +0000 (19:27 -0400)]
pan/bi: Align 64-bit register sources
Similar idea to aligning staging register sources.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16780>
Alyssa Rosenzweig [Tue, 31 May 2022 19:04:59 +0000 (15:04 -0400)]
pan/bi: Allow vec6 for collects
Hit for some Valhall texturing instructions.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16780>
Icecream95 [Thu, 2 Jun 2022 15:57:08 +0000 (11:57 -0400)]
pan/bi: Use nodearrays for linear constraints
Speeds up compiling shaders/skia/781.shader_test in shader-db by 8x
(Icecream95).
...At least it did before I extended to support register allocation of vec8. On
Valhall, texture instructions require up to 8 consecutive registers. To handle
this, provide for vec8 register allocation. Liveness was already (accidentally?)
vec8. The increased memory requirement is acceptable given that the interference
matrix is now stored sparsely (Alyssa).
Icecream95 reports the vec8 changes hurt RA performance by about 1% on average.
I consider this acceptable for now.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16780>
Icecream95 [Thu, 2 Jun 2022 15:56:27 +0000 (11:56 -0400)]
pan/bi: Add nodearray datastructure
This is an array which can either be sparse or dense, and was designed
to be used to track liveness and interference information.
Either a sparse array with sorted indices or dense array is used.
Other data structures were tried, such as red-black trees or hash
tables, but they were slower. When used for storing constraints, the
indices do not have to be sorted as duplicating elements is okay, but
the speedup from that was not enough to justify the extra complexity.
v2: Add a comment about how to potentially speed it up. But it seems
fast enough even without this change.
v3: Use a custom struct rather than relying on util_dynarray.
v4: Split out functions only used for liveness analysis, rather than the simpler
data structure needed for the register interference matrix. If we need to
optimize liveness, that can follow on after. Also make it for vec8 (Alyssa).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16780>
Icecream95 [Sun, 2 Jan 2022 22:57:24 +0000 (11:57 +1300)]
pan/bi: Reverse linear constraint bits
This will make it simpler to implement parallel RA where multiple
possible registers for a node are tested at once.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16780>
Sil Vilerino [Fri, 20 May 2022 14:38:48 +0000 (07:38 -0700)]
d3d12: Align output buffer offset access to D3D12_FEATURE_DATA_VIDEO_ENCODER_RESOURCE_REQUIREMENTS.CompressedBitstreamBufferAccessAlignment
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16644>
Connor Abbott [Thu, 2 Jun 2022 00:54:54 +0000 (02:54 +0200)]
tu: Enable shaderTessellationAndGeometryPointSize
This already works and AFAICT there was no reason to disable it other
than that the blob does.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16830>
Danylo Piliaiev [Thu, 2 Jun 2022 10:52:05 +0000 (13:52 +0300)]
tu: Fix D32S8 resolves into D32 or S8 in sysmem mode
Fixes CTS tests in sysmem mode:
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint.compatibility_depth_zero_stencil_zero_testing_depth
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint_separate_layouts.compatibility_depth_zero_stencil_zero_testing_depth
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint_separate_layouts.compatibility_depth_zero_stencil_zero_testing_stencil
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d32_sfloat_s8_uint.compatibility_depth_zero_stencil_zero_testing_depth
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d32_sfloat_s8_uint_separate_layouts.compatibility_depth_zero_stencil_zero_testing_depth
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d32_sfloat_s8_uint_separate_layouts.compatibility_depth_zero_stencil_zero_testing_stencil
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16834>
Samuel Pitoiset [Thu, 2 Jun 2022 11:16:11 +0000 (13:16 +0200)]
radv/ci: update list of failures for Pitcairn
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16836>
Rhys Perry [Tue, 18 Jan 2022 14:53:38 +0000 (14:53 +0000)]
radv,aco: disable shader cache when ACO debug options are used
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14594>
Jason Ekstrand [Wed, 1 Jun 2022 18:32:20 +0000 (13:32 -0500)]
nir: xfb_buffer_info::stride is in bytes
For the NIR XFB gathering as well as all the Vulkan drivers, buffer
strides in nir_xfb_info are in bytes. When Marek started using
nir_xfb_info for GLSL on radeonsi, he copied directly from the GLSL
struct which has strides in dwords. This inconsistency didn't show up
until I went through and started us using the NIR passes for GL drivers
directly without going through the GLSL structs. We could change the
nir_xfb_buffer_info field to be in dwords to be consistent with
shader_info but that would mean changing all the Vulkan drivers but, for
now, it's easier to always use bytes in nir_xfb_info.
Fixes:
2a22885a457e ("st,nir: Use nir_shader::xfb_info in nir_lower_io_passes")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16819>
Jason Ekstrand [Wed, 1 Jun 2022 18:26:46 +0000 (13:26 -0500)]
nir/glsl: Use rzalloc for nir_xfb_info
A lot of the fields get fully overwritten but outputs/buffers_written
are both bitfields that we set one bit at a time.
Fixes:
7c5dc0b11a11 ("glsl/nir: Populate nir_shader::xfb_info after linking varyings")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16819>
Mike Blumenkrantz [Wed, 1 Jun 2022 20:25:58 +0000 (16:25 -0400)]
lavapipe: fix dynamic patchControlPoints
the dynamic state value is independent of whether tesselation is used
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16824>
Erik Faye-Lund [Wed, 1 Jun 2022 11:38:39 +0000 (13:38 +0200)]
include: drop c11_compat.h
We now require C11, and C++ supports static_assert just fine, which is
the only thing this header ever added support for. So let's get rid of
this needless header.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>
Erik Faye-Lund [Wed, 1 Jun 2022 12:46:46 +0000 (14:46 +0200)]
include: drop c99_math.h
Since we now depend on C11, we know that we have support for the C99
math functionality. So let's drop the c99_math.h compatibility wrapper,
and just include <math.h> directly.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>
Erik Faye-Lund [Wed, 1 Jun 2022 12:22:19 +0000 (14:22 +0200)]
vulkan/device_select: remove needless c99_compat.h includes
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>
Erik Faye-Lund [Wed, 1 Jun 2022 12:21:51 +0000 (14:21 +0200)]
intel/isl: remove needless c99_compat.h includes
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>
Erik Faye-Lund [Wed, 1 Jun 2022 12:21:31 +0000 (14:21 +0200)]
include: remove needless c99_compat.h includes
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>
Erik Faye-Lund [Wed, 1 Jun 2022 12:20:58 +0000 (14:20 +0200)]
gallium: remove needless c99_compat.h includes
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>
Erik Faye-Lund [Wed, 1 Jun 2022 12:20:27 +0000 (14:20 +0200)]
mapi: remove needless c99_compat.h includes
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>
Erik Faye-Lund [Wed, 1 Jun 2022 12:19:59 +0000 (14:19 +0200)]
gallium/util: remove needless c99_compat.h includes
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>
Erik Faye-Lund [Wed, 1 Jun 2022 12:19:02 +0000 (14:19 +0200)]
egl: remove needless c99_compat.h includes
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>
Erik Faye-Lund [Wed, 1 Jun 2022 12:17:43 +0000 (14:17 +0200)]
util: remove needless c99_compat.h includes
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>
Erik Faye-Lund [Wed, 1 Jun 2022 12:04:53 +0000 (14:04 +0200)]
util: add missing c99_compat.h includes
These headers use the "restrict" keyword, so they need to include
c99_compat.h in case they get included from C++.
Right now, we include c99_compat.h in many needless places, which saves
us. But we're about to stop doing that.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>
Erik Faye-Lund [Wed, 1 Jun 2022 11:33:48 +0000 (13:33 +0200)]
c99_compat.h: remove inline and __func__ shims
We're requiring C11 now, and both "inline" and __func__ is supported
in C++ code as well. So no need for these compatibility-shims anymore.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>
Erik Faye-Lund [Wed, 1 Jun 2022 11:14:27 +0000 (13:14 +0200)]
meson: modernize win_flex stdint.h logic
Since this logic was written, we've moved to require C11, so this can
now be simplified. First of all, we no longer need to set
__STDC_VERSION__ for C code at all, because the issue that MSVC doesn't
set __STDC_VERSION__ for C99 is longer a concern. Second, we can make
the C++ check unconditional.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>
Erik Faye-Lund [Tue, 31 May 2022 06:54:30 +0000 (08:54 +0200)]
intel: remove stale makefile
When this landed, the Autotools build system was already removed. Why
was this file added in the first place? Probably a rebase-mistake...
Fixes:
134e750e16b ("i965: extract performance query metrics")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16790>
Erik Faye-Lund [Tue, 31 May 2022 05:27:42 +0000 (07:27 +0200)]
freedreno: remove stale makefile
We don't use this makefile, so there's no point in keeping it in the
repo. It's also a generated one, so it contains a lot of... mess.
Fixes:
536f43cb96b ("freedreno: slurp in afuc")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16790>
Erik Faye-Lund [Tue, 31 May 2022 07:03:19 +0000 (09:03 +0200)]
radeonsi: port amdgcn_glslc build to meson
Seems nice to reduce the number of old-fashioned build systems we have
in-tree.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16789>
Martin Roukala (né Peres) [Thu, 2 Jun 2022 05:42:29 +0000 (08:42 +0300)]
radv/ci: try to guess failure expectations for Fiji/Raven/Navi14/Navi22
The guesses are based on other gpus from the same gfx version. We will
need actual runs on the GPUs to confirm this.
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16810>
Martin Roukala (né Peres) [Thu, 2 Jun 2022 05:25:13 +0000 (08:25 +0300)]
radv/ci: remove an expected fail from all families
dEQP-VK.glsl.builtin.precision_double.determinant.compute.mat3 was
failing because of a CTS bug, which got fixed in the latest update for
all our CI machines.
This commit assumes this got fixed for all families, even the ones we
did not try to run on.
Fixes:
836ce97f5e (ci: bump VK-GL-CTS to 1.3.2.0)
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16810>
Martin Roukala (né Peres) [Wed, 1 Jun 2022 11:37:24 +0000 (14:37 +0300)]
radv/ci: update the vkcts expectations for the CI machines
Fixes:
836ce97f5e (ci: bump VK-GL-CTS to 1.3.2.0)
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16810>
Martin Roukala (né Peres) [Wed, 1 Jun 2022 11:43:03 +0000 (14:43 +0300)]
radv/ci: bump the timeout of vangogh/renoir
The execution time of vkcts has drastically changed with the latest
update, especially for APUs. This commit bumps the timeout to give
them a chance to finish.
Fixes:
836ce97f5e (ci: bump VK-GL-CTS to 1.3.2.0)
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16810>
Samuel Pitoiset [Tue, 12 Apr 2022 10:38:24 +0000 (12:38 +0200)]
radv: fix lowering GS intrinsics if NGG is disabled per pipeline
If NGG is disabled per pipeline for extreme (or suboptimal) geometry
or with transform feedback, make sure to not lower GS intrinsics that
are only needed for NGG GS. This means we have to lower GS intrinsics
later in the compilation process to effectively know if the pipeline
uses NGG.
fossils-db (Navi21):
Totals from 8 (0.01% of 134913) affected shaders:
VGPRs: 512 -> 520 (+1.56%)
CodeSize: 58180 -> 65080 (+11.86%); split: -0.04%, +11.90%
MaxWaves: 128 -> 126 (-1.56%)
Instrs: 10525 -> 11779 (+11.91%); split: -0.05%, +11.96%
Latency: 62941 -> 49428 (-21.47%); split: -21.59%, +0.12%
InvThroughput: 16121 -> 12950 (-19.67%); split: -19.96%, +0.29%
VClause: 122 -> 123 (+0.82%); split: -0.82%, +1.64%
SClause: 130 -> 143 (+10.00%)
Copies: 566 -> 596 (+5.30%); split: -0.35%, +5.65%
Branches: 200 -> 208 (+4.00%)
PreSGPRs: 424 -> 422 (-0.47%)
PreVGPRs: 430 -> 424 (-1.40%); split: -1.63%, +0.23%
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15885>
Dylan Baker [Wed, 1 Jun 2022 23:55:26 +0000 (16:55 -0700)]
docs: update calendar and link releases notes for 22.0.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16828>
Dylan Baker [Wed, 1 Jun 2022 23:54:36 +0000 (16:54 -0700)]
docs: update sha256 for 22.0.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16828>
Dylan Baker [Wed, 1 Jun 2022 21:52:05 +0000 (14:52 -0700)]
docs: add release notes for 22.0.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16828>
Dylan Baker [Wed, 1 Jun 2022 23:55:17 +0000 (16:55 -0700)]
docs: update calendar and link releases notes for 22.1.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16828>
Dylan Baker [Wed, 1 Jun 2022 21:48:35 +0000 (14:48 -0700)]
docs: Add sh256sums for 22.1.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16828>
Dylan Baker [Wed, 1 Jun 2022 21:09:10 +0000 (14:09 -0700)]
docs: add release notes for 22.1.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16828>
Jesse Natalie [Thu, 28 Apr 2022 20:53:58 +0000 (13:53 -0700)]
wgl, d3d12: Handle front buffer writes for double-buffered MSAA surfaces backed by swapchains
We don't need to go as far as the fake front thing when MSAA is being used, because the
swapchain (single-sampled) is already decoupled from the app render buffers. But we do
need to direct the frontbuffer flush to the single-sampled back buffer, and then present
the back buffer. We also need to swap the buffers when we do this, so the next blit
targets the former front buffer.
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16227>
Emma Anholt [Thu, 19 May 2022 20:41:34 +0000 (13:41 -0700)]
freedreno/ir3: Fold 16-bit conversions into image load/store src/dsts.
Shaves 5 instructions off of one manhattan31 shader.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
Emma Anholt [Tue, 31 May 2022 19:49:27 +0000 (12:49 -0700)]
freedreno/ir3: Fix validation of half-precision image store values.
ce1a381e57d2 ("turnip: enable VK_KHR_16bit_storage on A650") determined
that the type of the instr decided the type of the value being stored in
the ".b" case. But it would be surprising if image stores had the type
determine the coordinates' precision instead of the value's, and once we
turned on image instruction precision lowering we ran into asserts.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
Matt Turner [Mon, 22 Feb 2021 20:11:14 +0000 (20:11 +0000)]
freedreno/ir3: Pass 16-bit sampler coordinates when possible.
shader-db highlights from Rob's android shaders:
total instructions in shared programs: 769641 -> 767536 (-0.27%)
instructions in affected programs: 151139 -> 149034 (-1.39%)
total last-baryf in shared programs: 55908 -> 55607 (-0.54%)
last-baryf in affected programs: 35219 -> 34918 (-0.85%)
total sstall in shared programs: 67074 -> 65767 (-1.95%)
total full in shared programs: 36115 -> 36080 (-0.10%)
full in affected programs: 203 -> 168 (-17.24%)
sstall in affected programs: 9510 -> 8203 (-13.74%)
total (ss) in shared programs: 14380 -> 14239 (-0.98%)
(ss) in affected programs: 2965 -> 2824 (-4.76%)
total systall in shared programs: 92425 -> 91522 (-0.98%)
systall in affected programs: 13146 -> 12243 (-6.87%)
total (sy) in shared programs: 4330 -> 4314 (-0.37%)
(sy) in affected programs: 167 -> 151 (-9.58%)
total waves in shared programs: 71580 -> 71584 (<.01%)
waves in affected programs: 12 -> 16 (33.33%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
Emma Anholt [Tue, 31 May 2022 21:35:58 +0000 (14:35 -0700)]
freedreno/ir3: Make the types of tex coord padding match.
Required for lowering of coords to be 16-bit.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
Matt Turner [Fri, 19 Feb 2021 20:30:05 +0000 (20:30 +0000)]
freedreno/ir3: Move the texture array coord fixup to nir
We're going to optimize sampler coordinates to FP16, so we'll need to
add the appropriately typed 0.5. Move this to NIR where that information
is readily available.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
Emma Anholt [Thu, 19 May 2022 19:40:18 +0000 (12:40 -0700)]
freedreno/ir3: Enable load/store vectorization for SSBO access, too.
Saves a few ldib/stib instructions in gfxbench vk-5-normal compute shaders
by grouping vec4 accesses together.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
Emma Anholt [Thu, 19 May 2022 20:26:33 +0000 (13:26 -0700)]
nir_lower_mediump: Drop assertion about not containing movs.
A 1D texture operation may need to do a mov to turn a reference to a
channel of an SSA value into a scalar value to be passed as the texture
coordinate (since texture srcs can't do swizzles). Seen in
amnesia-the-dark-descent/low/46.shader_test() for example, where a 1D
texture is used to remap each of r,g,b from a previous texture result.
Besides, the nir_op_is_vec() case will (perhaps surprisingly) look through
a mov, anyway.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
Emma Anholt [Wed, 1 Jun 2022 22:15:24 +0000 (15:15 -0700)]
ci/turnip: Add missing xfails for a618 full VK run
Fixes:
836ce97f5ea8 ("ci: bump VK-GL-CTS to 1.3.2.0")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
Yiwei Zhang [Fri, 27 May 2022 23:02:49 +0000 (23:02 +0000)]
venus: resolve AHARDWAREBUFFER_FORMAT_Y8Cb8Cr8_420 to external format
This is to work around ANGLE yuv support.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16759>
Alyssa Rosenzweig [Thu, 26 May 2022 16:09:54 +0000 (12:09 -0400)]
pan/bi: Respect swizzles in nir_op_pack_64_2x32_split
Triggered a BIR validation error, which made debugging a breeze. That validation
pass (dimensionality checks) gets a lot of use, it seems :-)
Fixes:
dEQP-VK.ssbo.layout.2_level_array.std430.row_major_mat4x2_comp_access_store_cols
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16724>
Alyssa Rosenzweig [Thu, 26 May 2022 16:29:06 +0000 (12:29 -0400)]
panvk: Use vk_image_subresource_*_count for clears
This handles VK_REMAINING_* for us, instead of underflowing and clearing no
levels/layers.
Fixes dEQP-VK.api.image_clearing.core.clear_color_image.2d.linear.single_layer.*
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16724>
Alyssa Rosenzweig [Tue, 17 May 2022 15:13:59 +0000 (11:13 -0400)]
panfrost: Allow 2D AFBC on Valhall
2D AFBC should be working now, flip the switch. 3D AFBC needs more research to
get right, honestly it's not clear how 3D AFBC on Bifrost is working...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>
Alyssa Rosenzweig [Tue, 17 May 2022 18:27:44 +0000 (14:27 -0400)]
panfrost: Handle texturing from AFBC on Valhall
We need to pack special AFBC-specific plane descriptors instead of the generic
plane descriptor. Nothing too fancy here, though.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>
Alyssa Rosenzweig [Tue, 17 May 2022 18:27:09 +0000 (14:27 -0400)]
panfrost: Support rendering to AFBC on Valhall
Add the required handling when packing render target and depth buffer
descriptors on Valhall. This is mostly equivalent to Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>
Alyssa Rosenzweig [Tue, 17 May 2022 18:25:58 +0000 (14:25 -0400)]
panfrost: Add pan_afbc_compression_mode on Valhall
Map a canonical format (a hardware-independent pipe_format) to a compression
mode (Valhall-specific hardware enum defined in GenXML). To be used for packing
plane descriptors and render target descriptors when AFBC is in use on Valhall.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>
Alyssa Rosenzweig [Tue, 17 May 2022 18:22:09 +0000 (14:22 -0400)]
panfrost: Pass arch instead of dev into afbc_format
For callers that have a device object, it's easy to pass dev->arch instead of
dev. But this requires callers to have a reference to the device, which is
tricky for callers that only have the arch via PAN_ARCH. Pass dev->arch instead
of dev to accommodate them.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>
Alyssa Rosenzweig [Wed, 1 Jun 2022 18:34:08 +0000 (14:34 -0400)]
panfrost: Fix XML for AFBC header on v9
Misnamed field due to copy/paste fail from Bifrost.
Fixes:
c011ea6c265 ("panfrost: Shuffle render target AFBC for Valhall")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>
Alyssa Rosenzweig [Tue, 31 May 2022 13:18:46 +0000 (09:18 -0400)]
pan/mdg: Print outmods when printing IR
In particular, this lets us distinguish mul_high from regular mul.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
Alyssa Rosenzweig [Tue, 31 May 2022 13:08:23 +0000 (09:08 -0400)]
pan/mdg: Distinguish SSA vs reg when printing IR
This makes it easy to match the printed IR with the indices in the NIR.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
Alyssa Rosenzweig [Tue, 31 May 2022 12:43:33 +0000 (08:43 -0400)]
pan/mdg: Only print 1 source for moves
This makes the printed IR easier to read at a glance.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
Alyssa Rosenzweig [Tue, 31 May 2022 12:41:03 +0000 (08:41 -0400)]
pan/mdg: Only print 2 sources for ALU
..and assert the other sources are null. The one place this might fail in the
future is for real FMA, but we don't support that for GL.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
Alyssa Rosenzweig [Tue, 31 May 2022 12:37:33 +0000 (08:37 -0400)]
pan/mdg: Only print masked components of swizzle
This matches the IR printer with the disassembler, making the output of the IR
printer much easier to parse at a glance.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
Alyssa Rosenzweig [Thu, 19 May 2022 16:11:32 +0000 (12:11 -0400)]
pan/mdg: Use "<<" instead of "lsl"
Easier to read and consistent with C code.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
Alyssa Rosenzweig [Thu, 19 May 2022 16:08:46 +0000 (12:08 -0400)]
pan/mdg: Remove uppercase write masks
These do not convey any additional information, and fail to account for
shrinking. In particular, a 64-bit writemask with .keephi would fail to
disassemble and instead trip the assertion, since that would be the ZW
components. Just delete the broken code.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
Alyssa Rosenzweig [Thu, 19 May 2022 16:29:01 +0000 (12:29 -0400)]
pan/mdg: Scalarize with 64-bit sources
Otherwise, we can get vec3 with u2u32 with 64-bit sources which we need lowered.
Since our current approach is "scalarize all 64-bit ops", we need to check for
conversions too.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
Georg Lehmann [Thu, 20 Jan 2022 19:50:15 +0000 (20:50 +0100)]
radv, aco: Packed usub_sat/isub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Sat, 20 Nov 2021 16:18:28 +0000 (17:18 +0100)]
radv: Enable VK_INTEL_shader_integer_functions2.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Sat, 20 Nov 2021 13:33:20 +0000 (14:33 +0100)]
radv: Lower 8bit isub_sat/usub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Fri, 19 Nov 2021 13:56:07 +0000 (14:56 +0100)]
radv: Lower hadd/hradd.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Fri, 19 Nov 2021 21:58:41 +0000 (22:58 +0100)]
radv: Lower mul_32x16.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Fri, 19 Nov 2021 21:38:30 +0000 (22:38 +0100)]
nir: Add optional lowering for mul_32x16.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Sat, 20 Nov 2021 20:11:57 +0000 (21:11 +0100)]
ac/llvm: Implement uclz.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Sat, 20 Nov 2021 19:45:57 +0000 (20:45 +0100)]
ac/llvm: Implement usub_sat and isub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Fri, 19 Nov 2021 15:43:31 +0000 (16:43 +0100)]
aco: Implement isub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Fri, 19 Nov 2021 15:28:52 +0000 (16:28 +0100)]
aco: Implement usub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Fri, 19 Nov 2021 13:27:06 +0000 (14:27 +0100)]
aco: Implement uclz.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Danylo Piliaiev [Wed, 1 Jun 2022 15:32:27 +0000 (18:32 +0300)]
ir3: Force late-z if FS has global store/atomic
No known tests are fixed.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16816>
Alyssa Rosenzweig [Thu, 19 May 2022 20:10:44 +0000 (16:10 -0400)]
pan/bi: Use flow control lowering on Valhall
Logically at the same part of the compile pipeline as clause scheduling on
Bifrost. Lots of similarities, too. Now that we generate flow control only as a
late pass, various hacks in the compiler are no longer necessary and are
dropped.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Fri, 20 May 2022 16:30:59 +0000 (12:30 -0400)]
pan/va: Unit test flow control merging
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Thu, 19 May 2022 20:58:36 +0000 (16:58 -0400)]
pan/va: Unit test flow control insertion
Test that we correctly track the scoreboard, helper invocations, reconvergence,
and ends and insert NOPs to effect this expected flow control.
As the pass inserts NOPs but does not otherwise modify the shader, this is easy
to test with well-defined behaviour of the pass.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Wed, 25 May 2022 13:40:02 +0000 (09:40 -0400)]
pan/va: Respect assigned slots
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Wed, 25 May 2022 13:39:44 +0000 (09:39 -0400)]
pan/va: Assign slots roundrobin
This should reduce false dependencies with asynchronous instructions.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Fri, 20 May 2022 16:31:12 +0000 (12:31 -0400)]
pan/va: Add flow control merging pass
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Tue, 31 May 2022 19:12:13 +0000 (15:12 -0400)]
pan/va: Terminate helper threads
On Bifrost, to terminate helper threads we set the td bit on the clause. On
Valhall, we need to use the .discard flow control. Extend the flow control NOP
insertion to insert NOP.discard where necessary to terminate helper threads.
This should reduce wasted work in fragment shaders.
This requires fairly involved data flow analysis, but the handling here should
be optimal.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Thu, 19 May 2022 23:08:23 +0000 (19:08 -0400)]
pan/va: Do scoreboard analysis
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Thu, 19 May 2022 20:57:31 +0000 (16:57 -0400)]
pan/va: Add pass to insert flow control
To set flow control modifiers correctly and efficiently, we need a pass that
runs after register allocation and scheduling, but before packing. Add such a
pass.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>