Philip Reames [Wed, 7 Dec 2022 18:24:48 +0000 (10:24 -0800)]
[RISCV][InsertVSETVLI] Generalize scalar move rule for when AVL is unchanged
By definition, the AVL of the scalar move is equally zero to the prior AVL if they are the same value. This generalizes the existing code to the case where the scalar move has a register AVL which is unknown, but unchanged from the preceeding instruction.
This doesn't cause any interesting diffs on its own, but another patch makes this case much more common. Split off to reduce a future diff.
Brett Wilson [Wed, 7 Dec 2022 18:22:05 +0000 (10:22 -0800)]
Revert "[clang-doc] Add template support."
Causes a build failure in YAML specializations.
This reverts commit
0f6dbb5f164662c3e6a167a89e7a89f07c60e32b.
Craig Topper [Wed, 7 Dec 2022 18:03:51 +0000 (10:03 -0800)]
[RISCV] Remove pseudos for whole register load, store, and move.
The MC layer instructions have the correct register classes, and
the pseudos don't have any additional operands. So there doesn't
seem to be any reason for them to exist.
The pseudos were incorrectly going through code in RISCVMCInstLower
that converted LMUL>1 register classes to LMUL1 register class.
This makes the MCInst technically malformed, and prevented the
vl2r.v, vl4r.v, and vl8r.v InstAliases from matching. This accounts
for all of the .ll test diffs.
Differential Revision: https://reviews.llvm.org/D139511
Haojian Wu [Wed, 7 Dec 2022 17:59:17 +0000 (18:59 +0100)]
Fix an -Wunused-variable warning in release build, NFC
Simon Pilgrim [Wed, 7 Dec 2022 17:50:28 +0000 (17:50 +0000)]
[llvm-exegesis][x86] Add option to prevent use of xmm8-xmm15 upper SSE registers
Noticed while trying to use llvm-exegesis to get some accurate capture numbers on some old Atom/Silverment hardware as part of the work with D103695.
These targets' frontends are particularly poor and the use of the xmm8-xmm15 SSE registers results in longer instruction encodings which were affecting the latency/throughput estimates.
Thanks to @lebedev.ri for the --skip-measurements command line argument which made testing much easier!
Differential Revision: https://reviews.llvm.org/D138832
Roman Lebedev [Wed, 7 Dec 2022 17:42:33 +0000 (20:42 +0300)]
[NFC] Port all (but one) LICM tests to `-passes=` syntax
Nikolas Klauser [Thu, 1 Dec 2022 22:17:53 +0000 (23:17 +0100)]
[libc++] Implement P0339R6 (polymorphic_allocator<> as a vocabulary type)
Reviewed By: ldionne, #libc
Spies: LRFLEW, libcxx-commits, arichardson, krytarowski, jdoerfert
Differential Revision: https://reviews.llvm.org/D137739
Brett Wilson [Mon, 7 Nov 2022 23:07:56 +0000 (15:07 -0800)]
[clang-doc] Add template support.
Reads template information from the AST and adds template parameters and
specialization information to the corresponding clang-doc structures.
Add a "QualName" to the Reference struct which includes the full
qualified type name. The Reference object represents a link in the
HTML/MD generators so is based on the unqualified name. But this does
not encode C-V qualifiers or template information that decorate the
name. The new QualName member encodes all of this information and also
makes it easier for the generators or downsteam YAML consumers to
generate the full name (before they had to process the "Path").
In test code that was changed, remove made-up paths to built-in types
like "int". In addition to slightnly cleaning up the code, these types
do not have paths in real execution, and generating incorrect references
to nonexistant data may complicate future changes in the generators.
Differential Revision: https://reviews.llvm.org/D139154
Mitch Phillips [Wed, 7 Dec 2022 17:46:22 +0000 (09:46 -0800)]
Disable flaky MLIR async.mlir test on ASan.
Test keeps flaking on the ASan buildbot:
https://github.com/llvm/llvm-project/issues/57231
Craig Topper [Wed, 7 Dec 2022 17:33:40 +0000 (09:33 -0800)]
[RISCV] Replace uses of hasStdExtC with COrZca.
Except MakeCompressible which will need more work.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D139504
Mirko Brkusanin [Wed, 7 Dec 2022 17:20:41 +0000 (18:20 +0100)]
[AMDGPU][GlobalISel] Fix legalizing image intrinsics for new types
We no longer need to increase vector size to 16 for intrinsics that use more
than 8 vgprs for addr. There is no image intrinsic that needs more than 12
so all currently existing cases will be covered. Using incorrect size was
causing an error in instruction selection because instructions were updated
to require new types (9x32, 10x32, 11x32, 12x32).
Differential Revision: https://reviews.llvm.org/D139546
Roman Lebedev [Wed, 7 Dec 2022 17:14:13 +0000 (20:14 +0300)]
[llvm-exegesis] Dry run mode
Sometimes we only want to ensure that we can produce snippets (all the way
through `SnippetRepetitor`!), but don't care for the execution.
E.g. all of our tests are this way.
I've built LLVM without PFM and removed my CPU from `X86PfmCounters.td`,
and this produces the expected results in that configuration.
Reviewed By: courbet
Differential Revision: https://reviews.llvm.org/D139448
Roman Lebedev [Wed, 7 Dec 2022 16:43:17 +0000 (19:43 +0300)]
[NFC] Port all (but one) LoopUnroll tests to `-passes=` syntax
Mitch Phillips [Wed, 7 Dec 2022 16:50:33 +0000 (08:50 -0800)]
Fix dwarf5-lazy-dwo.c for the default c target not being c99.
My host compiler is clang version 15.0.0, which uses -std=c11 by
default. The test asserts that the language is 'c99', and so the test
fails locally.
Update the test to be explicit about compiling with 'c99'.
Reviewed By: Eric
Differential Revision: https://reviews.llvm.org/D139461
LLVM GN Syncbot [Wed, 7 Dec 2022 16:50:20 +0000 (16:50 +0000)]
[gn build] Port
d184958bad5c
Krzysztof Parzyszek [Wed, 7 Dec 2022 16:18:35 +0000 (08:18 -0800)]
[IRReader] Convert Optional in DataLayoutCallbackTy to std::optional
Joe Nash [Wed, 7 Dec 2022 16:34:58 +0000 (11:34 -0500)]
[AMDGPU] Add gfx11 runline to omod test. NFC
Phoebe Wang [Wed, 7 Dec 2022 16:17:45 +0000 (00:17 +0800)]
[X86] Pre-commit test for pr59305
Mark de Wever [Wed, 19 Oct 2022 17:50:48 +0000 (19:50 +0200)]
[libc++][format] Adds range-default-formatter.
This adds an incomplete version where the specializations for the
format_kinds are disabled dummy formatters.
Implements part of
- P2585R0 Improving default container formatting
Reviewed By: ldionne, #libc
Differential Revision: https://reviews.llvm.org/D137271
serge-sans-paille [Wed, 7 Dec 2022 16:15:14 +0000 (17:15 +0100)]
Revert "Store OptTable::Info::Name as a StringRef"
Another revert, for another set of issues I don't reproduce locally...
see https://lab.llvm.org/buildbot/#/builders/139/builds/32327
This reverts commit
bdfa3100dc3ea9e9ce4d3d4100ea6bb4c3fa2b81.
Dmitry Kurtaev [Wed, 7 Dec 2022 16:19:33 +0000 (08:19 -0800)]
[RISCV][JitLink] Propagate error from Expected<T> result during R_RISCV_PCREL_HI20 parsing
related issue: https://github.com/llvm/llvm-project/issues/59139
Differential Revision: https://reviews.llvm.org/D138781
Yitzhak Mandelbaum [Mon, 5 Dec 2022 20:38:55 +0000 (20:38 +0000)]
[clang][dataflow] Support (in)equality operators in `optional` model.
This patch adds interpretation of the overloaded equality and inequality
operators available for the optional types.
Fixes issue #57253.
Differential Revision: https://reviews.llvm.org/D139360
Emilio Cota [Tue, 6 Dec 2022 15:30:06 +0000 (10:30 -0500)]
[mlir][bufferize] lower allocation alignment from 128 to 64 bytes
While it is unlikely to matter in practice, there is no reason
for this value to be larger than it should be. 64 bytes is the
size of a cache line in most machines, and we can fit a full
512-bit vector in it.
Reviewed By: springerm
Differential Revision: https://reviews.llvm.org/D139434
Doru Bercea [Tue, 6 Dec 2022 19:07:57 +0000 (13:07 -0600)]
Automate tests.
chenglin.bi [Wed, 7 Dec 2022 15:54:23 +0000 (23:54 +0800)]
[InstCombine] fold more icmp + select patterns by distributive laws
follow up D139076, add icmp with not only eq/ne, but also gt/lt/ge/le.
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D139253
chenglin.bi [Wed, 7 Dec 2022 02:16:22 +0000 (10:16 +0800)]
[Instcombine] Canonicalize ~((A & B) ^ (A | ?)) -> (A & B) | ~(A | ?)
~((A & B) ^ (A | ?)) -> (A & B) | ~(A | ?)
https://alive2.llvm.org/ce/z/JHN2p4
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D139299
serge-sans-paille [Sun, 4 Dec 2022 08:33:14 +0000 (09:33 +0100)]
Store OptTable::Info::Name as a StringRef
This is a recommit of
8ae18303f97d5dcfaecc90b4d87effb2011ed82e,
with a few cleanups.
This avoids implicit conversion to StringRef at several points, which in
turns avoid redundant calls to strlen.
As a side effect, this greatly simplifies the implementation of
StrCmpOptionNameIgnoreCase.
It also eventually gives a consistent, humble speedup in compilation
time (timing updated since original commit).
https://llvm-compile-time-tracker.com/compare.php?from=
76fcfea283472a80356d87c89270b0e2d106b54c&to=
b70eb1f347f22fe4d2977360c4ed701eabc43994&stat=instructions:u
Differential Revision: https://reviews.llvm.org/D139274
Daniel Kiss [Wed, 7 Dec 2022 14:45:42 +0000 (15:45 +0100)]
[AArch64] Add __ARM_FEATURE_BTI and __ARM_FEATURE_PAUTH
Macros are added to ACLE[1] and already added to ARM but these two are missing from AArch64.
[1] https://github.com/ARM-software/acle/blob/main/main/acle.md#changes-between-acle-q3-2021-and-acle-q4-2021
Reviewed By: chill
Differential Revision: https://reviews.llvm.org/D139445
Matthias Springer [Wed, 7 Dec 2022 15:22:07 +0000 (16:22 +0100)]
[mlir][tensor] Support parallel_insert_slice in reassociative reshape folder
Differential Revision: https://reviews.llvm.org/D139540
Hans Wennborg [Tue, 6 Dec 2022 14:21:43 +0000 (15:21 +0100)]
Handle char{8,16,32} and wchar_t in ASTContext::getIntegerRank()
They were previously not handled, causing the llvm_unreachable with
"getIntegerRank(): not a built-in integer" message to be hit.
The test case is derived from how we hit it in Chromium
(crbug.com/1396142). I tried to come up with something more direct, but
this is the best I could find.
Differential revision: https://reviews.llvm.org/D139428
Jens Massberg [Thu, 1 Dec 2022 16:49:41 +0000 (17:49 +0100)]
[clang] Correctly handle by-reference capture with an initializer that is a pack expansion in lambdas.
Ensure that the correct information whether an init-capture of a lambda
is passed by reference or by copy. This information is already computed
and has to be passed to the place where `NewInitCaptureType` is
created.
Before this fix it has been checked whether the VarDecl is a reference
type. This doesn't work for packed expansions, as the information
whether it is passed by reference or by copy is stored at the pattern of
a `PackExpansionType` and not at the type itself.
However, as the information has been already computed, we just have to
pass it.
Add tests that lambda captures with var decls which are reference types
are created in the AST and a disgnotics test for pack expansions.
Fixes #49266
Differential Revision: https://reviews.llvm.org/D139125
Guillaume Chatelet [Wed, 7 Dec 2022 14:54:03 +0000 (14:54 +0000)]
[reland][Alignment] Use Align in MCStreamer emitZeroFill/emitLocalCommonSymbol
Before performing this change, I checked that `ByteAlignment` was never `0` inside `MCAsmStreamer:emitZeroFill` and `MCAsmStreamer::emitLocalCommonSymbol`.
I believe it is NFC as `0` values are illegal in `emitZeroFill` anyways, `Log2(ByteAlignment)` would be undefined.
And currently, all calls to `emitLocalCommonSymbol` are provably `>0`.
Differential Revision: https://reviews.llvm.org/D139439
Guillaume Chatelet [Wed, 7 Dec 2022 14:48:40 +0000 (14:48 +0000)]
Revert D139439 "[Alignment] Use Align in MCStreamer emitZeroFill/emitLocalCommonSymbol"
This breaks Windows bots with
`warning C4334: '<<': result of 32-bit shift implicitly converted to 64 bits (was 64-bit shift intended?)`
Some shift operators are lacking a proper literal unit ('1ULL' instead of
'1'). Will reland once fixed.
This reverts commit
c621c1a8e81856e6bf2be79714767d80466e9ede.
Nikita Popov [Wed, 7 Dec 2022 14:31:17 +0000 (15:31 +0100)]
[SCEV] Use umin_seq for symbolic max BE count
We were using umin_seq when computing the exact BE count, but not
when computing the symbolic max BE count.
Will Dietz [Tue, 6 Dec 2022 20:44:12 +0000 (14:44 -0600)]
[mlir][Pass] Fix dropped statistics with nested adaptors.
When running in parallel, nesting more than once caused
statistics to be dropped.
Fix by also preparing "async" pass managers before merging,
as they may also have "async" pass managers within.
Add test checking reported statistics have expected values
with and without threading enabled.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D139459
Guillaume Chatelet [Tue, 6 Dec 2022 15:50:02 +0000 (15:50 +0000)]
[Alignment] Use Align in MCStreamer emitZeroFill/emitLocalCommonSymbol
Before performing this change, I checked that `ByteAlignment` was never `0` inside `MCAsmStreamer:emitZeroFill` and `MCAsmStreamer::emitLocalCommonSymbol`.
I believe it is NFC as `0` values are illegal in `emitZeroFill` anyways, `Log2(ByteAlignment)` would be undefined.
And currently, all calls to `emitLocalCommonSymbol` are provably `>0`.
Differential Revision: https://reviews.llvm.org/D139439
Nikita Popov [Wed, 7 Dec 2022 14:25:02 +0000 (15:25 +0100)]
[SCEV] Add another symbolic BE count test (NFC)
Simon Pilgrim [Wed, 7 Dec 2022 14:21:18 +0000 (14:21 +0000)]
[X86] combine-and.ll - add some 256/512-bit test coverage for D138521
Simon Pilgrim [Wed, 7 Dec 2022 14:17:42 +0000 (14:17 +0000)]
[X86] combine-and.ll - add AVX1 test coverage
Simon Pilgrim [Wed, 7 Dec 2022 14:16:41 +0000 (14:16 +0000)]
X86SelectionDAGInfo.cpp - move dyn_cast check inside if(). NFC.
Minor cleanup - we only use the non-null pointer inside the if() block
Daniel Kiss [Wed, 7 Dec 2022 14:19:31 +0000 (15:19 +0100)]
Revert "[AArch64] Add __ARM_FEATURE_BTI and __ARM_FEATURE_PAUTH"
This reverts commit
cfd44221e3e1783c0f44d5b1694dfbe84187246a.
Florian Hahn [Wed, 7 Dec 2022 14:12:44 +0000 (14:12 +0000)]
[ConstraintElim] Address comments from D137840.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D139482
Krzysztof Parzyszek [Wed, 7 Dec 2022 01:51:30 +0000 (19:51 -0600)]
[Remarks] Convert Optional to std::optional
Nico Weber [Wed, 7 Dec 2022 14:00:20 +0000 (09:00 -0500)]
[llvm] Auto-cleanup left-over file from earlier version of this test on bots
When this test was originally added in
991dfedfd738ce, it didn't pass
`-o` to to llc, causing llc to write a .s file to the source directory.
On the next run, lit would then try to run that as a test.
Make the test auto-cleanup that file for a while.
Quentin Colombet [Wed, 7 Dec 2022 10:17:26 +0000 (10:17 +0000)]
[mlir][NFC] Add a new getStridesAndOffset function
The new function is a wrapper around the regular `getStridesAndOffset`
that offers a more compact way (as in writing less code) of getting the
relevant information.
This method is intended to be used only when it is known that the
LogicalResult of the regular `getStridesAndOffset` must be "succeeded".
This warpper will assert on that.
Differential Revision: https://reviews.llvm.org/D139529
Daniel Kiss [Wed, 7 Dec 2022 13:52:11 +0000 (14:52 +0100)]
[AArch64] Add __ARM_FEATURE_BTI and __ARM_FEATURE_PAUTH
Macros are added to ACLE[1] and already added to ARM but these two are missing from AArch64.
[1] https://github.com/ARM-software/acle/blob/main/main/acle.md#changes-between-acle-q3-2021-and-acle-q4-2021
Reviewed By: chill
Differential Revision: https://reviews.llvm.org/D139445
Jean Perier [Wed, 7 Dec 2022 13:45:41 +0000 (14:45 +0100)]
[flang] Lower parentheses with hlfir.as_expr and hlfir.no_reassoc
Differential Revision: https://reviews.llvm.org/D139523
Jean Perier [Wed, 7 Dec 2022 13:44:29 +0000 (14:44 +0100)]
[flang] add hlfir.no_reassoc definition
Same as fir.no_reassoc but accepts hlfir.expr type. It is needed because
FIR operation can only produce FIR types, and I do not want to change
that for now.
Depends on D139519
Differential Revision: https://reviews.llvm.org/D139520
Jean Perier [Wed, 7 Dec 2022 13:43:29 +0000 (14:43 +0100)]
[flang] Add hlfir.as_expr definition
hlfir.as_expr allows taking a value from a character, derived type,
or array expressions. This will allow implementing parentheses.
Combining as_expr + hlfir.associate will allow creating a variable copy
into a new temporary variable.
A later patch will add the ability to "move" a variable into an
expression (to give ownership of the variable storage to the expression,
with the commitment that the variable will not be used anymore).
Differential Revision: https://reviews.llvm.org/D139519
Nico Weber [Tue, 6 Dec 2022 15:28:08 +0000 (10:28 -0500)]
[compiler-rt] Make get_test_cc_for_arch() complain on accidental extra args
This would've helped find the bug mentioned in
9531fc37fb8b84e4
faster.
Differential Revision: https://reviews.llvm.org/D139432
Nico Weber [Wed, 7 Dec 2022 13:24:34 +0000 (08:24 -0500)]
[gn build] Port
c9b325088d14
Peixin Qiao [Wed, 7 Dec 2022 13:24:01 +0000 (21:24 +0800)]
[flang] Support codegen for global procedure pointer
This supports the codegen for global procedure pointer in BoxedProcedure
pass. Reset the boxproc type.
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D138273
Peixin Qiao [Wed, 7 Dec 2022 13:21:08 +0000 (21:21 +0800)]
[flang] Support codegen of procedure pointer component
This supports the codegen for procedure pointer component in
BoxedProcedure pass. Also fix the FIR in ProcedurePointer.md so that
all the cases can be run using `tco` to generate the LLVM IR.
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D136842
Jay Foad [Wed, 7 Dec 2022 11:28:54 +0000 (11:28 +0000)]
[AMDGPU] Use SOP_Pseudo more consistently. NFC.
SOPK_Pseudo was not inheriting from SOP_Pseudo at all, and some other
Pseudo classes were needlessly redefining things that were already
defined by SOP_Pseudo.
Differential Revision: https://reviews.llvm.org/D139527
Ilya Biryukov [Wed, 7 Dec 2022 12:53:14 +0000 (13:53 +0100)]
[clangd] Fix a typo in -ranking-model documentation. NFC
Ilya Biryukov [Wed, 7 Dec 2022 12:50:47 +0000 (13:50 +0100)]
[clangd] Allow to build Clangd without decision forest
Make it possible to disable building the decision forest ranking
model for clangd. To unbreak build of Clangd on PPC32 in gentoo, see
https://bugs.gentoo.org/829602
Based on D138520.
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D139107
LLVM GN Syncbot [Wed, 7 Dec 2022 12:44:01 +0000 (12:44 +0000)]
[gn build] Port
cb5b25c58783
Nico Weber [Sat, 3 Dec 2022 12:52:00 +0000 (07:52 -0500)]
[gn build] port
d62480c1995b (LoongArchTests)
Max Kazantsev [Wed, 7 Dec 2022 12:27:57 +0000 (19:27 +0700)]
[Test] Add a test where we expect to see symbolic max as umin_seq
Haojian Wu [Wed, 7 Dec 2022 12:23:53 +0000 (13:23 +0100)]
Fix a typo ll->llc in test
Haojian Wu [Wed, 7 Dec 2022 11:18:32 +0000 (12:18 +0100)]
Add implementation isTargetCanonicalConstantNode for hexagon.
This fixes an infinite compiling loop caused by https://reviews.llvm.org/D137140
Differential Revision: https://reviews.llvm.org/D139525
Stephen Thomas [Wed, 7 Dec 2022 11:02:16 +0000 (11:02 +0000)]
[AMDGPU] Small cleanup in insertWaitcntInBlock()
Move some code that checks if an instruction is a waitcount into a separate
function, mainly to aid readability in the logic where it is used.
Differential Revision: https://reviews.llvm.org/D139522
Janek van Oirschot [Tue, 6 Dec 2022 20:36:07 +0000 (20:36 +0000)]
[AMDGPU] G_IS_FPCLASS lower() support for IEEE fp types
Simplified globalisel version of sdag's expandIS_FPCLASS.
Reviewed By: arsenm, #amdgpu
Differential Revision: https://reviews.llvm.org/D139128
Lorenzo Chelini [Mon, 5 Dec 2022 17:31:25 +0000 (18:31 +0100)]
[MLIR][Tensor] Add custom builder for unpack op
Reviewed By: hanchung
Differential Revision: https://reviews.llvm.org/D139344
Matthias Springer [Wed, 7 Dec 2022 11:21:53 +0000 (12:21 +0100)]
[mlir][bufferize] Update remaining getMemorySpaceAsInt API uses
D138330 updated the deprecated `getMemorySpaceAsInt` uses to `getMemorySpace`. There are few uses that were missed.
Differential Revision: https://reviews.llvm.org/D139526
Markus Böck [Wed, 7 Dec 2022 11:24:48 +0000 (12:24 +0100)]
[mlir][tblgen][docs] Use correct introductionary prefix for the Syntax description of attributes and types
The doc generator currently has the use of `!` as prefix hardcoded, despite being incorrect for Attributes. These start with `#`.
This patch fixes that little issue by using `#` for AttrDefs and `!` for TypeDefs in the `Syntax` field of the generated Markdown file.
Differential Revision: https://reviews.llvm.org/D139524
Valentin Clement [Wed, 7 Dec 2022 11:00:41 +0000 (12:00 +0100)]
[flang] Handle polymorphic passed object in host association
Polymorphic entities are always emboxed. This patch
handles host association of polyrmophic entities as passed object.
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D139423
Jean Perier [Wed, 7 Dec 2022 10:59:01 +0000 (11:59 +0100)]
[flang] fir.emboxchar codegen with static length fir.char types
The verifier of fir.emboxchar accepts `fir.char<kind, constant>` types,
but its codegen failed because of a missing cast. It is convenient and
safe to not require making the cast in FIR, so add it in codegen.
Differential Revision: https://reviews.llvm.org/D139514
Max Kazantsev [Wed, 7 Dec 2022 10:31:40 +0000 (17:31 +0700)]
[SCEV] Remember blocks for which we know symbolic exit count but not exact
The old code didn't bother to memoize blocks for which exact exit count is not
known. As result, in situation when exact isn't known but symbolic is known, this
info was lost. This patch fixes the situation: now we memoize when symbolic is
known (exact always implies symbolic, so this is a strict superset of what was before).
Differential Revision: https://reviews.llvm.org/D139515
Reviewed By: nikic
Anton Sidorenko [Fri, 14 Oct 2022 13:20:43 +0000 (16:20 +0300)]
[MachineCombiner] Extend reassociation logic to handle inverse instructions
Machine combiner supports generic reassociation only of associative and
commutative instructions, for example (A + X) + Y => (X + Y) + A. However, we
can extend this generic support to handle patterns like
(X + A) - Y => (X - Y) + A), where `-` is the inverse of `+`.
This patch adds interface functions to process reassociation patterns of
associative/commutative instructions and their inverse variants with minimal
changes in backends.
Differential Revision: https://reviews.llvm.org/D136754
Matthias Springer [Wed, 7 Dec 2022 10:38:44 +0000 (11:38 +0100)]
[mlir][bufferize] Support parallel_insert_slice in EmptyTensorElimination
Differential Revision: https://reviews.llvm.org/D139431
Guillaume Chatelet [Wed, 7 Dec 2022 10:33:31 +0000 (10:33 +0000)]
[libc] Fix warning with -fno-lax-vector-conversions
Wenzel Jakob [Wed, 7 Dec 2022 10:12:53 +0000 (11:12 +0100)]
[llvm-c] Added a C-API binding to query the LLVM version
The LLVM C bindings currently offer no way to query the version string
dynamically. This is a useful feature in situations where a program
isn't compiled against a specific version of LLVM but rather loads it
dynamically (e.g. using dlopen()).
In situations where the shared library filename doesn't reveal the
version (e.g. LLVM-C.dll) and to adapt to version-specific API
differences, it is then useful to be able to query the version string by
calling the proposed LLVMGetVersion function.
Differential Revision: https://reviews.llvm.org/D139381
David Sherwood [Tue, 29 Nov 2022 11:11:31 +0000 (11:11 +0000)]
[SVE] Commonise bfmlal* and fmlal* instruction classes
Given the significant commonality between the bfmlal* and fmlal*
instructions it makes sense to use just a single class for both.
We can do this now that the bfmlal* lane intrinsics take a i32
index.
Differential Revision: https://reviews.llvm.org/D138906
Piotr Sobczak [Fri, 2 Dec 2022 15:30:40 +0000 (16:30 +0100)]
[AMDGPU] Fix wide spills
Update spill code to account for new vector types with
bit widths: 288, 320, 352, 384.
Related to D138205.
Differential Revision: https://reviews.llvm.org/D139203
David Sherwood [Mon, 28 Nov 2022 11:43:51 +0000 (11:43 +0000)]
[SVE] Change some bfloat lane intrinsics to use i32 immediates
Almost all of the other SVE LLVM IR intrinsics take i32 values
for lane indices or other immediates. We should bring the bfloat
intrinsics in line with that. It will also make it easier to
add support for the SVE2.1 float intrinsics in future, since
they reuse the same underlying instruction classes.
I've maintained backwards compatibility with the old i64 variants
and used the autoupgrade mechanism.
Differential Revision: https://reviews.llvm.org/D138788
Chenbing Zheng [Wed, 7 Dec 2022 09:06:11 +0000 (17:06 +0800)]
[InstCombine] Add tests for (X << Z) / (X * Y) -> (1 << Z) / Y. nfc
Nikita Popov [Wed, 7 Dec 2022 08:48:28 +0000 (09:48 +0100)]
[LICM] Remove custom isInstInList() implementation (PR59324)
We already collect all instructions that need to be promoted. The
custom isInstInList() implementation could provide incorrect
results if a new use of the original pointer was introduced as
part of promotion. This probably cannot happen with normal code,
because of the pointer capture, but it can happen with a null
pointer.
Fixes https://github.com/llvm/llvm-project/issues/59324.
Jean Perier [Wed, 7 Dec 2022 08:48:53 +0000 (09:48 +0100)]
[flang] hlfir.assign default implementation
Add the default unoptimized implementation implementation
of hlfir.assign. It relies on the runtime for array assignment
and always makes a temp of the right hand side for arrays.
Assignment optimization will be done when all HLFIR pieces are in place
and aliasing analysis is available.
Differential Revision: https://reviews.llvm.org/D139426
Jean Perier [Wed, 7 Dec 2022 08:46:35 +0000 (09:46 +0100)]
[flang] turn fatal error into a TODO for FORALL edge-case
See https://github.com/llvm/llvm-project/issues/59337.
This TODO will be implemented as part of HLFIR work
(see https://github.com/llvm/llvm-project/blob/main/flang/docs/HighLevelFIR.md).
Differential Revision: https://reviews.llvm.org/D139410
Qiu Chaofan [Wed, 7 Dec 2022 08:42:37 +0000 (16:42 +0800)]
[PowerPC] Support test data class intrinsic of 128-bit float
We've exploited test data class instructions introduced in ISA 3.0.
This change unifies the scalar intrinsics into ppc_test_data_class
and add support for 128-bit precision float values using xststdcqp.
Vector versions of the intrinsic can't be unified because they return
vector int instead of int.
Reviewed By: shchenz
Differential Revision: https://reviews.llvm.org/D138105
Max Kazantsev [Wed, 7 Dec 2022 08:08:00 +0000 (15:08 +0700)]
[SCEV][NFC] Sink initialization of SymbolicMaxNotTaken from ExitLimit constructor to its callers
Preserves current behavior (always select Exact if known, otherwise select Constant Max).
This is the final preparation step before letting each particular computation way to decide
how exactly it should be computed. Functional improvement is coming shortly as follow-up.
Differential Revision: https://reviews.llvm.org/D139402
Reviewed By: nikic, fhahn
Jay Foad [Tue, 6 Dec 2022 11:43:33 +0000 (11:43 +0000)]
[AMDGPU] Change handling of s_endpgm's optional operand. NFC.
s_endpgm is a special SOPP instruction in that its operand is optional
and if it is not present then we don't want to print a space after the
mnemonic.
Previously this was handled by defaulting real_name to the mnemonic with
a trailing space, and having s_endpgm override it to be the mnemonic
with no trailing space.
This patch implements a different approach where the separator between
Mnemonic and AsmOperands defaults to a space, but s_endpgm overrides it
to be the empty string.
Differential Revision: https://reviews.llvm.org/D139412
Yeting Kuo [Wed, 7 Dec 2022 06:37:58 +0000 (14:37 +0800)]
[VP][RISCV] Recommit "Add vp.fshl/fshr and RISC-V support."
This reverts commit
7883e5b061bdbbe8bee5f479ebe911db5045b7e9.
The original commit was reverted that it didn't update test files after D136263
landed. The recommit fixed those.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D139509
Xiaodong Liu [Wed, 7 Dec 2022 07:49:14 +0000 (15:49 +0800)]
Reland: "[LoongArch] Use tablegen size for getInstSizeInBytes"
Correct the pseudo atomic instruction size for branch
relaxation and branch folding passes.
Inspired by D118175, D118009 and D117970.
Depends on D138481
Reviewed By: SixWeining, gonglingqin, xen0n
Differential Revision: https://reviews.llvm.org/D138469
Kazu Hirata [Wed, 7 Dec 2022 07:50:19 +0000 (23:50 -0800)]
[clangd] Use std::nullopt instead of None (NFC)
This is part of an effort to migrate from llvm::Optional to
std::optional:
https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
Kazu Hirata [Wed, 7 Dec 2022 07:22:09 +0000 (23:22 -0800)]
[clang-tools-extra] Don't including None.h (NFC)
These source files no longer use None, so they do not need to include
None.h.
This is part of an effort to migrate from llvm::Optional to
std::optional:
https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
Justin Bogner [Wed, 7 Dec 2022 03:49:32 +0000 (19:49 -0800)]
[AMDGPU] Handle `min(max(x, y), max(min(x, y), z))` in med3 combines
Differential Revision: https://reviews.llvm.org/D139508
Justin Bogner [Wed, 7 Dec 2022 06:06:52 +0000 (22:06 -0800)]
[AMDGPU] Handle nnan and fast on the call in fpmed3 patterns
We were only allowing these med3 patterns if the operands were known
to not be NaN, but we should also allow it if the calls to max/min
have the `nnan` or `fast` flags.
Differential Revision: https://reviews.llvm.org/D139506
Justin Bogner [Wed, 7 Dec 2022 06:42:20 +0000 (22:42 -0800)]
[AMDGPU] Precommit GISel test for min(max(x, y), max(min(x, y), z)) -> med3
These combines will be added by https://reviews.llvm.org/D139508
Rahman Lavaee [Wed, 7 Dec 2022 06:37:33 +0000 (22:37 -0800)]
[Propeller] Use Fixed MBB ID instead of volatile MachineBasicBlock::Number.
Let Propeller use specialized IDs for basic blocks, instead of MBB number.
This allows optimizations not just prior to asm-printer, but throughout the entire codegen.
This patch only implements the functionality under the new `LLVM_BB_ADDR_MAP` version, but the old version is still being used. A later patch will change the used version.
####Background
Today Propeller uses machine basic block (MBB) numbers, which already exist, to map native assembly to machine IR. This is done as follows.
- Basic block addresses are captured and dumped into the `LLVM_BB_ADDR_MAP` section just before the AsmPrinter pass which writes out object files. This ensures that we have a mapping that is close to assembly.
- Profiling mapping works by taking a virtual address of an instruction and looking up the `LLVM_BB_ADDR_MAP` section to find the MBB number it corresponds to.
- While this works well today, we need to do better when we scale Propeller to target other Machine IR optimizations like spill code optimization. Register allocation happens earlier in the Machine IR pipeline and we need an annotation mechanism that is valid at that point.
- The current scheme will not work in this scenario because the MBB number of a particular basic block is not fixed and changes over the course of codegen (via renumbering, adding, and removing the basic blocks).
- In other words, the volatile MBB numbers do not provide a one-to-one correspondence throughout the lifetime of Machine IR. Profile annotation using MBB numbers is restricted to a fixed point; only valid at the exact point where it was dumped.
- Further, the object file can only be dumped before AsmPrinter and cannot be dumped at an arbitrary point in the Machine IR pass pipeline. Hence, MBB numbers are not suitable and we need something else.
####Solution
We propose using fixed unique incremental MBB IDs for basic blocks instead of volatile MBB numbers. These IDs are assigned upon the creation of machine basic blocks. We modify `MachineFunction::CreateMachineBasicBlock` to assign the fixed ID to every newly created basic block. It assigns `MachineFunction::NextMBBID` to the MBB ID and then increments it, which ensures having unique IDs.
To ensure correct profile attribution, multiple equivalent compilations must generate the same Propeller IDs. This is guaranteed as long as the MachineFunction passes run in the same order. Since the `NextBBID` variable is scoped to `MachineFunction`, interleaving of codegen for different functions won't cause any inconsistencies.
The new encoding is generated under the new version number 2 and we keep backward-compatibility with older versions.
####Impact on Size of the `LLVM_BB_ADDR_MAP` Section
Emitting the Propeller ID results in a 23% increase in the size of the `LLVM_BB_ADDR_MAP` section for the clang binary.
Reviewed By: tmsriram
Differential Revision: https://reviews.llvm.org/D100808
Kazu Hirata [Wed, 7 Dec 2022 06:45:17 +0000 (22:45 -0800)]
[llvm] Use std::nullopt instead of None in comments (NFC)
This is part of an effort to migrate from llvm::Optional to
std::optional:
https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
Kazu Hirata [Wed, 7 Dec 2022 06:34:50 +0000 (22:34 -0800)]
[llvm] Don't include Optional.h (NFC)
These source files no longer use Optional<T>, so they do not need to
include Optional.h.
This is part of an effort to migrate from llvm::Optional to
std::optional:
https://discourse.llvm.org/t/deprecating-llvm-optional-x-hasvalue-getvalue-getvalueor/63716
Kazu Hirata [Wed, 7 Dec 2022 06:27:43 +0000 (22:27 -0800)]
Revert "[VP][RISCV] Add vp.fshl/fshr and RISC-V support."
This reverts commit
70de0e014013b4d97febe6704881a9a8c893d078.
I'm seeing:
Failed Tests (2):
LLVM :: CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
LLVM :: CodeGen/RISCV/rvv/fshr-fshl-vp.ll
Also reported at:
https://lab.llvm.org/buildbot/#/builders/123/builds/14531
Justin Bogner [Wed, 7 Dec 2022 06:04:16 +0000 (22:04 -0800)]
[AMDGPU] Precommit GISel test showing missing med3 combines
These combines will be added by https://reviews.llvm.org/D139506
Yeting Kuo [Tue, 6 Dec 2022 00:39:07 +0000 (08:39 +0800)]
[RISCV] Add basic cost model for vp float rounding instructions.
Reviewed By: craig.topper, reames
Differential Revision: https://reviews.llvm.org/D137766
Monk Chiang [Wed, 30 Nov 2022 09:07:14 +0000 (17:07 +0800)]
[RISCV] Codegen support for Zfhmin.
The Zfhmin subset only has FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S.
If the D extension is present, the FCVT.D.H and FCVT.H.D instructions are also included.
Since most instructions are not included for Zfhmin, so most operations are promoted.
The patch primarily about making f16 a legal type.
RISC-V ISA info:
https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D139391
Craig Topper [Wed, 7 Dec 2022 04:54:08 +0000 (20:54 -0800)]
[RISCV] Remove trailing whitespace. NFC
Hongtao Yu [Tue, 6 Dec 2022 23:22:50 +0000 (15:22 -0800)]
[llvm-profdata] Drop profile symbol list during merging AutoFDO profiles.
Adding a switch to drop profile symbol list during merging AutoFDO profiles. This is needed to minimize the impact on default profiles when the profile symbol list is enabled for the source input profiles. The symbol list is quite large and could potentially slow down the compiler.
Reviewed By: davidxl, wenlei
Differential Revision: https://reviews.llvm.org/D139486
Jakub Kuderski [Wed, 7 Dec 2022 04:29:41 +0000 (23:29 -0500)]
[mlir][spirv] Fix integer dot product format attr validation
Do not allow formats for non-scalar vector operands.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D139495