intel: add swizzle flag into driver uuid

Suggested by Lionel Landwerlin, we add has_bit6_swizzle as
another input when computing driver uuid.

Also fix miscalculation of the length of driver tag.

Signed-off-by: Jianxun Zhang <jianxun.zhang@linux.intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13936>

intel: remove chipset_id

The chipset_id should be named after i915 ioctl that's called
to get the device id. In user space this field holds pci device
id in reality. We now have a pci_device_id queried from drm
instead using the ioctl, so there is no much reason to keep
the chipset_id for the same purpose.

Signed-off-by: Jianxun Zhang <jianxun.zhang@linux.intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13936>

intel: dump PCI info in intel_dev_info

Dump PCI bus and device info so that we can easily identify output
in a multi-gpu system.

Signed-off-by: Jianxun Zhang <jianxun.zhang@linux.intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13936>

anv: remove private pci fields

These fields are in the base device struct 'intel_device_info' now.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5489

Signed-off-by: Jianxun Zhang <jianxun.zhang@linux.intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13936>

intel: use PCI info to compute device uuid

With the new input from PCI bus and device fields, we can compute
device uuids in a multi-gpu system.

Signed-off-by: Jianxun Zhang <jianxun.zhang@linux.intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13936>

intel: provide pci bus and dev info in base device struct

Having PCI bus and dev info in the base struct
'intel_device_info' enables us to utilize the info across
multiple drivers for several purposes, such as computing
device uuids in a multi-gpu system.

Signed-off-by: Jianxun Zhang <jianxun.zhang@linux.intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13936>

venus: VkExternalImageFormatProperties is optional

It's optional even if VkPhysicalDeviceExternalImageFormatInfo is there.

Fixes: 108f386a612 ("venus: initial support for VkPhysicalDevice commands")

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14503>

docs: update calendar and link releases notes for 21.3.4

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14526>

docs: add release notes for 21.3.4

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14526>

nir/opt_if: also merge break statements with ones after the branch

 This optimizations turns

     loop {
        ...
        if (cond1) {
           if (cond2) {
              do_work_1();
              break;
           } else {
              do_work_2();
           }
           do_work_3();
           break;
        } else {
           ...
        }
     }

 into:

     loop {
        ...
        if (cond1) {
           if (cond2) {
              do_work_1();
           } else {
              do_work_2();
              do_work_3();
           }
           break;
        } else {
           ...
        }
     }

As this optimizations moves code into the NIF statement,
it re-iterates on the branch legs in case of success.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7587>

nir/opt_if: merge two break statements from both branch legs

 This optimization turns

     loop {
        ...
        if (cond) {
           do_work_1();
           break;
        } else {
           do_work_2();
           break;
        }
     }

 into:

     loop {
        ...
        if (cond) {
           do_work_1();
        } else {
           do_work_2();
        }
        break;
     }

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7587>

vulkan/overlay: support Vulkan 1.2

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5602
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14465>

virgl: disable texture uploads with copy transfers

This disables cdc480585c9 ("virgl/drm: New optimization for uploading
textures") effectively.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Lepton Wu <lepton@chromium.org>
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14497>

docs: move the release for 22.0 out

Between a troubles with Marge and FD.O, and requests for a bit more
time for a few patches to land, we're going to bump the release out by
three weeks.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14502>

ci: Add paraview traces to several drivers.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14501>

ci/llvmpipe: Add a trace for the game JVGS, which got regressed recently.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14501>

ci/llvmpipe: Sort the list of traces.

so I don't have to deliberate about where to put new ones.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14501>

radv: set radv_split_fma=true for Proton SotTR

The game seems to expect fma to be unfused. Fixes depth-prepass artifacts.

I haven't tested the D3D12 version, but I think it doesn't work and needs
sparse depth/stencil images.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14458>

radv: add RADV_DEBUG=splitfma

This splits application-provided FMA in vertex/geometry/tesselation/mesh
shaders.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14458>

lima: remove not needed lie about PIPE_CAP_OCCLUSION_QUERY

Occlusion queries are supported always but only the number of
supported samples differ.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14361>

i915: remove not needed lie about PIPE_CAP_OCCLUSION_QUERY

Occlusion queries are supported always but only the number of
supported samples differ. This also removes I915_LIE debug
option.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14361>

vc4: remove not needed lie about PIPE_CAP_OCCLUSION_QUERY

Occlusion queries are supported always but only the number of
supported samples differ.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14361>

broadcom/ci: use .test-manual-mr

Allow the jobs to be available for MRs.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14361>

mesa: always support occlusion queries

Excerpt from ARB_occlusion_query.txt:
  An implementation can either set QUERY_COUNTER_BITS_ARB to the
  value 0, or to some number greater than or equal to n.  If an
  implementation returns 0 for QUERY_COUNTER_BITS_ARB, then the
  occlusion queries will always return that zero samples passed the
  occlusion test, and so an application should not use occlusion queries
  on that implementation.

This looks more sane for drivers wanting desktop gl 1.5 without real
hw support then just faking it.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14361>

Revert "ci: disable vs2019 windows build"

This reverts commit 567a9550d78a92815e7075eda42c38519b73c0b2.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14513>

freedreno: drop dead assignment

width0 was introduced in e11a239e8ca642414a61ac6fddf442a269a51d92

Its use was dropped in 979e7e3680792dc23d434295edd10b161af8aee3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14500>

freedreno: silence sometimes-uninitialized warning

Clang does not see that this is unreachable and thus
thinks that opc will be used uninitialized later.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14500>

radeon/vcn: enable dynamic dpb Tier2 for hevc dec vaapi path

keep omx hevc decoding using the current mode, set dpb Tier2 for
vaapi hevc decoding mode as default.

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14484>

radeon/vcn: enable dynamic dpb Tier2 support for h264 dec vaapi path

By disabling h264 enxtension flag to let vaapi application manage the
dpb buffers. The calculation of the non_exist_flags for h264 reference
frames needs to consider both frame number and POC in the reference
picture list, set this flag only if both of the frame number and POC
are not existed in the valid reference lists; otherwise, that reference
frame is considered valid.

Also enabled drm buffer in dynamic dpb Tier2.

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14484>

frontends/va: preparing to disable h264 extension flag in vaapi dec path

In frame reference frame, the top/bottom field reference flag also needs
to be set, so does the long term reference flag.

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14484>

frontends/omx: preserve omx to keep current mode for avc decoding

Preparing to disable h264 extension flag in vaapi path, and this change
will not affect omx.

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14484>

zink: ci updates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14397>

zink: use even more accurate stride values for query result copies

this shouldn't be used at all, but some drivers get it wrong and I don't want
to have to fix every driver

Fixes: 039ed2de94d ("zink: always use type size for query result copy stride")

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14397>

Revert "zink: when performing an implicit reset, sync qbos"

this appeared to fix some sort of bug related to preserving qbo data,
but really there shouldn't have been any sort of bug anyway since the qbos
all get read back, and thus the data is already preserved

instead, it just preserved the query id, which overloaded the pools and crashed

This reverts commit 79790e276f61f23217badd80c51add755dfe18ac.

fixes #5669

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14397>

zink: skip readback of qbos with no results

this is a no-op and also crashes

Fixes: 93190be1b99 ("zink: rewrite query internals")

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14397>

zink: fix availability buffer sizing/copying for xfb queries

xfb queries have 2 results, and the availability bit is a 3rd result, so
the buffer size has to be at least that big and the copy offset has to reflect
the number of xfb results in the src offset

cc: mesa-stable

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14397>

zink: always set number of timestamp results to 1 for internal qbo

timestamp queries don't accumulate results

Fixes: 93190be1b99 ("zink: rewrite query internals")

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14397>

zink: add a better threshold for clamping query pool resets on suspend

these pools should be dumped even if they aren't used

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14397>

nir: refactor nir_opt_move

This patch is a rewrite of nir_opt_move.
Differently from the previous version, each instruction is checked
if it can be moved downwards and then inserted before the first user
of the definition. The advantage is that less insert operations are
performed, the original order is kept if two movable instructions have
the same first user, and instructions without user in the same block
are moved towards the end.

v2: Only return true if an instruction really changed the position.
    Don't care for discards, this will be handled by another MR.
v3: fix self-referring phis and update according to nir_can_move_instr().
v4: use nir_can_move_instr() and nir_instr_ssa_def()
v5: deduplicate some code

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3657>

intel/devinfo: drop num_eus_per_subslice field

This field is an average computation that is not actually useful for
any of our driver code.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14510>

intel/devinfo: add a helper to check for slice availability

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14510>

intel/devinfo: printout devinfo struct size

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14510>

intel/devinfo: printout pixel pipes in info printout

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14510>

radeonsi/tests: add expected results for vega20

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14454>

radeonsi/tests: update expected results

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14454>

radeonsi,radv: fix usages of surf_pitch

For linear textures, pitch[level] should be used instead.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14454>

radeonsi/gfx10: fix si_texture_get_offset for mipmapped tex

Pitch can be different per-level so adjust stride and offset.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5792
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14454>

radv: fix computing the fb size in presence of dynamic VRS attachment

This fixes
dEQP-VK.fragment_shading_rate.dynamic_rendering.attachment_rate.*.

Fixes: e914a6710fd ("radv: Expose the VK_KHR_dynamic_rendering extension.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14421>

radv: reset VRS if the current subpass doesn't have a VRS attachment

With a scenario like:
BeginRP(DS + VRS att)
Draw()
EndRP()
BeginRP(same DS)
Draw()
EndRP()

The second draw shouldn't use VRS but it did because the VRS bit
is always set during DS surface initialization if a surface can use VRS.
So, it would have been using the previous copied VRS rates.

Found by inspection.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14443>

radv: stop checking if dynamic states changed

This is costly for the CPU and might hurt "good" applications that
already avoid that like DXVK/vkd3d-proton.

Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5009
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12441>

ci: disable vs2019 windows build

Failing with :

   error during connect: In the default daemon configuration on
   Windows, the docker client must be run with elevated privileges to
   connect.: Post http://%2F%2F.%2Fpipe%2Fdocker_engine/v1.24/auth:
   open //./pipe/docker_engine: The system cannot find the file
   specified.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14509>

anv,iris: Flush HDC before color fast clears

Needed for XeHP (see Bspec 47704).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14024>

anv,iris: PSS Stall Sync around color fast clears

Needed for XeHP (see Bspec 47704).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14024>

intel: Rename the PSD bit in PIPE_CONTROL for XeHP

The name of the field now starts with PSS Stall instead of PSD.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14024>

anv,iris: Depth stall around color fast clears

Needed for TGL (see Bspec 47704).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14024>

anv,iris: Flush tile cache after color fast clears

Needed for TGL (see Bspec 47704).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14024>

radv: 256 byte push constants.

This helps vkd3d-proton, especially when indirecting more stuff.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14485>

radv: Use 16-bits to store push constant indices.

Otherwise things horrible go wrong when we get 256 bytes of push
constants.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14485>

radv: Use MAX_PUSH_CONSTANTS_SIZE for saved push constants.

So that it can never again get out of sync.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14485>

zink: use device-local heap for sparse backing allocations

backing allocations are real allocations, so they shouldn't be initialized
as sparse containers

Fixes: 40fdb3212c3 ("zink: add a suballocator")

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14394>

nir: handle per-view clip/cull distances

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14263>

spirv: mark [Clip|Cull]DistancePerViewNV variables as compact

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14263>

nir: remove invalid assert affecting per-view variables

per-view variables can have arbitrary (but > 0) number of array levels

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14263>

spirv: handle multiview bits of SPV_NV_mesh_shader

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14263>

nir: add load_mesh_view_count and load_mesh_view_indices intrinsics

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14263>

spirv: add MeshViewCountNV/MeshViewIndidcesNV builtins from SPV_NV_mesh_shader

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14263>

compiler: add new MESH_VIEW_COUNT/MESH_VIEW_INDICES system values

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14263>

spirv: handle ViewportMaskNV builtin/cap from SPV_NV_mesh_shader

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14263>

intel/isl: Return false more in isl_surf_get_hiz_surf

Follow the CCS and MCS functions by returning false for unsupported
cases. This reduces the burden on the caller.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>

intel/isl: Allow HiZ with Tile4/64 surfaces

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>

intel/isl: Require Y-tiling for depth on gfx4-5

This enables isl_surf_get_hiz_surf to be simplified.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>

intel/isl: Use a new HiZ format on XeHP+

The new HiZ compresses twice as many rows of the depth surface compared
to TGL (Bspec 47009). Also, its tiling needs to be specified in
3DSTATE_HIER_DEPTH_BUFFER_BODY::TiledMode.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>

intel/isl: Update comment for the XeHP HiZ block

An 8x4 HiZ block doesn't fit in with the new formulas for sizing HiZ on
XeHP. Update a comment which assumed this block size on SKL+.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>

intel/isl: Rework HiZ image align calculations

* Check the format's compression type instead of the format directly to
  prepare for a new HiZ format on XeHP.
* Adjust the gfx12+ calculations so that XeHP will automatically be
  handled.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>

blorp: Drop multisampled code in blorp_can_hiz_clear_depth

Anv allows non-8x4-aligned depth buffer clears, but it has multisampled
HiZ disabled for BDW. iris allows multisampled HiZ on BDW, but disallows
non-8x4-aligned depth buffer clears.

Drop the unused optimization for non-8x4-aligned clears of multisampled
surfaces on BDW and use this opportunity to use some PRM text in the
code comment.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14091>

anv: increase binding table pool size to 64KB

Binding table pool runs out of capacity quickly on modern games,
requiring new Surface Base Address instructions to be sent. That
is costly due to flushes and stalls.  Increasing BT pool capacity
to 64KB improves performance several workloads.

Fallout4 +4%
Shadow of the Tomb Raider +4%
Borderlands3 +3%

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14483>

intel/dev: fixup chv workaround

We're using the wrong helper to get the subslice total count.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c24ba6cecbacf2 ("intel/dev: Handle CHV CS thread weirdness in get_device_info_from_fd")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14492>

turnip: Use vk_common_QueueSignalReleaseImageANDROID for DRM

It's identical to the one turnip copy+pasted from RADV.  For KGSL, we
still need to hand-roll because of all the emulated stuff.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14411>

turnip: Use vk_common_AcquireImageANDROID

It's got some bug fixes that turnip never picked up.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14411>

r300: use point sprite coordinates only when drawing points (v5)

Fixes piglit arb_point_sprite-interactions
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/364
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/370

Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14389>

zink: add extra synchronization for buffer descriptor binds

"most" times it isn't necessary to insert any pipeline barriers when binding
descriptors, as GL requires explicit barrier usage which comes through a different
codepath

the exception here is when the following scenario occurs:
* have buffer A
* buffer_subdata is called on A
* discard path is taken || A is not host-visible
* stream uploader is used for host write
* CmdCopyBuffer is used to copy the data back to A
buffer A now has a pending TRANSFER write that must complete before the buffer is
used in a shader, so synchronization is required any time TRANSFER usage is detected
in a bind

there's also going to be more exceptions going forward as more internal usage is added,
so just remove the whole fake-barrier mechanism since it'll become more problematic
going forward

Cc: 21.3 mesa-stable
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14496>

d3d12/ci: Skip flaky tex-miplevel-selection and timestamp tests

Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14494>

zink: always unset vertex shader variant key data when changing last vertex stage

ensure that vertex key data is always zeroed when changing last stage since it will
be updated before draw anyway and can only cause problems if left alone here

fixes the following caselist:
dEQP-GLES31.functional.shaders.builtin_constants.tessellation_shader.max_tess_evaluation_texture_image_units
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_quads_geometry_output_points
dEQP-GLES31.functional.ubo.random.all_per_block_buffers.25

cc: mesa-stable

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14482>

zink: add some wsi instance extensions

not used for now

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14426>

zink: add missing assert for 8bit vertex decompose

verify that this bit was set above

Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14380>

radv: implement wsi's private transfer queue using SDMA

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13959>

vulkan/wsi: add a private transfer pool to exec the DRI_PRIME blit

The idea is to offer the driver a way to execute on a different queue
than the one the app is using for Present.

For instance, this could be used to make the DRI_PRIME blit asynchronous,
by using a transfer queue.

So instead of creating a command buffer to be executed on present using
the supplied queue, this commit uses an internal transfer queue to perform
the blit.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13959>

vulkan/wsi: add use_prime_blit param to wsi_swapchain_init

Instead of initializing it to false and overriding it later if
needed.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13959>

radv: allocate the prime buffer as uncached

This is a write only buffer so caches aren't needed.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13959>

radv: partial sdma support

SDMA code adapted from https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12763

The only supported use case is image (linear or tiled) -> buffer and only GFX9+ is
supported (for now).

Since RADV_QUEUE_TRANSFER aren't exposed to applications, this cannot be used,
except by the driver.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13959>

amd: add SDMA_NOP_PAD

And use it in amdgpu_cs.c.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13959>

aco: validate VOP3P opsel correctly

Before RA, subdword operands must use .xx
After RA, opsel can either be .xx or .yy

Cc: mesa-stable
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14472>

mesa: free vbo_save_vertex_list store prims

Fixes a leak:
  ==47470== 60 bytes in 1 blocks are definitely lost in loss record 1,790 of 1,904
  ==47470==    at 0x484186F: malloc (vg_replace_malloc.c:381)
  ==47470==    by 0x58EBA6A: compile_vertex_list (vbo_save_api.c:535)
  ==47470==    by 0x58EDABF: wrap_buffers (vbo_save_api.c:1021)
  ==47470==    by 0x58EDF97: upgrade_vertex (vbo_save_api.c:1134)
  ==47470==    by 0x58EE52F: fixup_vertex (vbo_save_api.c:1251)
  ==47470==    by 0x58EFE9E: _save_Normal3f (vbo_attrib_tmp.h:315)

Fixes: 69615d92a0e ("vbo/dlist: realloc prims array instead of free/malloc")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14474>

mesa: free idalloc storage for display lists

Fixes a leak:
  ==46154== 48 bytes in 1 blocks are definitely lost in loss record 1,571 of 1,905
  ==46154==    at 0x48466AF: realloc (vg_replace_malloc.c:1437)
  ==46154==    by 0x5FC98EC: util_idalloc_resize (u_idalloc.c:43)
  ==46154==    by 0x5FC9C16: util_idalloc_alloc_range (u_idalloc.c:125)
  ==46154==    by 0x56FDB9F: _mesa_EndList (dlist.c:13681)

Fixes: b703d7c15f4 ("dlist: store all dlist in a continuous memory block")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14474>

intel/xehp: Switch to coarser cross-slice pixel hashing with table permutation.

The coarser 32x32 cross-slice hashing mode seems to lead to better L1
and L2 utilization due to the improved execution locality, however it
can also lead to a bottleneck in a single slice, especially in
workloads that concentrate heavy rendering in small areas of the
screen (e.g. SynMark2 OglGeomPoint, OglTerrain*) -- This effect is
mitigated here by performing a permutation of the pixel pipe hashing
tables that ensures that adjacent rows map to pixel pipes as far away
as possible in the caching hierarchy.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569>

anv: Program pixel hashing tables on XeHP.

Note that this has an effect even for unfused native die platforms,
since the pixel pipe hashing tables we intend to program aren't
equivalent to the hardware's defaults on such configs.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569>

iris: Program pixel hashing tables on XeHP.

Unlike the Gen11 code, this requires us to allocate a pipe_resource
for the pixel pipe hashing tables and hold a reference to it from the
context, since we need to add it to the validation list of every
batch, the tables may be accessed by the hardware at any time after
they're specified via 3DSTATE_SLICE_TABLE_STATE_POINTERS.

Note that this has an effect even for unfused native die platforms,
since the pixel pipe hashing tables we intend to program aren't
equivalent to the hardware's defaults on such configs.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569>

intel: Rename intel_compute_pixel_hash_table() to intel_compute_pixel_hash_table_3way().

For consistency with intel_compute_pixel_hash_table_nway().

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569>

intel: Minimal calculation of pixel hash table for arbitrary number of pixel pipes.

This starts off with the simplest possible pixel hashing table
calculation that just assigns consecutive indices (modulo N) to
adjacent entries of the table, along the lines of the existing
intel_compute_pixel_hash_table().  The same function will be improved
in a future commit with a more optimal calculation.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569>

intel: Move pixel hashing table computation into common header file.

In order to avoid some duplication between the GL and Vulkan driver,
which will get worse as we introduce additional code in order to
handle more recent generations.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569>