Boyuan Zhang [Thu, 26 Mar 2020 23:16:43 +0000 (19:16 -0400)]
drm/amdgpu: add internal reg offset translation for VCN inst 1
Add range for vcn instance 1 for translation for internal register offset, which
is needed for VCN3.0
V2: update description.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Thu, 26 Mar 2020 23:11:56 +0000 (19:11 -0400)]
drm/amdgpu: set indirect sram mode for VCN3.0
Use indirect sram for secure DPG mode
V2: update description.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Fri, 27 Mar 2020 17:41:54 +0000 (13:41 -0400)]
drm/amdgpu: add pause DPG mode for VCN3.0
Add vcn_v3_0_pause_dpg_mode to pause/unpause DPG mode for VCN3.0
V2: update description.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Fri, 27 Mar 2020 17:38:54 +0000 (13:38 -0400)]
drm/amdgpu: add stop DPG mode for VCN3.0
Add vcn_v3_0_stop_dpg_mode to power off in DPG mode for VCN3.0
V2: update description.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Fri, 27 Mar 2020 17:30:53 +0000 (13:30 -0400)]
drm/amdgpu: add start DPG mode for VCN3.0
Add vcn_v3_0_start_dpg_mode to setup and start VCN block in DPG mode for VCN3.0
V2: Separate from previous patch-0002, and update description.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Mon, 30 Mar 2020 13:42:45 +0000 (09:42 -0400)]
drm/amdgpu: add mc resume DPG mode for VCN3.0
Add vcn_v3_0_mc_resume_dpg_mode to resume memory controller in DPG mode for VCN3.0
V2: Separate from previous patch-0002, and update description.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Fri, 27 Mar 2020 17:11:16 +0000 (13:11 -0400)]
drm/amdgpu: add clock gating DPG mode for VCN3.0
Add vcn_v3_0_clock_gating_dpg_mode to enabling clock gating in DPG mode for VCN3.0
V2: Separate from previous patch-0002, and update description.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 30 Mar 2020 09:07:11 +0000 (17:07 +0800)]
drm/am/powerplay: enable OUT OF BAND MONITER for sienna_cichlid
Enable OUT OF BAND MONITER for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 30 Mar 2020 07:07:10 +0000 (15:07 +0800)]
drm/amd/powerplay: enable RSMU SMN PG for sienna_cichlid
Enable RSMU SMN PG for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 30 Mar 2020 06:56:53 +0000 (14:56 +0800)]
drm/amdgpu: update golden setting for sienna_cichlid
Update golden setting for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Fri, 27 Mar 2020 06:44:35 +0000 (14:44 +0800)]
drm/amd/powerplay: bundle GPO with gfx DPM
Bundle GPO with gfx DPM and enable it since gfxclk dpm
should work first then GPO works.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Fri, 27 Mar 2020 06:17:41 +0000 (14:17 +0800)]
drm/amd/powerplay: enable GPO
GPO is graphics power optimizer.
SMU calculates the 16 gfxclk V/F points according to the CU numbers
and memory activity.RLC picks one of them according to the memory
speed requirements for the data transmission.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Fri, 27 Mar 2020 04:23:14 +0000 (12:23 +0800)]
drm/amd/powerplay: enable mmhub pg
mmhub pg can be obvserved from PCTL_CTRL
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Thu, 26 Mar 2020 04:01:15 +0000 (12:01 +0800)]
drm/amd/powerplay: enable athub pg
enable athub pg and the status can be checked in
ATHUB_MISC_CNTL.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Fri, 20 Mar 2020 11:28:52 +0000 (19:28 +0800)]
drm/amdgpu: skip VM inv eng assignment for mes ring
Statically allocated VM inv eng of gfxhub on sienna_cichlid is used up.
Also VM inv eng is no need for mes ring.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Fri, 20 Mar 2020 11:11:36 +0000 (19:11 +0800)]
drm/amdgpu/mes: allocate memory slots for hw resource setting
Pass a piece of memory to MES ucode to fill contents.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Fri, 20 Mar 2020 08:35:50 +0000 (16:35 +0800)]
drm/amdgpu/mes: add status fence memory definitions
Update for new member query_status_fence_gpu_mc_ptr in MESAPI_SET_HW_RESOURCES.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Fri, 20 Mar 2020 07:22:37 +0000 (15:22 +0800)]
drm/amdgpu/mes: update mes fw api
Update mes_api_def.h to match the latest mes fw.
v2: clean up coding style based on kernel standards:
- fix indentation and alignment
- break long lines
- put the opening brace last on the line
- remove unnecessary blank line and space
- replace uint(32|64) with standard uint(32|64)_t
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 24 Mar 2020 07:25:40 +0000 (15:25 +0800)]
drm/amd/powerplay: add function to get power limit for sienna_cichlid
Add function to get pptable power limit for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 24 Mar 2020 07:15:10 +0000 (15:15 +0800)]
drm/amd/powerplay: enable APCC DFLL for sienna_cichlid
Enable APCC DFLL for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 23 Mar 2020 03:29:20 +0000 (11:29 +0800)]
drm/amd/powerplay: enable BACO for sienna_cichlid
Enable BACO for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
shaoyunl [Tue, 17 Mar 2020 15:41:34 +0000 (11:41 -0400)]
drm/amdgpu: Sienna_Cichlid don't enable SMU for SRIOV
SMU firmware already been loaded from host, don't enable it for now.
May need to re-work it if we want to enable the SMU for guest in the future.
Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 19 Mar 2020 07:21:27 +0000 (15:21 +0800)]
drm/amd/powerplay: enable MM DPM PG for sienna_cichlid (v2)
Enable VCN dpm set for sienna_cichlid.
Enable JPEG dpm set for sienna_cichlid.
v2: squash in BACO fix (Kenneth)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Wed, 18 Mar 2020 20:59:38 +0000 (16:59 -0400)]
drm/amdgpu: fix typo for vcn3/jpeg3 idle check
fix typo for vcn3/jpeg3 idle check
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 17 Mar 2020 05:28:10 +0000 (13:28 +0800)]
drm/amd/powerplay: enable FCLK DS for sienna_cichlid
Enable the feature of FCLK Deep Sleep for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 17 Mar 2020 05:25:12 +0000 (13:25 +0800)]
drm/amd/powerplay: enable VR0HOT for sienna_cichlid
Enable the feature of Voltage Regulator (VR) Hot for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
shaoyunl [Fri, 7 Feb 2020 23:56:42 +0000 (18:56 -0500)]
drm/amdkfd: sienna_cichlid virtual function support
amdkfd add support for sienna_cichlid virtual function
Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Thu, 21 Nov 2019 18:41:11 +0000 (12:41 -0600)]
drm/amdkfd: Support debugger in Navi1x trap handler
- Preserve scalar GPRs ttmp[4:11] and ttmp13
- Add single step exception during context save workaround
- Remove incorrect PC adjustment during context save
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Wed, 20 Nov 2019 22:13:03 +0000 (16:13 -0600)]
drm/amdkfd: Support newer assemblers in gfx10 trap handler
The contents of macros are parsed by the assembler before conditions
have been tested. This causes assembly errors when using IP-specific
instructions in the IP-unified trap handler.
Add a preprocessing step to filter IP-specific code.
Also guard a Navi1x-specific instruction (no effect on Sienna_Cichlid).
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Sat, 2 Nov 2019 00:05:08 +0000 (19:05 -0500)]
drm/amdkfd: Add Sienna_Cichlid trap handler support
- Replace SQC stores with TCP stores
- Synchronize with MSG_SAVEWAVE via lgkmcnt
- HW_REG_IB_STS is now read-only
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yong Zhao [Tue, 1 Oct 2019 21:42:20 +0000 (17:42 -0400)]
drm/amdkfd: Support Sienna_Cichlid KFD v4
v4: drop get_tile_config, comment out other callbacks
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jerry (Fangzhi) Zuo [Mon, 20 Jan 2020 16:39:18 +0000 (11:39 -0500)]
drm/amdgpu/dc: Add missing Sienna_Cichlid chip id
Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 3 Mar 2020 02:40:32 +0000 (10:40 +0800)]
drm/amdgpu: enable 3D pipe 1 on Sienna_Cichlid
Only disable 3D pipe 1 on navi1x, enable 3D pipe 1 on Sienna_Cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 4 Mar 2020 08:40:24 +0000 (16:40 +0800)]
drm/amdgpu: fix SDMA hdp flush engine conflict
Each of HDP flush engine should be used by one ring, correct allocate of
hdp flush engine to SDMA ring.
Correct me value of each SDMA ring, as it was cleared when init microcode.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 18 Mar 2020 21:33:47 +0000 (17:33 -0400)]
drm/amdgpu: Enable Multi Media Hub (MMHUB) Clock Gating for sienna_cichlid.
Enable mmhub clockgating.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Fri, 28 Feb 2020 06:14:00 +0000 (14:14 +0800)]
drm/amd/amdgpu: add athub ls support
athub ls is bounded with hdp ls,verified.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Fri, 28 Feb 2020 06:09:31 +0000 (14:09 +0800)]
drm/amd/amdgpu: add IH cg support
IH cg verified
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Fri, 28 Feb 2020 03:57:04 +0000 (11:57 +0800)]
drm/amd/amdgpu: add HDP mgcg and ls support
add HDP mgcg and ls support and verified
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Fri, 28 Feb 2020 03:57:04 +0000 (11:57 +0800)]
drm/amd/amdgpu: fix the HDP LS/DS/SD programming
confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN
have to be set for SRAM LS/DS/SD
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 14 Feb 2020 08:45:56 +0000 (16:45 +0800)]
drm/amdgpu: update golden setting for gfx10.3
Update gfx golden setting for gfx10.3.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 28 Jan 2020 17:21:52 +0000 (12:21 -0500)]
drm/amdgpu: set the LMI ctrl and reset earlier
So the LMI register will be programmed properly
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 28 Jan 2020 16:50:00 +0000 (11:50 -0500)]
drm/amdgpu: fix the PSP front door loading VCN firmware
for the second instance with correct index
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Mon, 20 Jan 2020 15:07:40 +0000 (10:07 -0500)]
drm/amdgpu: change the offset for VCN FW cache window
The signed header is added
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 23 Jan 2020 19:57:55 +0000 (03:57 +0800)]
drm/amdgpu: open GFX clock gating for sienna_cichlid
Open GFX MGCG, CGCG and 3DCG for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 23 Jan 2020 16:14:32 +0000 (00:14 +0800)]
drm/amdgpu: switch to query reserved fb size from vbios (v3)
For Sienna_Cichlid, query fw_reserved_fb_size from vbios directly.
For navi1x, fall back to default 64K TMR size.
For pre-navi, no need to reserve tmr region in top LFB.
v2: fix TMR define (Alex)
v3: partially revert size change
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 22 Jan 2020 20:13:01 +0000 (04:13 +0800)]
drm/amdgpu: add atomfirmware helper funciton to query reserved fb size
fw_reserved_size_in_kb is introduced for driver to query
the TMR region reserved by PSP BL in Sienna_Cichlid and onwards
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 22 Jan 2020 20:08:59 +0000 (04:08 +0800)]
drm/amdgpu: add firmware_info v3_4 structure for Sienna_Cichlid
firmware_info v3_4 strucure will be used by kernel driver
to query various parameters set by VBIOS for Sienna_Cichlid
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 20 Jan 2020 19:22:32 +0000 (03:22 +0800)]
drm/amdgpu: only send one sdma firmware for sienna_cichlid
As all four sdma firmware are same, PSP only receive one SDMA fw.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 19 Jan 2020 21:16:41 +0000 (05:16 +0800)]
drm/amdgpu: drop gfx_v10_0_tiling_mode_table_init
tiling mode table is not used anymore for gfx10
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 19 Jan 2020 20:46:33 +0000 (04:46 +0800)]
drm/amdgpu: support query vram info for sienna_cichlid
support query vram_module v11 and vram_info v2_5
for sienna_cichlid
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 19 Jan 2020 20:41:40 +0000 (04:41 +0800)]
drm/amdgpu: add vram_info v2_5 in atomfirmware header
vram_info v2_5 was introduced to support sienna_cichlid
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Sun, 19 Jan 2020 21:29:06 +0000 (05:29 +0800)]
drm/amdgpu: disable gfxoff for sienna_cichlid
Temporary disable gfxoff for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 16 Jan 2020 20:35:09 +0000 (04:35 +0800)]
drm/amdgpu: add cp firmware backdoor loading triger
Triger CP ucode addr and data to backdoor load CP firmware.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 16 Jan 2020 03:07:20 +0000 (11:07 +0800)]
drm/amdgpu: force pa_sc_tile_steering_override to 0 for gfx10.3
pa_sc_tile_steering_override is only programmable for
gfx10.0/10.1/10.2
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 9 Apr 2020 18:19:48 +0000 (14:19 -0400)]
drm/amdgpu/gfx10: add gc golden setting for sienna_cichlid
Add gc golden setting for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 24 Mar 2020 20:31:23 +0000 (16:31 -0400)]
drm/amdgpu: enable JPEG3.0 for Sienna_Cichlid
By adding JPEG HW block to Sienna_Cichlid
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 3 Dec 2019 14:23:24 +0000 (09:23 -0500)]
drm/amdgpu: enable JPEG3.0 PG and CG for Sienna_Cichlid
By setting up the flags to the ASIC
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Fri, 29 Nov 2019 17:47:55 +0000 (11:47 -0600)]
drm/amdgpu: add Sienna_Cichlid JPEG PG and CG support
This is for static powergating and clockgating
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Fri, 15 Nov 2019 18:23:10 +0000 (13:23 -0500)]
drm/amdgpu: add JPEG3.0 support for Sienna_Cichlid
With basic IP block functions and ring functions
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 24 Mar 2020 20:30:24 +0000 (16:30 -0400)]
drm/amdgpu: enable VCN3.0 for Sienna_Cichlid
By adding VCN HW block to Sienna_Cichlid
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Fri, 27 Sep 2019 16:28:48 +0000 (11:28 -0500)]
drm/amdgpu: add Sienna_Cichlid VCN to the VCN family
By adding Sienna_Cichlid VCN firmware
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 3 Dec 2019 14:18:51 +0000 (09:18 -0500)]
drm/amdgpu: enable VCN3.0 PG and CG for Sienna_Cichlid
By setting up the flags to the ASIC
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Wed, 27 Nov 2019 16:03:39 +0000 (11:03 -0500)]
drm/amdgpu: add Sienna_Cichlid VCN PG and CG support (v2)
This is for static powergating and clockgating
v2: fix registers (Alex)
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Fri, 15 Nov 2019 17:45:55 +0000 (12:45 -0500)]
drm/amdgpu: add VCN3.0 support for Sienna_Cichlid
With basic IP block functions and ring functions
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 20 Nov 2019 08:21:22 +0000 (16:21 +0800)]
drm/amdgpu/mes: correct register offset for sienna_cichlid
Correct CP_MES_IC_OP_CNTL register address for sienna_cichlid on mes v10.1.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 24 Oct 2019 04:03:08 +0000 (12:03 +0800)]
drm/amdgpu: update the num of queue per pipe for mec on sienna_cichlid
The number of queue per pipe for mec on sienna_cichlid should be 4.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 24 Mar 2020 20:28:43 +0000 (16:28 -0400)]
drm/amdgpu: add mes block to sienna_cichlid
Add mes block support to sienna_cichlid.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 16 Oct 2019 03:48:48 +0000 (11:48 +0800)]
drm/amdgpu/mes10.1: update mes initialization
Update mes initialization sequence.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Mon, 21 Oct 2019 05:49:38 +0000 (13:49 +0800)]
drm/amdgpu: no need to set up GPU scheduler for mes ring
As mes ring directly submits to hardwared,
it's no need to set up GPU scheduler for mes ring.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 6 Jun 2019 09:54:15 +0000 (17:54 +0800)]
drm/amdgpu/psp: convert amdgpu mes ucode type
Convert to psp defined ucode item, so that psp can recognize them.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 6 Jun 2019 09:52:37 +0000 (17:52 +0800)]
drm/amdgpu: upload mes firmware to gpu buffer
Copy mes firmware to gpu buffer.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 6 Jun 2019 09:46:24 +0000 (17:46 +0800)]
drm/amdgpu/mes10.1: copy mes fw info into global fw array
Copy mes firmware info into into global fw array, preparing
for fw front door loading.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 16 Oct 2019 05:45:11 +0000 (13:45 +0800)]
drm/amdgpu/mes10.1: add sienna_cichlid mes firmware support
Add sienna_cichlid mes firmware support.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 16 Oct 2019 03:12:48 +0000 (11:12 +0800)]
drm/amdgpu/mes10.1: implement setting hardware resources
The routine is implemented to generate mes command to
assign the hardware resources which can be scheduled
to mes.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 15 Oct 2019 09:21:01 +0000 (17:21 +0800)]
drm/amdgpu/mes10.1: implement querying the scheduler status
The routine is implemented to generate mes command
to query the status of hardware scheduler.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 15 Oct 2019 09:07:42 +0000 (17:07 +0800)]
drm/amdgpu/mes10.1: implement removing hardware queue
The routine is implemented to generate mes command to remove
a specified hardware queue.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 15 Oct 2019 09:05:49 +0000 (17:05 +0800)]
drm/amdgpu/mes10.1: implement adding hardware queue
The routine is implemented to generate mes command
to install a hardware queue.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 15 Oct 2019 08:35:30 +0000 (16:35 +0800)]
drm/amdgpu/mes10.1: add the helper function for mes command submission
The helper function is used to submit mes command and poll waiting
for the command completion.
v2: replaced with amdgpu_fence_wait_polling to wait.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 15 Oct 2019 09:02:45 +0000 (17:02 +0800)]
drm/amdgpu/mes10.1: add the mes fw api
Add the definitions of mes commands.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 30 Apr 2019 03:44:04 +0000 (11:44 +0800)]
drm/amdgpu/mes10.1: enable the mes ring during initialization
Enable the mes ring during mes block initialization.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 30 Apr 2019 03:39:54 +0000 (11:39 +0800)]
drm/amdgpu/mes10.1: install mes queue via kiq
Install mes queue via kiq. Disable it temporarily
until it's workable.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 30 Apr 2019 03:11:00 +0000 (11:11 +0800)]
drm/amdgpu/mes10.1: install mes queue by register programming
Directly writing mes queue registers to set up it.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 30 Apr 2019 03:27:10 +0000 (11:27 +0800)]
drm/amdgpu/mes10.1: initialize the mqd
Initialize the mqd according to mes ring setup.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 6 Jun 2019 03:14:07 +0000 (11:14 +0800)]
drm/amdgpu/mes10.1: allocate mqd buffer
Allocate mqd buffer preparing for mes queue setup.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 5 Jun 2019 08:57:35 +0000 (16:57 +0800)]
drm/amdgpu/mes10.1: implement the ring functions of mes specific
Implement mes ring functions and set up them.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 26 Apr 2019 10:59:35 +0000 (18:59 +0800)]
drm/amdgpu/mes10.1: initialize the software part of mes ring
Do the software initialization on the mes ring.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 6 Jun 2019 02:55:23 +0000 (10:55 +0800)]
drm/amdgpu/mes10.1: allocate the eop buffer
eop buffer will be used for mes queue setup.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 16 Oct 2019 03:13:50 +0000 (11:13 +0800)]
drm/amdgpu/mes: update some mes definitions
Update some mes definitions.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Wed, 5 Jun 2019 08:30:13 +0000 (16:30 +0800)]
drm/amdgpu: avoid dereferencing a NULL pointer
Check if irq_src is NULL to avoid dereferencing a NULL pointer,
for MES ring is uneccessary to recieve an interrupt notification.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Thu, 9 Apr 2020 18:16:40 +0000 (14:16 -0400)]
drm/amdgpu: add the ring type definition of MES
Add a new ring type definition.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Fri, 26 Apr 2019 10:58:41 +0000 (18:58 +0800)]
drm/amdgpu: assign the doorbell index to mes ring
MES ring will use the assigned doorbell index for
command submission.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Thu, 10 Oct 2019 13:43:34 +0000 (09:43 -0400)]
drm/amdgpu: add 2rd VCN instance doorbell support
Sienna_Cichlid have 2 VCN instances, using different register for range
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 24 Mar 2020 20:27:43 +0000 (16:27 -0400)]
drm/amdgpu: add psp block load condition for sienna_cichlid
Enable PSP block for firmware loading and other security
setup only when amdgpu use PSP load type to load ucode.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Sun, 29 Sep 2019 03:32:24 +0000 (11:32 +0800)]
drm/amdgpu: add gmc cg support for sienna_cichlid
Add gmc clockgating support for sienna_cichlid.
The athub version used for sienna_cichlid is v2.1.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 25 Sep 2019 08:44:46 +0000 (16:44 +0800)]
drm/amdgpu: add support for athub v2.1
Add athub v2.1 function and support to compile it.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yong Zhao [Thu, 19 Sep 2019 22:01:06 +0000 (18:01 -0400)]
drm/amdgpu: Use variable instead of constant for sdma doorbell range
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 28 Aug 2019 09:52:54 +0000 (17:52 +0800)]
drm/amdgpu: update SDMA 5.2 microcode init
Removed loading duplicate instances of SDMA FW for Sienna_Cichlid,
As sienna_cichlid only use a single image for all instances.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 24 Mar 2020 20:26:17 +0000 (16:26 -0400)]
drm/amdgpu: enable psp ip block for sienna_cichlid
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 5 Aug 2019 07:32:40 +0000 (15:32 +0800)]
drm/amdgpu: skip for reroute ih for sienna_cichlid psp ring init currently
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 22 Jul 2019 08:52:20 +0000 (16:52 +0800)]
drm/amdgpu/psp: add psp support for sienna_cichlid
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
projects / platform / kernel / linux-starfive.git / log