Jim Ingham [Thu, 28 Mar 2019 01:51:33 +0000 (01:51 +0000)]
Copy the breakpoint site owner's collection so we can drop
the collection lock before we iterate over the owners calling ShouldStop.
BreakpointSite::ShouldStop can do a lot of work, and might by chance hit the same breakpoint
site again on another thread. So instead of holding the site's owners lock
while iterating over them calling ShouldStop, I make a local copy of the list, drop the lock
and then iterate over the copy calling BreakpointLocation::ShouldStop.
It's actually quite difficult to make this cause problems because usually all the
action happens on the private state thread, and the lock is recursive.
I have a report where some code hit the ASAN error breakpoint, went to
compile the ASAN error gathering expression, in the course of compiling
that we went to fetch the ObjC runtime data, but the state of the program
was such that the ObjC runtime grubbing function triggered an ASAN error and
we were executing that function on another thread.
I couldn't figure out a way to reproduce that situation in a test. But this is an
NFC change anyway, it just makes the locking strategy more narrowly focused.
<rdar://problem/
49074093>
llvm-svn: 357141
Rui Ueyama [Thu, 28 Mar 2019 01:37:48 +0000 (01:37 +0000)]
Inline a trivial function. NFC.
I found that hiding this particular actual expression doesn't help
readers understand the code. So I remove and inline that function.
llvm-svn: 357140
Louis Dionne [Thu, 28 Mar 2019 01:27:52 +0000 (01:27 +0000)]
[libc++] Rename span's as_writeable_bytes to as_writable_bytes
Summary: The Standard says as_writable_bytes.
Reviewers: mclow.lists, EricWF
Subscribers: christof, jkorous, dexonsmith, libcxx-commits
Differential Revision: https://reviews.llvm.org/D59882
llvm-svn: 357139
Eric Christopher [Thu, 28 Mar 2019 01:12:13 +0000 (01:12 +0000)]
Fix typoed variable name.
NFCI.
llvm-svn: 357138
Chandler Carruth [Thu, 28 Mar 2019 00:51:36 +0000 (00:51 +0000)]
[NewPM] Fix a nasty bug with analysis invalidation in the new PM.
The issue here is that we actually allow CGSCC passes to mutate IR (and
therefore invalidate analyses) outside of the current SCC. At a minimum,
we need to support mutating parent and ancestor SCCs to support the
ArgumentPromotion pass which rewrites all calls to a function.
However, the analysis invalidation infrastructure is heavily based
around not needing to invalidate the same IR-unit at multiple levels.
With Loop passes for example, they don't invalidate other Loops. So we
need to customize how we handle CGSCC invalidation. Doing this without
gratuitously re-running analyses is even harder. I've avoided most of
these by using an out-of-band preserved set to accumulate the cross-SCC
invalidation, but it still isn't perfect in the case of re-visiting the
same SCC repeatedly *but* it coming off the worklist. Unclear how
important this use case really is, but I wanted to call it out.
Another wrinkle is that in order for this to successfully propagate to
function analyses, we have to make sure we have a proxy from the SCC to
the Function level. That requires pre-creating the necessary proxy.
The motivating test case now works cleanly and is added for
ArgumentPromotion.
Thanks for the review from Philip and Wei!
Differential Revision: https://reviews.llvm.org/D59869
llvm-svn: 357137
Davide Italiano [Thu, 28 Mar 2019 00:07:33 +0000 (00:07 +0000)]
[Process] Reorder declarations and document ReadMemoryFromInferior.
llvm-svn: 357136
Davide Italiano [Thu, 28 Mar 2019 00:07:20 +0000 (00:07 +0000)]
[ObjectFileMachO] Remove another debugging aid.
Pointed out by Jason.
llvm-svn: 357135
Davide Italiano [Thu, 28 Mar 2019 00:07:07 +0000 (00:07 +0000)]
[ObjectFileMachO] Disable memory caching for savecore.
Summary:
It's not really useful, and largely increases the footprint.
<rdar://problem/
49293525>
Reviewers: jasonmolenda
Subscribers: llvm-commits, lldb-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59896
llvm-svn: 357134
Rui Ueyama [Wed, 27 Mar 2019 23:52:22 +0000 (23:52 +0000)]
[ELF] Dump symbols ordered by profiled guided section layout to file.
Patch by Tiancong Wang.
In D36351, Call-Chain Clustering (C3) heuristic is implemented with
option --call-graph-ordering-file <file>.
This patch adds a flag --print-symbol-order=<file> to LLD, and when
specified, it prints out the symbols ordered by the heuristics to the
file. The symbols printout is helpful to those who want to understand
the heuristics and want to reproduce the ordering with
--symbol-ordering-file in later pass.
Differential Revision: https://reviews.llvm.org/D59311
llvm-svn: 357133
Craig Topper [Wed, 27 Mar 2019 23:12:19 +0000 (23:12 +0000)]
[X86] Add test cases from PR27202.
llvm-svn: 357132
Nathan Lanza [Wed, 27 Mar 2019 23:00:47 +0000 (23:00 +0000)]
Teach TypeSystem about PDBASTParser
Currently, only ClangASTContext knows about PDBASTParser. Eventually
we want the TypeSystem to have getters/setters for the base parser
and then have the TypeSystem subclasses know about the proper
PDBASTParser subclasses. This is similar to how DWARFASTParsers work.
llvm-svn: 357131
Sam Clegg [Wed, 27 Mar 2019 23:00:12 +0000 (23:00 +0000)]
[ARM] Remove dead function ARMMCCodeEmitter::getSOImmOpValue
The last reference to this function was removed from the ARM
td files in 2015 in rL225266.
Differential Revision: https://reviews.llvm.org/D59868
llvm-svn: 357130
Sanjay Patel [Wed, 27 Mar 2019 22:42:11 +0000 (22:42 +0000)]
[x86] improve AVX lowering of vector zext
If we know the 2 halves of an oversized zext-in-reg are the same,
don't create those halves independently.
I tried several different approaches to fold this, but it's difficult
to get right during legalization. In the default path, we are creating
a generic shuffle that looks like an unpack high, but it can get
transformed into a different mask (a blend), so it's not
straightforward to match that. If we try to fold after it actually
becomes an X86ISD::UNPCKH node, we can't be sure what the operand node
is - it might be a generic shuffle, or it could be some x86-specific op.
From the test output, we should be doing something like this for SSE4.1
as well, but I'd rather leave that as a follow-up since it involves
changing lowering actions.
Differential Revision: https://reviews.llvm.org/D59777
llvm-svn: 357129
Sanjay Patel [Wed, 27 Mar 2019 22:24:03 +0000 (22:24 +0000)]
[x86] look through bitcast operand of MOVMSK
This is not exactly NFC because it should make further combines
of MOVMSK easier to match, but there should be no outward differences
because we have isel patterns in place specifically to allow this. See:
// Also support integer VTs to avoid a int->fp bitcast in the DAG.
llvm-svn: 357128
Derek Schuff [Wed, 27 Mar 2019 22:22:18 +0000 (22:22 +0000)]
Revert "[WebAssembly] Don't use default GetLinkerPath"
This reverts commit
4dcf3acce6d7455fd079d8e57441906ca2bad254.
(reverts LLVM SVN r356953)
llvm-svn: 357127
Jonas Devlieghere [Wed, 27 Mar 2019 21:45:11 +0000 (21:45 +0000)]
[Python] Remove unused includes
llvm-svn: 357126
Jan Vesely [Wed, 27 Mar 2019 21:28:31 +0000 (21:28 +0000)]
travis: Add LLVM-8 build
Reviewer: Tom Stellard
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 357125
Louis Dionne [Wed, 27 Mar 2019 21:28:24 +0000 (21:28 +0000)]
Restructure test suite to follow libc++ standard layout
Summary: Subsumes changes requested in https://reviews.llvm.org/D59110
Reviewers: EricWF, ldionne
Subscribers: mgorny, krytarowski, jfb, jdoerfert, libcxx-commits
Differential Revision: https://reviews.llvm.org/D59856
llvm-svn: 357124
Craig Topper [Wed, 27 Mar 2019 21:05:07 +0000 (21:05 +0000)]
[X86ISelDAGToDAG] Move initialization of OptForSize and OptForMinSize from PreprocessISelDAG to runOnMachineFunction. NFCI
This makes more sense as a place to initialize these. I don't think runOnMachineFunction was overriden when these cached values were originally created.
llvm-svn: 357123
Daniel Sanders [Wed, 27 Mar 2019 20:43:47 +0000 (20:43 +0000)]
test/CodeGen/X86/codegen-prepare-replacephi.mir requires a default triple
llvm-svn: 357122
Nirav Dave [Wed, 27 Mar 2019 20:37:08 +0000 (20:37 +0000)]
[DAGCombiner] Teach TokenFactor pruning to peek through lifetime nodes
Summary: Lifetime nodes were inhibiting TokenFactor simplification inhibiting chain-based optimizations.
Reviewers: courbet, jyknight
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59897
llvm-svn: 357121
Justin Bogner [Wed, 27 Mar 2019 20:35:56 +0000 (20:35 +0000)]
[LegalizeVectorTypes] Allow single loads and stores for more short vectors
When lowering a load or store for TypeWidenVector, the type legalizer
would use a single load or store if the associated integer type was legal
or promoted. E.g. it loads a v4i8 as an i32 if i32 is legal/promotable.
(See https://reviews.llvm.org/rL236528 for reference.)
This applies that behaviour to vector types. If the vector type is
TypePromoteInteger, the element type is going to be TypePromoteInteger
as well, which will lead to have a single promoting load rather than N
individual promoting loads. For instance, if we have a v3i1, we would
now have a load of v4i1 instead of 3 loads of i1.
Patch by Guillaume Marques. Thanks!
Differential Revision: https://reviews.llvm.org/D56201
llvm-svn: 357120
Nikita Popov [Wed, 27 Mar 2019 20:18:51 +0000 (20:18 +0000)]
[ConstantRangeTest] Add exhaustive intersectWith() test
Add a test that checks the intersectWith() implementation against
all 4-bit range pairs. The test uses a more explicit way of
calculating the possible intersections, and checks that the right
one is picked out according to the smallest set heuristic.
This is in preparation for introducing intersectWith() variants that
use different heuristics to pick an intersection range, if there are
multiple possibilities.
llvm-svn: 357119
Evgeniy Stepanov [Wed, 27 Mar 2019 20:15:08 +0000 (20:15 +0000)]
Fix llvm-rc tests.
Summary:
Follow-up for D56743.
* Add more "--" in llvm-rc invocations.
* Add llvm-rc to the tools list. This uses full path to llvm-rc in test
RUN lines (llvm-lit -v), making them copy-pasteable.
Reviewers: mstorsjo, zturner
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59858
llvm-svn: 357118
Alon Zakai [Wed, 27 Mar 2019 20:12:42 +0000 (20:12 +0000)]
[WebAssembly] Add some whitespace to WebAssemblyFixIrreducibleControlFlow
Differential Revision: https://reviews.llvm.org/D59855
modified: llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp
llvm-svn: 357117
Nirav Dave [Wed, 27 Mar 2019 19:54:41 +0000 (19:54 +0000)]
Revert r356996 "[DAG] Avoid smart constructor-based dangling nodes."
This patch appears to trigger very large compile time increases in
halide builds.
llvm-svn: 357116
Adrian Prantl [Wed, 27 Mar 2019 19:22:55 +0000 (19:22 +0000)]
Add LLDB_LIBDIR_SUFFIX to Config.h to unbreak the Xcode project
llvm-svn: 357115
Zinovy Nis [Wed, 27 Mar 2019 19:21:32 +0000 (19:21 +0000)]
[clang-tidy] Handle missing yaml module in run-clang-tidy.py
The Yaml module is missing on some systems and on many of clang buildbots.
But the test for run-clang-tidy.py doesn't fail due to 'NOT' statement masking a python runtime error.
This patch conditionally imports and enables the yaml module only if it's present in the system.
If not, then '-export-fixes' is disabled.
Differential Revision: https://reviews.llvm.org/D59734
llvm-svn: 357114
Nathan Lanza [Wed, 27 Mar 2019 19:15:13 +0000 (19:15 +0000)]
Kill unused variable m_tu_decl_up in SymbolFilePDB
Summary:
An TranslationUnitDecl was being brought in from the clang::ASTContext
which required clang specific code to exist in SymbolFilePDB.
Since it was unused we can just get rid of it along with the clang
specific code.
Reviewers: rnk, zturner, compnerd
Reviewed By: compnerd
Subscribers: jdoerfert
Differential Revision: https://reviews.llvm.org/D59804
llvm-svn: 357113
Nikita Popov [Wed, 27 Mar 2019 19:12:09 +0000 (19:12 +0000)]
[ConstantRange] Add isWrappedSet() and isUpperSignWrapped()
Split off from D59749. This adds isWrappedSet() and
isUpperSignWrapped() set with the same behavior as isSignWrappedSet()
and isUpperWrapped() for the respectively other domain.
The methods isWrappedSet() and isSignWrappedSet() will not consider
ranges of the form [X, Max] == [X, 0) and [X, SignedMax] == [X, SignedMin)
to be wrapping, while isUpperWrapped() and isUpperSignWrapped() will.
Also replace the checks in getUnsignedMin() and friends with method
calls that implement the same logic.
llvm-svn: 357112
Teresa Johnson [Wed, 27 Mar 2019 18:44:25 +0000 (18:44 +0000)]
[CGP] Reset DT when optimizing select instructions
Summary:
A recent fix (r355751) caused a compile time regression because setting
the ModifiedDT flag in optimizeSelectInst means that each time a select
instruction is optimized the function walk in runOnFunction stops and
restarts again (which was needed to build a new DT before we started
building it lazily in r356937). Now that the DT is built lazily, a
simple fix is to just reset the DT at this point, rather than restarting
the whole function walk.
In the future other places that set ModifiedDT may want to switch to
just resetting the DT directly. But that will require an evaluation to
ensure that they don't otherwise need to restart the function walk.
Reviewers: spatel
Subscribers: jdoerfert, llvm-commits, xur
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59889
llvm-svn: 357111
Jessica Paquette [Wed, 27 Mar 2019 18:35:04 +0000 (18:35 +0000)]
[opt-viewer] Teach optrecord.py about !Failure tags
WarnMissedTransforms.cpp produces remarks that use !Failure tags.
These weren't supported in optrecord.py, so if you encountered one in any of
the tools, the tool would crash.
Add them as a type of missed optimization.
Differential Revision: https://reviews.llvm.org/D59895
llvm-svn: 357110
Eli Friedman [Wed, 27 Mar 2019 18:33:30 +0000 (18:33 +0000)]
[ARM] Don't confuse the scheduler for very large VLDMDIA etc.
ARMBaseInstrInfo::getNumLDMAddresses is making bad assumptions about the
memory operands of load and store-multiple operations. This doesn't
really fix the problem properly, but it's enough to prevent crashing,
at least.
Fixes https://bugs.llvm.org/show_bug.cgi?id=41231 .
Differential Revision: https://reviews.llvm.org/D59834
llvm-svn: 357109
Amara Emerson [Wed, 27 Mar 2019 18:31:46 +0000 (18:31 +0000)]
[AArch64][GlobalISel] Make G_PHI of v2s64, v4s32, v2s32 legal.
llvm-svn: 357108
Nikita Popov [Wed, 27 Mar 2019 18:19:33 +0000 (18:19 +0000)]
[ConstantRange] Rename isWrappedSet() to isUpperWrapped()
Split out from D59749. The current implementation of isWrappedSet()
doesn't do what it says on the tin, and treats ranges like
[X, Max] as wrapping, because they are represented as [X, 0) when
using half-inclusive ranges. This also makes it inconsistent with
the semantics of isSignWrappedSet().
This patch renames isWrappedSet() to isUpperWrapped(), in preparation
for the introduction of a new isWrappedSet() method with corrected
behavior.
llvm-svn: 357107
Jessica Paquette [Wed, 27 Mar 2019 18:14:32 +0000 (18:14 +0000)]
[opt-viewer] Make filter_=None by default in get_remarks and gather_results
Right now, if you try to use optdiff.py on any opt records, it will fail because
its calls to gather_results weren't updated to support filtering.
Since filters are supposed to be optional, this makes them None by default in
get_remarks and in gather_results. This allows other tools that don't support
filtering to still use the functions as is.
Differential Revision: https://reviews.llvm.org/D59894
llvm-svn: 357106
Matt Arsenault [Wed, 27 Mar 2019 18:14:02 +0000 (18:14 +0000)]
RegPressure: Fix crash on blocks with only dbg_value
If there were only dbg_values in the block, recede would hit the
beginning of the block and try to use thet dbg_value as a real
instruction.
llvm-svn: 357105
Thomas Anderson [Wed, 27 Mar 2019 18:09:30 +0000 (18:09 +0000)]
Fix and speedup __libcpp_locale_guard on Windows
The old implementation assumed the POSIX `setlocale()` API where the old
locale is returned. On Windows, the _new_ locale is returned. This meant
that `__libcpp_locale_guard` wasn't resetting the locale on destruction.
The new implementation fixes the above issue and takes advantage of
`setlocale(LC_ALL)` to reduce the number of calls, and also avoids setting
the locale at all if it's not necessary.
Differential Revision: https://reviews.llvm.org/D59572
llvm-svn: 357104
Nikita Popov [Wed, 27 Mar 2019 17:56:15 +0000 (17:56 +0000)]
[InstCombine] Use uadd.sat and usub.sat for canonicalization
Start using the uadd.sat and usub.sat intrinsics for the existing
canonicalizations. These intrinsics should optimize better than
expanded IR, have better handling in the X86 backend and should
be no worse than expanded IR in other backends, as far as we know.
rL357012 already introduced use of uadd.sat for the add+umin pattern.
Differential Revision: https://reviews.llvm.org/D58872
llvm-svn: 357103
Sam McCall [Wed, 27 Mar 2019 17:47:49 +0000 (17:47 +0000)]
[clangd] Support utf-8 offsets (rather than utf-16) as a protocol extension
Summary:
Still some pieces to go here: unit tests for new SourceCode functionality and
a command-line flag to force utf-8 mode. But wanted to get early feedback.
Reviewers: hokein
Subscribers: ilya-biryukov, ioeric, MaskRay, jkorous, arphaman, kadircet, jdoerfert, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D58275
llvm-svn: 357102
Amara Emerson [Wed, 27 Mar 2019 17:47:42 +0000 (17:47 +0000)]
[GlobalISel] Fix legalizer artifact combiner from crashing with invalid dead instructions.
The artifact combiners push instructions which have been marked for deletion
onto an list for the legalizer to deal with on return. However, for trunc(ext)
combines the combiner routine recursively calls itself. When it does this the
dead instructions list may not be empty, and the other combiners don't expect
to be dealing with essentially invalid MIR (multiple vreg defs etc).
This change fixes it by ensuring that the dead instructions are processed on
entry into tryCombineInstruction.
As a result, this fix exposed a few places in tests where G_TRUNC instructions
were not being deleted even though they were dead.
Differential Revision: https://reviews.llvm.org/D59892
llvm-svn: 357101
Shafik Yaghmour [Wed, 27 Mar 2019 17:47:36 +0000 (17:47 +0000)]
[ASTImporter] Fix IsStructuralMatch specialization for EnumDecl to prevent re-importing an EnumDecl while trying to complete it
Summary:
We may try and re-import an EnumDecl while trying to complete it in IsStructuralMatch(...) specialization for EnumDecl. This change mirrors a similar fix for the specialization for RecordDecl.
Differential Revision: https://reviews.llvm.org/D59845
llvm-svn: 357100
Clement Courbet [Wed, 27 Mar 2019 17:44:16 +0000 (17:44 +0000)]
[X86MacroFusion][NFC] Add a bulldozer test.
llvm-svn: 357099
Matt Arsenault [Wed, 27 Mar 2019 17:31:29 +0000 (17:31 +0000)]
Reapply "AMDGPU: Scavenge register instead of findUnusedReg"
This reapplies r356149, using the correct overload of findUnusedReg
which passes the current iterator.
This worked most of the time, because the scavenger iterator was moved
at the end of the frame index loop in PEI. This would fail if the
spill was the first instruction. This was further hidden by the fact
that the scavenger wasn't passed in for normal frame index
elimination.
llvm-svn: 357098
Matt Arsenault [Wed, 27 Mar 2019 17:31:26 +0000 (17:31 +0000)]
AMDGPU: Add testcase I meant to merge into r357093
llvm-svn: 357097
Craig Topper [Wed, 27 Mar 2019 17:29:34 +0000 (17:29 +0000)]
[X86] Add post-isel pseudos for rotate by immediate using SHLD/SHRD
Haswell CPUs have special support for SHLD/SHRD with the same register for both sources. Such an instruction will go to the rotate/shift unit on port 0 or 6. This gives it 1 cycle latency and 0.5 cycle reciprocal throughput. When the register is not the same, it becomes a 3 cycle operation on port 1. Sandybridge and Ivybridge always have 1 cyc latency and 0.5 cycle reciprocal throughput for any SHLD.
When FastSHLDRotate feature flag is set, we try to use SHLD for rotate by immediate unless BMI2 is enabled. But MachineCopyPropagation can look through a copy and change one of the sources to be different. This will break the hardware optimization.
This patch adds psuedo instruction to hide the second source input until after register allocation and MachineCopyPropagation. I'm not sure if this is the best way to do this or if there's some other way we can make this work.
Fixes PR41055
Differential Revision: https://reviews.llvm.org/D59391
llvm-svn: 357096
Quentin Colombet [Wed, 27 Mar 2019 17:27:56 +0000 (17:27 +0000)]
[PeepholeOpt] Don't stop simplifying copies on sequence of subregs
This patch removes an overly conservative check that would prevent
simplifying copies when the value we were tracking would go through
several subregister indices.
Indeed, the intend of this check was to not track values whenever
we have to compose subregister, but actually what the check was
doing was bailing anytime we see a second subreg, even if that
second subreg would actually be the new source of truth (as opposed
to a part of that subreg).
Differential Revision: https://reviews.llvm.org/D59891
llvm-svn: 357095
Sander de Smalen [Wed, 27 Mar 2019 17:23:38 +0000 (17:23 +0000)]
[AArch64][SVE] Asm: error on unexpected SVE vector register type suffix
This patch fixes an assembler bug that allowed SVE vector registers to contain a
type suffix when not expected. The SVE unpredicated movprfx instruction is the
only instruction affected.
The following are examples of what was previously valid:
movprfx z0.b, z0.b
movprfx z0.b, z0.s
movprfx z0, z0.s
These instructions are now erroneous.
Patch by Cullen Rhodes (c-rhodes)
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D59636
llvm-svn: 357094
Matt Arsenault [Wed, 27 Mar 2019 17:14:32 +0000 (17:14 +0000)]
AMDGPU: Enable the scavenger for large frames
Another test is needed for the case where the scavenge fail, but
there's another issue with that which needs an additional fix.
llvm-svn: 357093
Casey Carter [Wed, 27 Mar 2019 17:03:44 +0000 (17:03 +0000)]
Fix occurrences of _LIBCPP_ASSERT in span tests
llvm-svn: 357092
Matt Arsenault [Wed, 27 Mar 2019 16:58:30 +0000 (16:58 +0000)]
AMDGPU: Add additional MIR tests for exec mask optimizations
Also includes one example of how this transform is unsound. This isn't
verifying the copies are used in the control flow intrinisic patterns.
Also add option to disable exec mask opt pass. Since this pass is
unsound, it may be useful to turn it off until it is fixed.
llvm-svn: 357091
Matt Arsenault [Wed, 27 Mar 2019 16:58:27 +0000 (16:58 +0000)]
AMDGPU: Skip debug_instr when collapsing end_cf
Based on how these are inserted, I doubt this was causing a problem in
practice.
llvm-svn: 357090
Matt Arsenault [Wed, 27 Mar 2019 16:58:22 +0000 (16:58 +0000)]
AMDGPU: Fix missing scc implicit def on s_andn2_b64_term
Introduce new helper class to copy properties directly from the base
instruction.
llvm-svn: 357089
Mikhail R. Gadelha [Wed, 27 Mar 2019 16:54:12 +0000 (16:54 +0000)]
New methods to check for under-/overflow in the SMT API
Summary: Added methods to check for under-/overflow in additions, subtractions, signed divisions/modulus, negations, and multiplications.
Reviewers: ddcc, gou4shi1
Reviewed By: ddcc, gou4shi1
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59796
llvm-svn: 357088
Matt Arsenault [Wed, 27 Mar 2019 16:37:31 +0000 (16:37 +0000)]
PEI: Delay checking requiresFrameIndexReplacementScavenging
Currently this is called before the frame size is set on the
function. For AMDGPU, the scavenger is used for large frames where
part of the offset needs to be materialized in a register, so
estimating the frame size is useful for knowing whether the scavenger
is useful.
llvm-svn: 357087
Jonas Devlieghere [Wed, 27 Mar 2019 16:23:50 +0000 (16:23 +0000)]
[Platform] Remove Kalimba Platform
This patch removes the Kalimba platform. For more information please
refer to the corresponding thread on the mailing list.
http://lists.llvm.org/pipermail/lldb-dev/2019-March/014921.html
llvm-svn: 357086
Andrea Di Biagio [Wed, 27 Mar 2019 16:22:36 +0000 (16:22 +0000)]
[MCA] Fix -Wparentheses warning breaking the -Werror build.
Waring was introduced at r357074.
llvm-svn: 357085
Matt Arsenault [Wed, 27 Mar 2019 16:12:29 +0000 (16:12 +0000)]
AMDGPU: Don't hardcode num defs for MUBUF instructions
This shouldn't change anything since the no-ret atomics are selected
later.
llvm-svn: 357084
Matt Arsenault [Wed, 27 Mar 2019 16:12:26 +0000 (16:12 +0000)]
MIR: Freeze reserved regs after parsing everything
The AMDGPU implementation of getReservedRegs depends on
MachineFunctionInfo fields that are parsed from the YAML section. This
was reserving the wrong register since it was setting the reserved
regs before parsing the correct one.
Some tests were relying on the default reserved set for the assumed
default calling convention.
llvm-svn: 357083
Haojian Wu [Wed, 27 Mar 2019 16:01:25 +0000 (16:01 +0000)]
[clangd] Bump vscode-clangd v0.0.12.
CHANGELOG:
- add an explicit command to activate the extension.
- support .cu files (the extension is not activated for .cu files by default,
you need to manually activate the extension).
llvm-svn: 357082
Matt Arsenault [Wed, 27 Mar 2019 15:54:45 +0000 (15:54 +0000)]
AMDGPU: wave_barrier is not isBarrier
This is not a control flow instruction, so should not be marked as
isBarrier. This fixes a verifier error if followed by unreachable.
llvm-svn: 357081
Pavel Labath [Wed, 27 Mar 2019 15:52:11 +0000 (15:52 +0000)]
Rename some variables in the std-module tests
They cause failures on some systems due to an unrelated bug (pr35043).
This works around that.
llvm-svn: 357080
Louis Dionne [Wed, 27 Mar 2019 15:50:34 +0000 (15:50 +0000)]
[libc++] Add proper XFAILs for shared_mutex tests
Dylib support for shared_mutex was added in macOS 10.12, so the tests
should be XFAILed accordingly instead of being completely disabled
whenever availability is enabled.
rdar://problem/
48769104
llvm-svn: 357079
Haojian Wu [Wed, 27 Mar 2019 15:50:33 +0000 (15:50 +0000)]
[clangd] Fix the inconsistent code indent in vscode extension, NFC.
llvm-svn: 357078
Yonghong Song [Wed, 27 Mar 2019 15:45:27 +0000 (15:45 +0000)]
[BPF] use std::map to ensure consistent output
The .BTF.ext FuncInfoTable and LineInfoTable contain
information organized per ELF section. Current definition
of FuncInfoTable/LineInfoTable is:
std::unordered_map<uint32_t, std::vector<BTFFuncInfo>> FuncInfoTable
std::unordered_map<uint32_t, std::vector<BTFLineInfo>> LineInfoTable
where the key is the section name off in the string table.
The unordered_map may cause the order of section output
different for different platforms.
The same for unordered map definition of
std::unordered_map<std::string, std::unique_ptr<BTFKindDataSec>>
DataSecEntries
where BTF_KIND_DATASEC entries may have different ordering
for different platforms.
This patch fixed the issue by using std::map.
Test static-var-derived-type.ll is modified to generate two
DataSec's which will ensure the ordering is the same for all
supported platforms.
Signed-off-by: Yonghong Song <yhs@fb.com>
llvm-svn: 357077
Clement Courbet [Wed, 27 Mar 2019 15:43:03 +0000 (15:43 +0000)]
[X86MacroFusion][NFC] Improve macrofusion testing.
Add negative tests.
Add arithmetic/inc/cmp/and macrofusion tests.
llvm-svn: 357076
Haojian Wu [Wed, 27 Mar 2019 15:41:59 +0000 (15:41 +0000)]
[clangd] Add activate command to the vscode extension.
Summary:
This would help minizime the annoying part of not activating the extension
for .cu file.
Reviewers: ilya-biryukov
Subscribers: ioeric, MaskRay, jkorous, arphaman, kadircet, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D59817
llvm-svn: 357075
Andrea Di Biagio [Wed, 27 Mar 2019 15:41:53 +0000 (15:41 +0000)]
[MCA][Pipeline] Don't visit stages in reverse order when calling method cycleEnd(). NFCI
There is no reason why stages should be visited in reverse order.
This patch allows the definition of stages that push instructions forward from
their cycleEnd() routine.
llvm-svn: 357074
Matt Arsenault [Wed, 27 Mar 2019 15:41:00 +0000 (15:41 +0000)]
AMDGPU: Fix areLoadsFromSameBasePtr for DS atomics
The offset operand index is different for atomics.
llvm-svn: 357073
Andrew Ng [Wed, 27 Mar 2019 15:30:52 +0000 (15:30 +0000)]
[LLD] Restore tests that use "-" as output
No longer require workarounds for output to "-" (stdout) for
Windows. These workarounds were just hiding the actual problem which has
been fixed in r357058.
Differential Revision: https://reviews.llvm.org/D59824
llvm-svn: 357072
Nico Weber [Wed, 27 Mar 2019 15:10:47 +0000 (15:10 +0000)]
gn build: Merge r357047
llvm-svn: 357071
Nirav Dave [Wed, 27 Mar 2019 14:14:46 +0000 (14:14 +0000)]
[DAGCombiner] Unify Lifetime and memory Op aliasing.
Rework BaseIndexOffset and isAlias to fully work with lifetime nodes
and fold in lifetime alias analysis.
This is mostly NFC.
Reviewers: courbet
Reviewed By: courbet
Subscribers: hiraditya, jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59794
llvm-svn: 357070
Nirav Dave [Wed, 27 Mar 2019 14:14:35 +0000 (14:14 +0000)]
[DAGCombine] Refactor GatherAllAliases. NFCI.
llvm-svn: 357069
Alexey Bataev [Wed, 27 Mar 2019 14:14:31 +0000 (14:14 +0000)]
[OPENMP]Initial support for 'allocate' clause.
Added parsing/sema analysis of the allocate clause.
llvm-svn: 357068
Hans Wennborg [Wed, 27 Mar 2019 14:10:11 +0000 (14:10 +0000)]
Re-commit r355490 "[CodeGen] Omit range checks from jump tables when lowering switches with unreachable default"
Original commit by Ayonam Ray.
This commit adds a regression test for the issue discovered in the
previous commit: that the range check for the jump table can only be
omitted if the fall-through destination of the jump table is
unreachable, which isn't necessarily true just because the default of
the switch is unreachable.
This addresses the missing optimization in PR41242.
> During the lowering of a switch that would result in the generation of a
> jump table, a range check is performed before indexing into the jump
> table, for the switch value being outside the jump table range and a
> conditional branch is inserted to jump to the default block. In case the
> default block is unreachable, this conditional jump can be omitted. This
> patch implements omitting this conditional branch for unreachable
> defaults.
>
> Differential Revision: https://reviews.llvm.org/D52002
> Reviewers: Hans Wennborg, Eli Freidman, Roman Lebedev
llvm-svn: 357067
Dmitry Preobrazhensky [Wed, 27 Mar 2019 13:49:52 +0000 (13:49 +0000)]
Revert of 357063 [AMDGPU][MC] Corrected handling of tied src for atomic return MUBUF opcodes
Reason: the change was mistakenly committed before review
llvm-svn: 357066
Kevin P. Neal [Wed, 27 Mar 2019 13:30:57 +0000 (13:30 +0000)]
The IR verifier currently supports the constrained floating point intrinsics,
but the implementation is hard to extend. It doesn't currently have an
easy way to support intrinsics that, for example, lack a rounding mode.
This will be needed for impending new constrained intrinsics.
This code is split out of D55897 <https://reviews.llvm.org/D55897>, which
itself was split out of D43515 <https://reviews.llvm.org/D43515>.
Reviewed by: arsenm
Differential Revision: http://reviews.llvm.org/D59830
llvm-svn: 357065
Sander de Smalen [Wed, 27 Mar 2019 13:16:19 +0000 (13:16 +0000)]
[AArch64] NFC: Cleanup isAArch64FrameOffsetLegal
Cleanup isAArch64FrameOffsetLegal by:
- Merging the large switch statement to reuse AArch64InstrInfo::getMemOpInfo().
- Using AArch64InstrInfo::getUnscaledLdSt() to determine whether an instruction
has an unscaled variant.
- Simplifying the logic that calculates the offset to fit the immediate.
Reviewers: paquette, evandro, eli.friedman, efriedma
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D59636
llvm-svn: 357064
Dmitry Preobrazhensky [Wed, 27 Mar 2019 13:07:41 +0000 (13:07 +0000)]
[AMDGPU][MC] Corrected handling of tied src for atomic return MUBUF opcodes
See bug 40917: https://bugs.llvm.org/show_bug.cgi?id=40917
Reviewers: artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D59305
llvm-svn: 357063
Simon Pilgrim [Wed, 27 Mar 2019 11:21:09 +0000 (11:21 +0000)]
[X86][SSE] Add shuffle test case for PR41249
llvm-svn: 357062
George Rimar [Wed, 27 Mar 2019 11:00:03 +0000 (11:00 +0000)]
Revert the r348352 "[clang] - Simplify tools::SplitDebugName."
This partially reverts the r348352 (https://reviews.llvm.org/D55006)
because of https://bugs.llvm.org/show_bug.cgi?id=41161.
I did not revert the test case file because it passes fine now.
llvm-svn: 357061
Pavel Labath [Wed, 27 Mar 2019 10:54:10 +0000 (10:54 +0000)]
minidump: Add ability to attach (breakpad) symbol files to placeholder modules
This re-commits r354263, which was because it uncovered with handling of
modules with empty (zero) UUIDs. This would cause us to treat two
modules as intentical even though they were not. This caused an assert
in PlaceholderObjectFile::SetLoadAddress to fire, because we were trying
to load the module twice even though it was designed to be only loaded
at a specific address. (The same problem also existed with the previous
implementation, but it had no asserts to warn us about this.) These
issues have now been fixed in r356896.
windows bot. The issue there was that ObjectFilePECOFF vended its base
address through the incorrect interface. SymbolFilePDB depended on that,
which lead to assertion failures when SymbolFilePDB was attempting to
use the placeholder object files as a base. This has been fixed in
r354258
The original commit message was:
The reason this wasn't working was that ProcessMinidump was creating odd
object-file-less modules, and SymbolFileBreakpad required the module to
have an associated object file because it needed to get its base
address.
This fixes that by introducing a PlaceholderObjectFile to serve as a
dummy object file. The general idea for this is taken from D55142, but
I've reworked it a bit to avoid the need for the PlaceholderModule
class. Now that we have an object file, our modules are sufficiently
similar to regular modules that we can use the regular Module class
almost out of the box -- the only thing I needed to tweak was the
Module::CreateModuleFromObjectFile functon to set the module's FileSpec
in addition to it's architecture. This wasn't needed for ObjectFileJIT
(the other user of CreateModuleFromObjectFile), but it shouldn't hurt it
either, and the change seems like a straightforward extension of this
function.
Reviewers: clayborg, lemo, amccarth
Subscribers: lldb-commits
Differential Revision: https://reviews.llvm.org/D57751
llvm-svn: 357060
Sander de Smalen [Wed, 27 Mar 2019 10:39:03 +0000 (10:39 +0000)]
[AArch64] Adds cases for LDRSHWui and LDRSHXui to getMemOpInfo
This patch also adds cases PRFUMi and PRFMui.
This change was discussed in https://reviews.llvm.org/D59635.
llvm-svn: 357059
Andrew Ng [Wed, 27 Mar 2019 10:26:21 +0000 (10:26 +0000)]
[Support] MemoryBlock size should reflect the requested size
This patch mirrors the change made to the Unix equivalent in
r351916. This in turn fixes bugs related to the use of FileOutputBuffer
to output to "-", i.e. stdout, on Windows.
Differential Revision: https://reviews.llvm.org/D59663
llvm-svn: 357058
Simon Pilgrim [Wed, 27 Mar 2019 10:25:02 +0000 (10:25 +0000)]
Revert rL356864 : [X86][SSE41] Start shuffle combining from ZERO_EXTEND_VECTOR_INREG (PR40685)
Enable SSE41 ZERO_EXTEND_VECTOR_INREG shuffle combines - for the PMOVZX(PSHUFD(V)) -> UNPCKH(V,0) pattern we reduce the shuffles (port5-bottleneck on Intel) at the expense of creating a zero (pxor v,v) and an extra register move - which is a good trade off as these are pretty cheap and in most cases it doesn't increase register pressure.
This also exposed a missed opportunity to use combine to ZERO_EXTEND_VECTOR_INREG with folded loads - even if we're in the float domain.
........
Causes PR41249
llvm-svn: 357057
Pavel Labath [Wed, 27 Mar 2019 10:02:36 +0000 (10:02 +0000)]
Fix a "memset clearing an object of non-trivial type" warning in DWARFFormValue
This is diagnosed by gcc-8. The ValueType struct already has a default
constructor which performs zero-initialization, so we can just call that
instead of using memset.
llvm-svn: 357056
Pavel Labath [Wed, 27 Mar 2019 09:39:46 +0000 (09:39 +0000)]
Fix an out-of-bounds error in RegisterContextDarwin_arm64
Summary:
gcc diagnoses this as "array subscript 63 is above array bounds of
'RegisterContextDarwin_arm64::VReg [32]'".
The correct fix seems to be subtracting the fpu register base index, but
I have no way of verifying that this actually works.
Reviewers: jasonmolenda
Subscribers: javed.absar, kristof.beyls, lldb-commits
Differential Revision: https://reviews.llvm.org/D59495
llvm-svn: 357055
Fangrui Song [Wed, 27 Mar 2019 09:38:05 +0000 (09:38 +0000)]
[DWARF] Add D to Seen early to avoid duplicate elements in Worklist
llvm-svn: 357054
Fangrui Song [Wed, 27 Mar 2019 08:43:21 +0000 (08:43 +0000)]
[DWARF] Simplify DWARFVerifier::handleDebugAbbrev. NFC
llvm-svn: 357053
Jonas Paulsson [Wed, 27 Mar 2019 08:41:46 +0000 (08:41 +0000)]
[DAGCombiner] Don't allow addcarry if the carry producer is illegal.
getAsCarry() checks that the input argument is a carry-producing node before
allowing a transformation to addcarry. This patch adds a check to make sure
that the carry-producing node is legal. If it is not, it may not remain in a
form that is manageable by the target backend. The test case caused a
compilation failure during instruction selection for this reason on SystemZ.
Patch by Ulrich Weigand.
Review: Sanjay Patel
https://reviews.llvm.org/D59822
llvm-svn: 357052
Fangrui Song [Wed, 27 Mar 2019 08:19:36 +0000 (08:19 +0000)]
[llvm-dwarfdump] Simplify -o handling
ToolOutputFile handles '-' so no need to specialize here.
Also, we neither reassign the variable nor pass it around, thus no need
to use std::unique_ptr<ToolOutputFile>.
exit(1) -> return 1; to call the destructor of raw_fd_stream
llvm-svn: 357051
Craig Topper [Wed, 27 Mar 2019 06:07:05 +0000 (06:07 +0000)]
[X86] Add test cases for missed opportunities in (x << C1) op C2 to (x op (C2>>C1)) << C1 transform.
We handle the case where the C2 does not fit in a signed 32-bit immediate, but
(C2>>C1) does. But there's also some 64-bit opportunities when C2 is not an unsigned
32-bit immediate, but (C2>>C1) is. For OR/XOR this allows us to load the
immediate with with MOV32ri instead of a movabsq. For AND it allows us to use a
32-bit AND and fold the immediate.
llvm-svn: 357050
Craig Topper [Wed, 27 Mar 2019 04:45:58 +0000 (04:45 +0000)]
[X86] When iselling (x << C1) and/or/xor C2 as (x and/or/xor (C2>>C1)) << C1, go through the isel table instead of manually selecting.
Previously we manually selected the AND/OR/XOR with immediate and the SHL(or ADD if the shift is 1). But this was missing out on the opportunity to use a 64 bit AND with a 32-bit immediate and possibly other isel tricks we have built into the tables.
Instead, insert the new nodes into the DAG using insertDAGNode and allow them each to be selected through the normal table.
llvm-svn: 357049
Yi Kong [Wed, 27 Mar 2019 04:18:37 +0000 (04:18 +0000)]
Revert "[builtins] Rounding mode support for addxf3/subxf3"
This reverts commit
2cabea054e40ae2837da959d0ca89ae25cf1b1f1.
Test failure on buildbots.
llvm-svn: 357048
QingShan Zhang [Wed, 27 Mar 2019 03:50:16 +0000 (03:50 +0000)]
[NFC][PowerPC] Custom PowerPC specific machine-scheduler
This patch lays the groundwork for extending the generic machine scheduler by providing a PPC-specific implementation.
There are no functional changes as this is an incremental patch that simply provides the necessary overrides which just
encapsulate the behavior of the generic scheduler. Subsequent patches will add specific behavior.
Differential Revision: https://reviews.llvm.org/D59284
llvm-svn: 357047
Craig Topper [Wed, 27 Mar 2019 02:18:41 +0000 (02:18 +0000)]
[X86] Autogenerate complete checks. NFC
llvm-svn: 357046
Craig Topper [Wed, 27 Mar 2019 02:08:03 +0000 (02:08 +0000)]
[X86] Simplify some code in matchBitExtract by using ANY_EXTEND.
We were manually outputting the code we would get from selecting ANY_EXTEND. We
can save some code by just letting an ANY_EXTEND go through isel on its own.
llvm-svn: 357045
Nathan Lanza [Wed, 27 Mar 2019 01:24:03 +0000 (01:24 +0000)]
Get the lang from the CompileUnit for ParseCompileUnitFunctionForPDBFunc
Summary:
Instead of assuming that the language is C++ instead check the compunit
for the language it received from the debug info.
Subscribers: aprantl, jdoerfert
Differential Revision: https://reviews.llvm.org/D59805
llvm-svn: 357044
Francis Visoiu Mistrih [Wed, 27 Mar 2019 01:13:59 +0000 (01:13 +0000)]
[Remarks] Emit a section containing remark diagnostics metadata
A section containing metadata on remark diagnostics will be emitted if
the flag (-mllvm) -remarks-section is present.
For now, the metadata is:
* a magic number for remarks: "REMARKS\0"
* the version number: a little-endian uint64_t
* the absolute file path to the serialized remark diagnostics: a
null-terminated string.
Differential Revision: https://reviews.llvm.org/D59571
llvm-svn: 357043
Nico Weber [Wed, 27 Mar 2019 00:17:05 +0000 (00:17 +0000)]
gn build: Add build files for clang-include-fixer and find-all-symbols
Differential Revision: https://reviews.llvm.org/D59838
llvm-svn: 357042