Jason Ekstrand [Fri, 9 Jul 2021 13:09:46 +0000 (08:09 -0500)]
nir: Validate newly documented texture restrictions
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Mike Blumenkrantz [Fri, 7 May 2021 18:06:23 +0000 (14:06 -0400)]
nir/validate: refactor validate_assert to have a return value
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Erik Faye-Lund [Mon, 12 Jul 2021 20:00:01 +0000 (15:00 -0500)]
dxil: Set coord_components on the txf in lower_int_sampler
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Jason Ekstrand [Fri, 9 Jul 2021 16:34:23 +0000 (11:34 -0500)]
nir/lower_tex: Rework invalid implicit LOD lowering
Only fragment and some compute shaders support implicit derivatives.
They're totally meaningless without helper invocations and some
understanding of the dispatch pattern. We've got code to lower
nir_texop_tex in these shader stages to use an explicit derivative of 0
but it was pretty badly broken:
1. It only handled nir_texop_tex, not nir_texop_txb or nir_texop_lod.
2. It didn't take min_lod into account
3. It was conflated with adding a missing LOD parameter to opcodes
which expect one such as nir_texop_txf. While not really a bug,
this does make it way harder to reason about the code.
4. Unless you set a flag (which most drivers don't), it left the
opcode nir_texop_tex instead of nir_texop_txl which it should have
been.
This reworks it to go through roughly the same path as other LOD
lowering only with a constant lod of 0 instead of calling out to
nir_texop_lod. We also get rid of the lower_tex_without_implicit_lod
flag because most drivers set it and those that don't are probably
subtly broken. If someone really wants to get nir_texop_tex in their
vertex shaders, they can write a new patch to add the flag back in.
Fixes:
e382890e25c0 "nir: set default lod to texture opcodes that..."
Fixes:
d5ac5d6e836f "nir: Add option to lower tex to txl when..."
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Alyssa Rosenzweig [Fri, 23 Jul 2021 15:44:35 +0000 (11:44 -0400)]
pan/mdg: Garbage collect silly quirk
As discussed with Jason and Connor, this is probably subtly broken on
Mali T720.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Jason Ekstrand [Fri, 9 Jul 2021 13:56:17 +0000 (08:56 -0500)]
intel/blorp: Use nir_texop_txl
We set an explicit LOD immediately afterwards so we don't want implicit
mipmap selection.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Jason Ekstrand [Wed, 7 Jul 2021 22:44:27 +0000 (17:44 -0500)]
docs,nir: Document NIR texture instructions
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Jason Ekstrand [Wed, 7 Jul 2021 22:06:46 +0000 (17:06 -0500)]
nir: Suffix all the MCS texture stuff _intel
It's intel-specific, used to get at MSAA compression information.
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Jason Ekstrand [Fri, 9 Jul 2021 15:57:39 +0000 (10:57 -0500)]
panfrost: Don't handle nir_texop_txf_ms_mcs
It's an intel-specific opcode and will never be seen on panfrost
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Jason Ekstrand [Fri, 9 Jul 2021 13:32:01 +0000 (08:32 -0500)]
amd: Don't handle nir_tex_src_ms_mcs
It's an intel-specific texture source and will never be seen on AMD.
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Jason Ekstrand [Wed, 7 Jul 2021 22:06:16 +0000 (17:06 -0500)]
ttn: Don't handle texop_txf_ms_mcs
It's an intel-specific opcode and will never come through TGSI.
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Juan A. Suarez Romero [Fri, 23 Jul 2021 12:16:10 +0000 (14:16 +0200)]
v3d: handle debug options with debug_named_value
Switch from using debug_control structure to debug_named_value
structure.
The main nice feature is that it provides a "help" option, so using
"V3D_DEBUG=help" will print all the debug options with a brief
description.
Useful to avoid going to https://docs.mesa3d.org/envvars.html everytime
we need to know the available options.
v1:
- Modify a couple of debug option documentation (Alejandro)
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12036>
Alyssa Rosenzweig [Thu, 22 Jul 2021 15:28:44 +0000 (11:28 -0400)]
targets/graw-xlib: Add missing dep_x11
Required to build Mesa on macOS with
-Dbuild-tests=true -Dglx=gallium-xlib
Without this change, the build fails with
In file included from ../src/gallium/targets/graw-xlib/graw_xlib.c:8:
../src/gallium/include/frontend/xlibsw_api.h:5:10: fatal error: 'X11/Xlib.h' file not found
#include <X11/Xlib.h>
With `brew sh` X11 is found but linking fails due to `llvm-ar` missing
in the path. That issue appears to be unrelated to this missing
dependency. X11 is installed via XQuartz, so Homebrew should not be
required.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12022>
Timothy Arceri [Wed, 14 Jul 2021 07:29:46 +0000 (17:29 +1000)]
glsl: relax rule on varying matching for shaders older than 4.20
This expands on commit
c54c42321ea5. See the code comment for full
justifications. At the time of the previous commit Ian wanted to
limit the relaxing of the rule to GLSL 3.30 as that was the highest
version of shaders seen in the wild that were having trouble with
the stricter rules.
However since then I've found that the long standing issue with tess
shaders failing to compile in the game 'Layers Of Fear' is due to
this same issue. The game uses 4.10 shaders and also makes use of
explicit varying locations, so here we relax the rule to 4.20 and
make sure to apply the restriction to shaders using varyings with
explicit locations also.
Fixes:
c54c42321ea5 ("glsl: relax rule on varying matching for shaders older than 4.00")
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11873>
Dave Airlie [Mon, 20 Jul 2020 21:05:17 +0000 (07:05 +1000)]
draw/llvmpipe: multiply polygon offset units by 2
I was trying to fix this test, but noticed brw_clip.c in i965
does a * 2 here, and it seems to fix this test as well.
Fixes:
dEQP-GLES2.functional.polygon_offset.default_displacement_with_units
Fixes:
f9e2c2432686 ("draw,llvmpipe,util: add depth bias calculation for arb_depth_buffer_float")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12029>
Sagar Ghuge [Wed, 21 Jul 2021 22:24:29 +0000 (15:24 -0700)]
intel/compiler: Handle ternary add in lower_simd_width
We need to lower the add3 instruction simd width otherwise in simd32
mode, we endup writing 4 register wide data which is not allowed.
Reported-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11985>
Sagar Ghuge [Tue, 20 Jul 2021 02:29:03 +0000 (19:29 -0700)]
intel/compiler: Fix missing break in switch
CoverityID: 1487496
Fixes:
cde9ca616d7 "intel/compiler: Make decision based on source type instead of opcode"
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11985>
Alyssa Rosenzweig [Thu, 22 Jul 2021 21:34:07 +0000 (17:34 -0400)]
panfrost,panvk: Remove broken v4 spilling code
Tells you how much use Mali T720 gets that nobody noticed but
Icecream95...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-by: Icecream95 <ixn@disroot.org>
Acked-by: Icecream95 <ixn@disroot.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12027>
Emma Anholt [Wed, 21 Jul 2021 18:50:24 +0000 (11:50 -0700)]
freedreno: Lock access to msm_pipe for RB object suballocation.
Hopefully this fixes the flakes that have happened since the suballoc
changes.
Fixes:
737d4caa83a9 ("freedreno: Suballocate our long-lived ring objects.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12002>
Eric Anholt [Fri, 12 Mar 2021 21:53:33 +0000 (13:53 -0800)]
gallium/ureg: Sort the output decls.
glsl_to_tgsi had been emitting outputs in sorted order, and it seems virgl
has a dependency on that -- it collects outputs into an array and indexes
by the subtracting the ".First" value of the first one seen, even if
that's not the first entry in the array.
Fixes the regressions in deqp-gles2 on virgl with ST_DEBUG=force_nir, and
fixes neverball trace rendering.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11934>
Jason Ekstrand [Tue, 20 Jul 2021 23:44:15 +0000 (18:44 -0500)]
intel/eu: Don't validate LSC transpose on ops that don't have it
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11991>
Dave Airlie [Thu, 15 Jul 2021 04:52:07 +0000 (14:52 +1000)]
gallivm/img: use uint for image coord builder.
VK CTS has a test that does -256 for sample index but since we use
signed >= we fail and write to random memory, changing to uint here
for comparisons for out of bounds and address calcs should ensure,
we stay within bounds even for negative vals.
Remove unused int_type/bld while here.
Fixes dEQP-VK.texture.multisample.invalid_sample_index.sample_count_4
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11913>
Dave Airlie [Thu, 15 Jul 2021 00:01:28 +0000 (10:01 +1000)]
llvmpipe: rework query fence signalling for get_query_result_resource
For compute shaders stats avail was never signalling because nothing
flushed.
Fixes dEQP-VK.query_pool.statistics_query.host_query_reset.compute_shader_invocations.64bits_cmdcopyquerypoolresults_primary
and others
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11913>
Jason Ekstrand [Wed, 21 Jul 2021 21:52:35 +0000 (16:52 -0500)]
turnip: Replace tu_lower_image_size with nir_lower_image
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12005>
Jason Ekstrand [Wed, 21 Jul 2021 21:41:14 +0000 (16:41 -0500)]
radv,radeonsi: Do cube size divide-by-6 lowering in NIR
No point in carrying all this code around twice each in two back-ends.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12005>
Jason Ekstrand [Wed, 21 Jul 2021 21:39:15 +0000 (16:39 -0500)]
nir/lower_tex: Add a lower_txs_cube_array option
Several bits of hardware require the division by 6 to happen in the
shader. May as well have common lowering for it.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12005>
Jason Ekstrand [Thu, 22 Jul 2021 05:17:33 +0000 (00:17 -0500)]
nir/lower_image: Handle index and bindless image_size
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12005>
Alyssa Rosenzweig [Wed, 21 Jul 2021 19:14:17 +0000 (15:14 -0400)]
pan/bi: Mark mod to string as maybe unused
Fixes warnings like the following under clang:
src/panfrost/bifrost/bi_printer.c:599:1: warning: unused function 'bi_widen_as_str' [-Wunused-function]
bi_widen_as_str(enum bi_widen widen)
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12003>
Alyssa Rosenzweig [Wed, 21 Jul 2021 19:14:17 +0000 (15:14 -0400)]
pan/bi: Remove duplicate NIR compiler options
Fixes the warning caught by clang (why did gcc miss this one?)
../src/panfrost/bifrost/bifrost_compile.h:81:45: warning: initializer overrides prior initialization of this subobject [-Winitializer-overrides]
.lower_bitfield_extract_to_shifts = true,
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12003>
Alyssa Rosenzweig [Wed, 21 Jul 2021 19:14:17 +0000 (15:14 -0400)]
pan/bi: Add explicit cast for lod_or_mode
The enums alias. Fixes the following warning under clang:
../src/panfrost/bifrost/bifrost_compile.c:2515:25: warning: implicit conversion from enumeration type 'enum bifrost_texture_fetch' to different enumeration type 'enum bifrost_lod_mode' [-Wenum-conversion]
BIFROST_TEXTURE_FETCH_TEXEL;
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12003>
Alyssa Rosenzweig [Wed, 21 Jul 2021 19:14:17 +0000 (15:14 -0400)]
panfrost: Only build libpanfrost with GL/VK
It's not needed for the standalone compiler. These depend on xf86drm.h which is
not available on other platforms where we might want to build the standalone
compiler.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12003>
Alyssa Rosenzweig [Wed, 21 Jul 2021 19:14:17 +0000 (15:14 -0400)]
panfrost: Remove unnecessary bifrost_compiler deps
These dependencies are not necessarily portbale, but bifrost_compiler itself is.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12003>
Alyssa Rosenzweig [Wed, 21 Jul 2021 19:14:17 +0000 (15:14 -0400)]
meson: Build panfrost with tools=panfrost
...even if neither GL or VK drivers are being built. Useful for building the
standalone compiler on non-Linux systems.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12003>
Kai Wasserbäch [Thu, 22 Jul 2021 05:42:12 +0000 (07:42 +0200)]
gallivm: fix FTBFS on i386 with LLVM >= 13, StackAlignmentOverride is gone
Use the newly added wrapper lp_set_module_stack_alignment_override() to
achieve the same end result.
Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Closes: mesa/mesa#4906
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11940>
Kai Wasserbäch [Thu, 22 Jul 2021 05:34:09 +0000 (07:34 +0200)]
gallivm: add new wrapper around Module::setOverrideStackAlignment()
We need it in the next commit to replace setting the stack alignment on
i386 with LLVM >= 13 through the TargetOption::StackAlignmentOverride,
which was removed in the upstream commit
<https://github.com/llvm/llvm-project/commit/
3787ee457173c3612aac4c9b1a2b6d6ab0202616>.
Unfortunately Module::setOverrideStackAlignment() is not available
through the C API and we need to wrap it ourselves.
Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reference: mesa/mesa#4906
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11940>
Simon Ser [Fri, 9 Jul 2021 11:10:24 +0000 (13:10 +0200)]
egl: add support for EGL_EXT_device_drm_render_node
This new EGL extension has been introduced in [1].
When we have a DRM device and a render node, we can advertise the
extension and return the render node name for the
EGL_DRM_RENDER_NODE_FILE_EXT query.
For the special software EGL device, we can advertise the extension
and return NULL for the EGL_DRM_RENDER_NODE_FILE_EXT query, because
we can guarantee that llvmpipe will never use a render node for
rendering operations.
However, llvmpipe might be using a primary node when used with the
GBM platform. So we can't advertise EXT_device_drm in this case.
When we have a DRM device but no render node, that means we're on a
split render/display SoC. We _should_ return the render node used
by the renderonly driver, however Mesa needs more plumbing to allow
this, so let's just disable the extension for now.
[1]: https://github.com/KhronosGroup/EGL-Registry/pull/127
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11797>
Simon Ser [Fri, 9 Jul 2021 10:30:14 +0000 (12:30 +0200)]
EGL: sync headers with Khronos
Taken from EGL-Registry commit
dc0b58dca533c5882c38bc623d133190fff883a4.
Signed-off-by: Simon Ser <contact@emersion.fr>
Acked-by: Emil Velikov <emil.l.velikov@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11797>
Juan A. Suarez Romero [Thu, 22 Jul 2021 14:56:56 +0000 (16:56 +0200)]
ci/v3d: add piglit flake test
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12020>
Rhys Perry [Wed, 21 Jul 2021 19:18:12 +0000 (20:18 +0100)]
aco: don't create v_madmk_f32/v_madak_f32 from v_fma_legacy_f16
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5105
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12004>
Rob Clark [Thu, 22 Jul 2021 03:12:10 +0000 (20:12 -0700)]
freedreno/registers: update dsi registers to support tpg
Based-on: https://patchwork.freedesktop.org/patch/445672/?series=92870&rev=1
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12021>
Timothy Arceri [Sat, 17 Jul 2021 11:39:55 +0000 (21:39 +1000)]
util: add workaround for Full Bore
Unfortunately I contacted the dev about this issue years ago and he
made a fix, but it has never been released after all these years.
This stops the screen from being completely black in game.
CC: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11941>
Dave Airlie [Mon, 19 Jul 2021 01:57:12 +0000 (11:57 +1000)]
llvmpipe: add support for time elapsed queries.
It turns out for QBO you really need to explicitly support time
elapsed queries to avoid wierd interactions with the non-qbo
query paths.
Fixes:
506e51b8560f ("llvmpipe: initial query buffer object support. (v2)")
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11946>
Daniel Stone [Thu, 22 Jul 2021 07:40:48 +0000 (08:40 +0100)]
Revert "CI: Disable LAVA devices"
This reverts commit
1f4ff4ed2e6fbefb5026d8300a80049ccf4912a5.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12016>
Mike Blumenkrantz [Fri, 21 May 2021 20:45:41 +0000 (16:45 -0400)]
zink: fix cached descriptor allocation clamping
the number of allocated sets should be directly compared to the maximum
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11690>
Mike Blumenkrantz [Fri, 21 May 2021 21:17:09 +0000 (17:17 -0400)]
zink: improve lazy descriptor pool handling
do set allocation when getting pool, queue filled pools for delete
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11690>
Mike Blumenkrantz [Tue, 1 Jun 2021 12:09:14 +0000 (08:09 -0400)]
zink: add define for descriptor alloc clamping
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11690>
Mike Blumenkrantz [Fri, 21 May 2021 20:45:08 +0000 (16:45 -0400)]
zink: clamp descriptor allocation bucket sizing to defined limit
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11690>
Mike Blumenkrantz [Wed, 12 May 2021 12:27:12 +0000 (08:27 -0400)]
zink: split mem cache per type
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11966>
Mike Blumenkrantz [Wed, 12 May 2021 12:18:08 +0000 (08:18 -0400)]
zink: inline mem cache hash table
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11966>
Mike Blumenkrantz [Wed, 12 May 2021 12:15:25 +0000 (08:15 -0400)]
zink: move mem cache to sub-struct
no functional changes
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11966>
Mike Blumenkrantz [Sat, 15 May 2021 14:20:43 +0000 (10:20 -0400)]
zink: rework oom flushing
tracking mem usage on the context is bad because if an app is always using
a large amount of memory across multiple batches, it triggers the oom flushes
on every flush and forces fencing
instead, add an explicit flag for oom flushing and another for stalling, then
flag oom flushing and stalling as needed, with set_framebuffer_state being an
additional flush point now since it's guaranteed not to split renderpasses
also proactively prune pending batch states if there's a lot of them
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11965>
Mike Blumenkrantz [Wed, 9 Jun 2021 18:12:13 +0000 (14:12 -0400)]
zink: add a param to check_batch_completion for toggling lock-taking
need this to avoid deadlocks
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11965>
Mike Blumenkrantz [Tue, 20 Jul 2021 00:41:17 +0000 (20:41 -0400)]
zink: use a local var for draw mode during draw
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11965>
Mike Blumenkrantz [Tue, 11 May 2021 23:42:20 +0000 (19:42 -0400)]
zink: make batch_rp and norp static inlines
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11965>
Mike Blumenkrantz [Tue, 11 May 2021 23:42:12 +0000 (19:42 -0400)]
zink: make zink_end_render_pass public
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11965>
Mike Blumenkrantz [Tue, 11 May 2021 23:29:36 +0000 (19:29 -0400)]
zink: split draw_count checking to local variable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11965>
Mike Blumenkrantz [Tue, 11 May 2021 22:13:02 +0000 (18:13 -0400)]
zink: split and move maybe_flush_or_stall mechanic
the batch state counting belongs in the flush call, and draws/computes
should each just check their counts and flush directly
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11965>
Mike Blumenkrantz [Thu, 13 May 2021 19:54:36 +0000 (15:54 -0400)]
zink: handle vertex buffer offset overflows
there's a screen limit for vertex buffer offsets (???), so if a buffer
is going to overflow that limit, just rebind it as a new tmp buffer and
clamp the offset to 0
this also applies to buffer rebinds
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11836>
Mike Blumenkrantz [Fri, 14 May 2021 14:44:02 +0000 (10:44 -0400)]
zink: change vbo_bind_count to a mask of slots
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11836>
Mike Blumenkrantz [Thu, 13 May 2021 18:54:43 +0000 (14:54 -0400)]
zink: add mechanism for generating VkBuffers for rebinding
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11836>
Chia-I Wu [Wed, 21 Jul 2021 00:52:47 +0000 (17:52 -0700)]
meson: allow egl_native_platform to be specified
After commit
f8dc22bf61c, it was no longer possible to have explicitly
enabled platforms with surfaceless being the EGL native platform. This
fixes that by adding -Degl-native-platform.
Fixes:
f8dc22bf61c ("meson: drop deprecated EGL platform build options")
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11992>
Chia-I Wu [Tue, 20 Jul 2021 21:31:46 +0000 (14:31 -0700)]
egl/surfaceless: try kms_swrast before swrast
Before commit
f7e0cdcf1a5, we tried these in order
- if (!ForceSoftware) surfaceless_probe_device(disp, false);
- surfaceless_probe_device(disp, true);
- surfaceless_probe_device_sw(disp);
The commit changed it to
- surfaceless_probe_device(disp, ForceSoftware);
- surfaceless_probe_device_sw(disp);
and broke 2D virtio-gpu and vgem when ForceSoftware is false. This
commit restores the old behavior.
Fixes:
f7e0cdcf1a5 ("egl/surfaceless: simplify dri2_initialize_surfaceless()")
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11992>
Roland Scheidegger [Mon, 19 Jul 2021 15:32:17 +0000 (17:32 +0200)]
llvmpipe: always use draw_regions intersection
This was still used in the linear branch, since it works all a little
differently there (in particular, when using guard band we have to
intersect the draw regions with the viewport, since draw won't clip
for us). However, we should always intersect with draw_regions
(regardless if that includes the intersection with vp or not), since
the viewport can be larger than the fb size, and we don't want to
draw outside the fb (usually harmless, but important for occlusion
queries and shader image/buffer writes).
This fixes various dEQP-GLES31.functional.fbo.no_attachments failures
(which uses oversized viewport with occlusion queries).
The other ci changes aren't really bugs (the humus/Portals image
looks the same, we cannot expect bit-identical results, and
for the piglit quad-invariance test, I think we merely passed it
by accident since our interpolation may give different results
depending on where on the screen a tri is regardless of linear
rasterizer).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11969>
Roland Scheidegger [Mon, 19 Jul 2021 02:01:50 +0000 (04:01 +0200)]
llvmpipe/linear: don't try to use tgsi analysis for nir shaders
Even though it's probably harmless, we shouldn't try it, so just skip it,
eventually need to hook in nir analysis there.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11969>
Dave Airlie [Fri, 14 May 2021 00:33:08 +0000 (10:33 +1000)]
llvmpipe: add some extra linear rast checks.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11969>
Dave Airlie [Fri, 14 May 2021 01:00:41 +0000 (11:00 +1000)]
llvmpipe/linear: fix ppc64/s390 build
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11969>
Jose Fonseca [Fri, 7 May 2021 12:49:07 +0000 (13:49 +0100)]
llvmpipe: Add a linear rasterizer optimized for 2D rendering.
This change adds:
- an alternative rasterizer, which rasterizes bins in a left->right &
top->bottom linear fashion;
- triangle -> rectangle detection;
- 1:1 blit detection;
- a special TGSI -> LLVM IR code generation that uses 8-bit SSE integers
in AoS fashion (as opposed to 32bits floats.)
Altogether these changes yield a 2x to 3x performance improvement for 2D
workloads. It was designed to render Windows 7 Aero and other Windows
built-in 3D applications (like Windows Media Player, Internet Explorer
11, UWP applications) with minimum CPU utilization, but it should be
generally applicable to other 2D-on-3D applications, like desktop
compositors, HTML browsers, 3D based UI toolkits, etc.
This was mostly the brainchild of Keith Whitwell back in 2010. I wrote
TGSI -> AoS translation. And many others added bug-fixes and
enhancements over the years: Roland Scheidegger, Brian Paul, and James
Benton.
Known issues:
- piglit spec@!opengl 1.1@quad-invariance will warn that "left and right
half should match" due to rounding error difference
- These optimized paths to kick in is that depth-buffer must not be
used, so some applications which want to benefit from these improvements
might need to be modified to ensure they use painter's algorithm instead
of depth-buffers.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Acked-by: Keith Whitwell <keithw@vmware.com>
v2: Incorporate Dave Airlie feedback: cleanup LP_DEBUG_xx; shrink 3+
empty lines.
v3: silence unused var warning, adapt to new upstream code (point setup)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11969>
Caio Marcelo de Oliveira Filho [Fri, 7 May 2021 18:41:13 +0000 (11:41 -0700)]
anv: Advertise support for VK_EXT_shader_atomic_float2
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11981>
Caio Marcelo de Oliveira Filho [Thu, 6 May 2021 21:56:54 +0000 (14:56 -0700)]
vulkan: Update XML and headers to 1.2.185
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11981>
Caio Marcelo de Oliveira Filho [Wed, 26 May 2021 06:12:40 +0000 (23:12 -0700)]
spirv: Implement SPV_EXT_shader_atomic_float16_add
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11981>
Jordan Justen [Wed, 3 Feb 2021 18:52:04 +0000 (10:52 -0800)]
intel/compiler: Remove cube array size lowering in compiler backend
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9466>
Jordan Justen [Wed, 3 Feb 2021 18:52:04 +0000 (10:52 -0800)]
intel/compiler: Lower cube image sizes using nir_lower_image()
Reworks:
* Re-merge early/late passes using Jason's nir image deref patches
* Create and use a common nir_lower_image() pass. (s-b Jason)
* Remove cube array size handling in image load/store lowering
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9466>
Jordan Justen [Wed, 3 Feb 2021 19:34:46 +0000 (11:34 -0800)]
intel/compiler: Rename brw_nir_lower_image_load_store to brw_nir_lower_storage_image
Reworks:
* Add crocus
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9466>
Jordan Justen [Thu, 15 Jul 2021 08:14:17 +0000 (01:14 -0700)]
nir: Add nir_lower_image() to lower cube image sizes
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9466>
Felix DeGrood [Thu, 8 Jul 2021 18:35:08 +0000 (11:35 -0700)]
iris: add tile cache flush to iris_copy_region
Add tile cache flush on iris_copy_region(). Temp workaround
until more robust tracking system implemented.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5029
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11935>
Jason Ekstrand [Tue, 20 Jul 2021 22:14:56 +0000 (17:14 -0500)]
nir/lower_subgroups: Handle down-casts in uint_to_ballot_type
This is required for Zink where the API ballot type is a uint64_t and
the "hardware" ballot type is uvec4.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11989>
Daniel Stone [Wed, 21 Jul 2021 16:25:23 +0000 (17:25 +0100)]
CI: Disable LAVA devices
We've had a physical machine death, and the restore/transfer is achingly
slow at the moment. Some of the devices are still fine, but
conservatively just kill the lot until it's all recovered.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11997>
Timothy Arceri [Thu, 21 Mar 2019 05:40:06 +0000 (16:40 +1100)]
intel/compiler: Use GCM in nir_optimize
There is still some work to do before we can enable GVN.
In these shader-db results, Skylake and older platforms used i965 while
newer platforms used Iris. I believe this accounts for the difference
in "sends." The shaders helped for sends are all Synmark shaders.
On Sandybridge, the shaders helped for sends were the same ones hurt for
spills and fills. These are also all Synmark shaders.
Tiger Lake and Ice Lake had similar results. (Ice Lake shown)
total instructions in shared programs:
19868594 ->
19868452 (<.01%)
instructions in affected programs: 6607 -> 6465 (-2.15%)
helped: 12
HURT: 1
helped stats (abs) min: 12 max: 12 x̄: 12.00 x̃: 12
helped stats (rel) min: 1.94% max: 2.62% x̄: 2.38% x̃: 2.58%
HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel) min: 0.45% max: 0.45% x̄: 0.45% x̃: 0.45%
95% mean confidence interval for instructions value: -13.27 -8.58
95% mean confidence interval for instructions %-change: -2.67% -1.65%
Instructions are helped.
total cycles in shared programs:
962404540 ->
962008224 (-0.04%)
cycles in affected programs: 961274 -> 564958 (-41.23%)
helped: 23
HURT: 1
helped stats (abs) min: 10 max: 32536 x̄: 17438.96 x̃: 23658
helped stats (rel) min: 0.02% max: 80.04% x̄: 42.05% x̃: 51.58%
HURT stats (abs) min: 4780 max: 4780 x̄: 4780.00 x̃: 4780
HURT stats (rel) min: 3.26% max: 3.26% x̄: 3.26% x̃: 3.26%
95% mean confidence interval for cycles value: -22989.90 -10036.43
95% mean confidence interval for cycles %-change: -55.01% -25.32%
Cycles are helped.
Skylake and Broadwell had simliar results. (Skylake shown)
total instructions in shared programs:
17996652 ->
17996154 (<.01%)
instructions in affected programs: 96622 -> 96124 (-0.52%)
helped: 85
HURT: 0
helped stats (abs) min: 1 max: 12 x̄: 5.86 x̃: 5
helped stats (rel) min: 0.39% max: 2.65% x̄: 0.68% x̃: 0.39%
95% mean confidence interval for instructions value: -6.42 -5.30
95% mean confidence interval for instructions %-change: -0.84% -0.52%
Instructions are helped.
total cycles in shared programs:
939899189 ->
939289732 (-0.06%)
cycles in affected programs: 3719430 -> 3109973 (-16.39%)
helped: 60
HURT: 39
helped stats (abs) min: 18 max: 32444 x̄: 10437.30 x̃: 6940
helped stats (rel) min: 0.08% max: 80.40% x̄: 23.99% x̃: 12.07%
HURT stats (abs) min: 10 max: 4970 x̄: 430.28 x̃: 323
HURT stats (rel) min: 0.05% max: 3.41% x̄: 1.55% x̃: 1.60%
95% mean confidence interval for cycles value: -8095.51 -4216.75
95% mean confidence interval for cycles %-change: -18.65% -9.21%
Cycles are helped.
total sends in shared programs: 1026997 -> 1026927 (<.01%)
sends in affected programs: 6090 -> 6020 (-1.15%)
helped: 70
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 1.15% max: 1.15% x̄: 1.15% x̃: 1.15%
95% mean confidence interval for sends value: -1.00 -1.00
95% mean confidence interval for sends %-change: -1.15% -1.15%
Sends are helped.
Haswell and Ivy Bridge had similar results. (Haswell shown)
total instructions in shared programs:
16040891 ->
16040252 (<.01%)
instructions in affected programs: 109132 -> 108493 (-0.59%)
helped: 87
HURT: 0
helped stats (abs) min: 1 max: 12 x̄: 7.34 x̃: 7
helped stats (rel) min: 0.05% max: 2.61% x̄: 0.75% x̃: 0.51%
95% mean confidence interval for instructions value: -7.84 -6.85
95% mean confidence interval for instructions %-change: -0.90% -0.61%
Instructions are helped.
total cycles in shared programs:
968579567 ->
967867117 (-0.07%)
cycles in affected programs:
30688439 ->
29975989 (-2.32%)
helped: 241
HURT: 62
helped stats (abs) min: 4 max: 31929 x̄: 3901.22 x̃: 2282
helped stats (rel) min: 0.04% max: 79.63% x̄: 12.70% x̃: 4.44%
HURT stats (abs) min: 4 max: 8230 x̄: 3673.27 x̃: 637
HURT stats (rel) min: 0.01% max: 63.87% x̄: 24.54% x̃: 3.56%
95% mean confidence interval for cycles value: -3100.23 -1602.41
95% mean confidence interval for cycles %-change: -7.94% -2.22%
Cycles are helped.
total sends in shared programs: 935025 -> 934955 (<.01%)
sends in affected programs: 6090 -> 6020 (-1.15%)
helped: 70
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 1.15% max: 1.15% x̄: 1.15% x̃: 1.15%
95% mean confidence interval for sends value: -1.00 -1.00
95% mean confidence interval for sends %-change: -1.15% -1.15%
Sends are helped.
LOST: 1
GAINED: 0
Sandy Bridge
total instructions in shared programs:
11785330 ->
11786504 (<.01%)
instructions in affected programs: 53462 -> 54636 (2.20%)
helped: 16
HURT: 36
helped stats (abs) min: 1 max: 17 x̄: 10.06 x̃: 9
helped stats (rel) min: 0.47% max: 3.29% x̄: 2.03% x̃: 1.90%
HURT stats (abs) min: 5 max: 38 x̄: 37.08 x̃: 38
HURT stats (rel) min: 1.77% max: 2.98% x̄: 2.94% x̃: 2.98%
95% mean confidence interval for instructions value: 16.26 28.90
95% mean confidence interval for instructions %-change: 0.75% 2.08%
Instructions are HURT.
total cycles in shared programs:
498009911 ->
497378300 (-0.13%)
cycles in affected programs: 6848277 -> 6216666 (-9.22%)
helped: 108
HURT: 28
helped stats (abs) min: 4 max: 25394 x̄: 6037.42 x̃: 766
helped stats (rel) min: 0.02% max: 60.58% x̄: 11.60% x̃: 4.83%
HURT stats (abs) min: 96 max: 6834 x̄: 729.64 x̃: 742
HURT stats (rel) min: 0.17% max: 16.23% x̄: 1.57% x̃: 1.55%
95% mean confidence interval for cycles value: -5907.99 -3380.40
95% mean confidence interval for cycles %-change: -11.67% -6.11%
Cycles are helped.
total spills in shared programs: 2316 -> 2526 (9.07%)
spills in affected programs: 280 -> 490 (75.00%)
helped: 0
HURT: 35
total fills in shared programs: 1540 -> 1750 (13.64%)
fills in affected programs: 280 -> 490 (75.00%)
helped: 0
HURT: 35
total sends in shared programs: 642985 -> 642950 (<.01%)
sends in affected programs: 3045 -> 3010 (-1.15%)
helped: 35
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 1.15% max: 1.15% x̄: 1.15% x̃: 1.15%
95% mean confidence interval for sends value: -1.00 -1.00
95% mean confidence interval for sends %-change: -1.15% -1.15%
Sends are helped.
LOST: 1
GAINED: 0
Iron Lake and GM45 had similar results. (Iron Lake shown)
total cycles in shared programs:
239442382 ->
239429400 (<.01%)
cycles in affected programs: 20816 -> 7834 (-62.37%)
helped: 2
HURT: 0
In Fossil-db, all of the shaders hurt for spill and fills are compute
shaders from Shadow of the Tomb Raider. Two shaders were helped for
sends, and these are also from SotTR.
All of the shaders helped for loops were from Geekbench5. These all
went from 3 loops to 2.
Tiger Lake
Instructions in all programs:
160852396 ->
160855303 (+0.0%)
SENDs in all programs: 6878559 -> 6878559 (+0.0%)
Loops in all programs: 38350 -> 38305 (-0.1%)
Cycles in all programs:
7369162339 ->
7344236445 (-0.3%)
Spills in all programs: 193762 -> 193876 (+0.1%)
Fills in all programs: 306417 -> 306600 (+0.1%)
Ice Lake
Instructions in all programs:
144592523 ->
144593946 (+0.0%)
SENDs in all programs: 6930697 -> 6930697 (+0.0%)
Loops in all programs: 38344 -> 38299 (-0.1%)
Cycles in all programs:
8732456458 ->
8707823383 (-0.3%)
Spills in all programs: 216692 -> 216806 (+0.1%)
Fills in all programs: 334089 -> 334272 (+0.1%)
Skylake
Instructions in all programs:
135618746 ->
135619971 (+0.0%)
SENDs in all programs: 6896728 -> 6896724 (-0.0%)
Loops in all programs: 38343 -> 38298 (-0.1%)
Cycles in all programs:
8391957144 ->
8368935657 (-0.3%)
Spills in all programs: 194741 -> 194879 (+0.1%)
Fills in all programs: 301048 -> 301255 (+0.1%)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/597>
Timothy Arceri [Mon, 25 Mar 2019 09:31:34 +0000 (20:31 +1100)]
intel/compiler: call nir_opt_dead_cf() after we have finished all opts
This will avoid a regression with the following patch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/597>
Timothy Arceri [Mon, 8 Apr 2019 01:30:53 +0000 (11:30 +1000)]
nir/gcm: be less destructive with instruction order
This changes the pass to extract pinned instructions and not just unpinned
instructions when rescheduling instructions. This stops pinned instructions
from being bunched together when instructions are reinserted into the blocks
which can result in regressions with regards to cycles and instruction
counts on i965 and register use/Max Waves on AMD hardware.
In order to do this we also throw away the post-order depth-first
search linearization algorithm used to re-insert the instructions, which
itself causes possible regressions when instructions are reinserted into
a less than ideal new order (of which the bunched together pinned
instructions is one example). Instead we simply insert instructions in the
reverse order they were extracted. This will simply place instructions
that were scheduled earlier onto the end of their new block and
instructions that were scheduled later to the start of their new block.
With this everything should remain in order without the need to run
over uses.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/597>
Ian Romanick [Tue, 20 Jul 2021 20:37:31 +0000 (13:37 -0700)]
nir/gcm: Clear out pass_flags before starting
With this pass enabled in Intel drivers, running shader-db on
shaders/unity/38.shader_test resulted in
Program received signal SIGSEGV, Segmentation fault.
gcm_schedule_early_src (src=0x555555d45348, void_state=0x7fffffffba40) at ../../SOURCE/master/src/compiler/nir/nir_opt_gcm.c:297
297 if (info->early_block->index < src_info->early_block->index)
(gdb) print src_info->early_block
$1 = (nir_block *) 0x0
I tracked this down to an early exit from gcm_schedule_early_instr on
the parent instruction because instr->pass_flags was 0x1c. That
should be an impossible value for this pass, so I inferred that
pass_flags must have dirt left from some previous pass.
Fixes:
8dfe6f672f4 ("nir/GCM: Use pass_flags instead of bitsets for tracking visited/pinned")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/597>
Mike Blumenkrantz [Tue, 20 Jul 2021 16:07:48 +0000 (12:07 -0400)]
nir: add nir_imm_ivec3 builder
the other ones exist, so why not this one too
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11983>
Daniel Schürmann [Mon, 19 Jul 2021 07:11:36 +0000 (09:11 +0200)]
aco: include <cstddef> in aco_util.h
It's needed for ptrdiff.
Fixes:
59fdaa1985f9269c40f0ca4704fbeb3fb05c4c2f ('aco: reorder and cleanup #includes')
Closes: #5076
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11947>
suijingfeng [Mon, 19 Jul 2021 13:24:35 +0000 (21:24 +0800)]
gallivm: fix pass init order on mips64 with llvm 8
llvm 8 has some missing pass dependencies, fix the mips64 case
as well.
See similiar fix:
[1] https://gitlab.freedesktop.org/mesa/mesa/-/commit/
f59ff014b199af118ac9b90e3a67f15f4c37110e
[2] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3805
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: suijingfeng <suijingfeng@loongson.cn>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11955>
suijingfeng [Mon, 19 Jul 2021 13:05:54 +0000 (21:05 +0800)]
pass egl-symbols-check test on mips64el
Without this patch the egl symbols check test fail on mips platform:
72/87 mesa:egl / egl-symbols-check FAIL 0.20s (exit status 1)
src/egl/libEGL.so.1.0.0: unknown symbol exported: _fbss
src/egl/libEGL.so.1.0.0: unknown symbol exported: _fdata
src/egl/libEGL.so.1.0.0: unknown symbol exported: _ftext
See Mips Run say thoes special symbols are automatically defined by the
linker to allow programs to discover the start and end of their various
section. They are descended from conventions that grew up in UNIX-like OSs,
and are peculiar to the MIPS environment.
_fbss : Start of uninitialized data segment
_fdata : Start of initialized data segment
_ftext : Start of text segment
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: suijingfeng <suijingfeng@loongson.cn>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11955>
suijingfeng [Mon, 19 Jul 2021 10:57:56 +0000 (18:57 +0800)]
gallivm: add basic mips64 support and set mcpu to mips64r5 on ls3a4000
ls3a4000 and ls2k1000 cpu is mips64r5 compatible with MSA SIMD
instruction set implemented, while ls3a3000 is mips64r2 compatible only.
Due to lacking llvm support for loongson CPU, llvm::sys::getHostCPUName().
return "generic" on all loongson mips CPU.
So we override the MCPU to mips64r5 if MSA is implemented, feedback to
mips64r2 for all other ordinaries.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: suijingfeng <suijingfeng@loongson.cn>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11955>
Daniel Stone [Tue, 20 Jul 2021 12:54:16 +0000 (13:54 +0100)]
egl/wayland: Allow EGLSurface to outlive wl_egl_window
According to the EGL spec, it is entirely valid for an EGLSurface to
outlive the native_window it was created from, provided that SwapBuffers
and MakeCurrent return EGL_BAD_NATIVE_WINDOW.
We don't have any facility to error on MakeCurrent, so just make sure we
can bundle on safely through rendering for now, then return
EGL_BAD_NATIVE_WINDOW from SwapBuffers.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2251
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4902
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11979>
Daniel Stone [Tue, 20 Jul 2021 12:40:00 +0000 (13:40 +0100)]
egl/wayland: Error on invalid native window
We unconditionally require a wl_egl_window to be passed as the native
window type, and do not permit a default window. The spec requires us to
return EGL_BAD_NATIVE_WINDOW when doing this, rather than crashing.
Further, if an EGLSurface has already been created for an existing
native window, we are required to return EGL_BAD_ALLOC.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2251
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4902
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11979>
Daniel Schürmann [Tue, 20 Jul 2021 09:12:26 +0000 (11:12 +0200)]
aco/ra: don't allocate vector space for MIMG NSA operands
In this case, the MIMG vaddr components are not vector-aligned anymore, anyway.
Totals from 11866 (7.90% of 150170) affected shaders: (GFX10.3)
VGPRs: 733064 -> 728408 (-0.64%); split: -0.66%, +0.02%
CodeSize:
67968356 ->
67968440 (+0.00%); split: -0.02%, +0.02%
MaxWaves: 214022 -> 214014 (-0.00%)
Instrs:
12798200 ->
12797232 (-0.01%); split: -0.02%, +0.01%
Latency:
196427665 ->
196418706 (-0.00%); split: -0.02%, +0.01%
InvThroughput:
37082037 ->
37080799 (-0.00%); split: -0.02%, +0.02%
VClause: 246097 -> 246031 (-0.03%); split: -0.16%, +0.13%
Copies: 494852 -> 493923 (-0.19%); split: -0.52%, +0.34%
Branches: 220323 -> 220294 (-0.01%); split: -0.03%, +0.02%
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11980>
Marcin Ślusarz [Tue, 20 Jul 2021 10:00:41 +0000 (12:00 +0200)]
anv: share some code between vkCmdDrawIndirectCount and vkCmdDrawIndexedIndirectCount
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11975>
Juan A. Suarez Romero [Mon, 19 Jul 2021 16:17:36 +0000 (18:17 +0200)]
ci/v3dv: update expected results
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11970>
Marcin Ślusarz [Mon, 19 Jul 2021 16:29:21 +0000 (18:29 +0200)]
intel/tools/aubinator_error_decode: tag hanging instruction
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11957>
Corentin Noël [Wed, 21 Jul 2021 06:50:01 +0000 (08:50 +0200)]
ci: actually run piglit tests with virgl
Make sure that the host is using llvmpipe while the guest is using virgl as driver.
Note that the neverball/neverball.trace trace actually regressed in a way that the
foreground is missing.
Fixes:
f1b952fa ("ci: Run tests inside Crosvm")
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11986>
Iago Toral Quiroga [Tue, 20 Jul 2021 12:20:32 +0000 (14:20 +0200)]
v3dv: fix I/O lowering for GS
Fixes
9e7d9a6ef ('v3dv: add support for geometry shaders to pipelines')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11977>
Dave Airlie [Wed, 21 Jul 2021 04:55:41 +0000 (14:55 +1000)]
crocus/gen4-5: fix ff gs emit on VS vue map change.
This should fix some texturing problems seen on gen4/5, I reproduced it
with a minecraft.trace file
Fixes:
f3630548f1da ("crocus: initial gallium driver for Intel gfx 4-7")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11993>
Dave Airlie [Sun, 18 Jul 2021 19:54:57 +0000 (05:54 +1000)]
docs: update anisotropic info for softpipe/llvmpipe/lavapipe
both drivers have proper implementations
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8804>
Dave Airlie [Sun, 18 Jul 2021 19:47:46 +0000 (05:47 +1000)]
llvmpipe/virgl/ci: update traces for aniso
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8804>
Mike Blumenkrantz [Thu, 27 May 2021 21:35:22 +0000 (17:35 -0400)]
lavapipe: add support for anisotropic texturing
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8804>
Dave Airlie [Mon, 8 Feb 2021 02:37:40 +0000 (12:37 +1000)]
llvmpipe: enable GL_ARB_texture_filter_anisotropic
Update checksums as images are same as softpipe.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8804>
Dave Airlie [Mon, 8 Feb 2021 02:33:51 +0000 (12:33 +1000)]
draw: add sampler max_aniso query.
Add support for draw shaders for retrieve max anisotropy.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8804>