Daniel Schürmann [Thu, 16 Mar 2023 21:24:49 +0000 (22:24 +0100)]
radv: remove unnecessary copy of binary->config
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22029>
Daniel Schürmann [Thu, 16 Mar 2023 21:18:26 +0000 (22:18 +0100)]
radv: separate radv_postprocess_binary_config() from radv_shader_create()
The goal is to make radv_shader_create() a function that creates a shader
from a binary without any additional information.
Postprocessing the config is only needed after compilation.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22029>
Daniel Schürmann [Thu, 16 Mar 2023 21:03:49 +0000 (22:03 +0100)]
radv: remove unused parameter from radv_open_rtld_binary()
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22029>
Patrick Lerda [Mon, 20 Mar 2023 22:34:36 +0000 (23:34 +0100)]
r600: fix refcnt imbalance related to shader
Indeed, gs_copy_shader was not freed.
Fixes: commit
1371d65a7fbd695d3516861fe733685569d890d0
r600g: initial support for geometry shaders on evergreen (v2)
For instance, with "piglit/bin/shader_runner generated_tests/spec/arb_gpu_shader_int64/execution/built-in-functions/gs-abs-i64vec2.shader_test -auto -fbo"
while setting GALLIUM_REFCNT_LOG=refcnt.log.
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22087>
José Roberto de Souza [Mon, 20 Mar 2023 17:41:34 +0000 (10:41 -0700)]
iris: Ajust gem buffer allocation size in Xe kmd
gem buffer size must also be aligned to mem_alignment otherwise
vm binds can fail when Xe kmd checks if vm bind range is bigger than
gem buffer size.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22059>
José Roberto de Souza [Tue, 14 Feb 2023 17:21:25 +0000 (09:21 -0800)]
iris: Implement gem_vm_bind() and gem_vm_unbind() in Xe kmd backend
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22059>
José Roberto de Souza [Tue, 1 Nov 2022 18:07:16 +0000 (11:07 -0700)]
iris: Add vm bind and unbind to kmd backend
At this time this is a nop for i915 but in future we will have a
Xe implementation.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22059>
José Roberto de Souza [Mon, 16 Jan 2023 20:48:40 +0000 (12:48 -0800)]
iris: Prepare iris_bufmgr functions for vm bind error paths
vm bind and unbind can fail, so error paths will be needed.
Here I'm just preparing the code paths for that.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22059>
Samuel Pitoiset [Fri, 24 Mar 2023 08:36:01 +0000 (09:36 +0100)]
radv: rework binding shaders to cmdbuf by introducing new helpers
For future work.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22101>
Danylo Piliaiev [Thu, 9 Mar 2023 18:57:51 +0000 (19:57 +0100)]
tu: Generate entrypoints for each gen
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Thu, 9 Mar 2023 20:50:21 +0000 (21:50 +0100)]
freedreno/regs: Include assert.h in generated headers
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Thu, 9 Mar 2023 18:56:43 +0000 (19:56 +0100)]
vk/entry_points: Add option to generate template entrypoints
As a C++ alternative to genX macros.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Wed, 8 Mar 2023 18:12:08 +0000 (19:12 +0100)]
tu: compile as C++
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Wed, 8 Mar 2023 12:45:41 +0000 (13:45 +0100)]
freedreno/msm: Rename drm_msm_gem_submit_reloc::or in C++ code
Clashes with C++ `or` keyword
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Mon, 13 Mar 2023 13:19:43 +0000 (14:19 +0100)]
tu: C++-proofing: misc fixes
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Wed, 15 Mar 2023 10:33:32 +0000 (11:33 +0100)]
tu: C++-proofing: cast result when extracting field from reg value
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Tue, 14 Mar 2023 19:01:11 +0000 (20:01 +0100)]
tu: C++-proofing: prevent taking address from rvalue
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Tue, 14 Mar 2023 18:16:59 +0000 (19:16 +0100)]
tu: C++-proofing: ease access to global bo struct
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Tue, 14 Mar 2023 18:03:03 +0000 (19:03 +0100)]
tu: C++-proofing: fix casting from void * fpermissive warnings
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Tue, 7 Mar 2023 15:22:22 +0000 (16:22 +0100)]
tu: C++-proofing: Initialize tu_reg_value in-order by pack funcs
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Wed, 8 Mar 2023 12:55:00 +0000 (13:55 +0100)]
tu: C++-proofing: fix extension table initialization
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Tue, 7 Mar 2023 16:03:50 +0000 (17:03 +0100)]
tu: C++-proofing: fix designator initializer order
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Tue, 7 Mar 2023 17:03:37 +0000 (18:03 +0100)]
tu: C++-proof: do not goto over variables initialization
That is not permitted by C++
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Mon, 13 Mar 2023 13:16:16 +0000 (14:16 +0100)]
tu: C++-proofing: various enum fixes
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Mon, 13 Mar 2023 13:13:47 +0000 (14:13 +0100)]
tu: C++-proofing: fix struct initializers
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Mon, 13 Mar 2023 13:09:20 +0000 (14:09 +0100)]
tu: C++-proofing: fix offsetof with dynamic array index
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Mon, 13 Mar 2023 13:52:44 +0000 (14:52 +0100)]
ir3: C++-proofing
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Mon, 13 Mar 2023 13:56:50 +0000 (14:56 +0100)]
freedreno/common: C++-proof freedreno_uuid.h
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Tue, 14 Mar 2023 13:44:17 +0000 (14:44 +0100)]
vk/util: Generate defines to help casting structs with vk_find_struct
C++ doesn't like implicit casts from void *.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Tue, 14 Mar 2023 18:20:01 +0000 (19:20 +0100)]
vk/util: remove (void *) casts from vk_foreach_multi_draw macros
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Wed, 8 Mar 2023 13:29:11 +0000 (14:29 +0100)]
vk/wsi: C++-proof wsi_common_drm.h
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Wed, 8 Mar 2023 12:52:36 +0000 (13:52 +0100)]
vk/vk_extension_gen: Make table struct initializable in C++ on older gcc
Before GCC 11.2 initializing anonymous struct with extensions gave:
error: too many initializers for 'vk_device_extension_table'
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Tue, 7 Mar 2023 16:27:51 +0000 (17:27 +0100)]
spirv: sort spirv_supported_capabilities
Makes easier for c++ driver to keep initializer in order.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Wed, 8 Mar 2023 12:35:22 +0000 (13:35 +0100)]
util/format: Make format_table compatible with C++
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Danylo Piliaiev [Wed, 8 Mar 2023 13:49:08 +0000 (14:49 +0100)]
util/perf: C++-proof util/perf
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21931>
Konstantin Seurer [Tue, 20 Dec 2022 17:26:34 +0000 (18:26 +0100)]
nir/lower_shader_calls: Remat derefs before lowering resumes
Closes: #7923
cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20399>
Samuel Pitoiset [Thu, 23 Mar 2023 15:45:18 +0000 (16:45 +0100)]
radv: remove radv_pipeline::device completely
This is unecessary and this prevents using a ton of functions without
a radv_pipeline object.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22090>
antonino [Mon, 6 Feb 2023 14:44:01 +0000 (15:44 +0100)]
gallium: decompose quad strips into quads if supported
This changes gallium to decompose quad strips into quads instead of triangles
when the driver advertises support for them.
This should result in a more correct result when those are drawn
with the line raster primitve (avoids showing the diagonal line).
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21987>
antonino [Tue, 21 Mar 2023 14:35:59 +0000 (15:35 +0100)]
mesa: correctly allocate space for converted primtives
Previosuly it was assumed that primitives where always converted to
triangles if the driver did not support all primitives, however that's
not true for a driver that supports quads but not quad strips.
Fixes piglit spec@!opengl 1.1@dlist-fdo3129-01 on Panfrost
Fixes:
dcbf2423d28 ("vbo/dlist: add vertices to incomplete primitives")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21987>
Samuel Pitoiset [Tue, 21 Mar 2023 10:21:48 +0000 (11:21 +0100)]
radv: pass a radv_shader to radv_emit_dispatch_packets()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22102>
Samuel Pitoiset [Tue, 21 Mar 2023 10:13:41 +0000 (11:13 +0100)]
radv: move cs_regalloc_hang_bug to radv_shader_info
This is more like a shader property.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22102>
Georg Lehmann [Wed, 22 Mar 2023 19:07:52 +0000 (20:07 +0100)]
amd: remove duplicate from .clang-format
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22077>
Georg Lehmann [Wed, 22 Mar 2023 17:55:31 +0000 (18:55 +0100)]
aco: remove duplicates from .clang-format
The latest clang-format doesn't support this anymore.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22077>
Lionel Landwerlin [Sun, 12 Mar 2023 20:04:22 +0000 (22:04 +0200)]
anv: add utrace support for queue debug utils
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22006>
Lionel Landwerlin [Sat, 18 Mar 2023 21:51:04 +0000 (23:51 +0200)]
anv: rename anv_utrace_flush_copy in anv_utrace_submit
We want to use this for submission of traces outside command buffers,
so it won't just execute copies of timestamp buffers.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22006>
Lionel Landwerlin [Sat, 18 Mar 2023 21:47:01 +0000 (23:47 +0200)]
anv: fixup locking for utrace submission increments
This is supposed to happen under the device lock.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
e760c5b37b ("anv: add perfetto source")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22006>
Lionel Landwerlin [Sat, 18 Mar 2023 21:30:39 +0000 (23:30 +0200)]
anv: fix incorrect utrace bo release
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
c67c9688c3 ("anv/utrace: use a bo pool for utrace buffers")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22006>
Lionel Landwerlin [Sat, 18 Mar 2023 21:06:47 +0000 (23:06 +0200)]
intel/ds: rename frame timeline row to queue
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22006>
Lionel Landwerlin [Sat, 18 Mar 2023 21:21:16 +0000 (23:21 +0200)]
vulkan/runtime: also copy strings on queue debug utils
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22006>
Lionel Landwerlin [Sat, 18 Mar 2023 21:03:56 +0000 (23:03 +0200)]
util/u_trace: move needs_cs_param option to tracepoints
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22006>
Teng, Jin Chung [Thu, 23 Mar 2023 02:17:45 +0000 (10:17 +0800)]
d3d12: AV1 Dec - Set anchor_frame_idx only when large_scale_tile equals 1
Signed-off-by: Teng, Jin Chung <jin.chung.teng@intel.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22048>
Teng, Jin Chung [Thu, 23 Mar 2023 02:17:13 +0000 (10:17 +0800)]
frontend/va: Add large_scale_tile from VADecPictureParameterBufferAV1
Signed-off-by: Teng, Jin Chung <jin.chung.teng@intel.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22048>
Mike Blumenkrantz [Thu, 23 Mar 2023 12:06:05 +0000 (08:06 -0400)]
zink: flag rp layout change if zsbuf usedness changes on dsa/fs state bind
this should (correctly) trigger the expected zsbuf elimination and
avoid hitting asserts
fixes #8679
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22086>
Alyssa Rosenzweig [Tue, 21 Mar 2023 16:30:00 +0000 (12:30 -0400)]
panfrost: Remove Midgard RSD fields from Bifrost
These were removed and replaced by new Bifrost RSD fields, don't print the wrong
values. Harmless but noises up the decoding.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 20 Feb 2023 03:47:31 +0000 (22:47 -0500)]
panvk: Lower blending late
Since
50b82ca8181 ("nir/lower_blend,agx,panfrost: Use lowered I/O"),
nir_lower_blend needs to be called after lowering I/O rather than before.
Furthermore, after lowering blend, we need (in general) to lower the resulting
load_output intrinsics. Now that we have a proper preprocess_nir hook, there is
a natural place in panvk_vX_shader to do this.
Fixes dEQP-VK.pipeline.blend.*
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 20 Feb 2023 04:44:17 +0000 (23:44 -0500)]
pan/bi: Call pan_nir_lower_zs_store late
This will give the driver [notably, PanVK] a chance to lower dual source
blending without having the dual stores turned into store_combined_output_pan.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 20 Feb 2023 03:47:24 +0000 (22:47 -0500)]
pan/bi: Export bifrost_nir_lower_load_output
If new load_output are created after preprocessing NIR (namely, from blend
lowering in panvk), this lowering needs to be called to lower load_output to the
vendor intrinsic with conversion descriptor.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Sat, 11 Feb 2023 02:45:05 +0000 (21:45 -0500)]
panfrost: Move panfrost_sysvals to GL driver
This shouldn't be used by anything else at this point.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Sat, 11 Feb 2023 02:43:48 +0000 (21:43 -0500)]
panvk: Remove unused function
Erroneously referencing sysvals.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Sat, 11 Feb 2023 02:40:50 +0000 (21:40 -0500)]
panfrost: Move sysvals to GL driver struct
Only the GL driver produces/consumes these, they shouldn't be in the common
shader_info.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Sat, 11 Feb 2023 02:22:49 +0000 (21:22 -0500)]
panfrost: Lower sysvals in GL
Drop the backend compiler sysval handling in favour of the pass in the GL
driver, bringing us into compliance with Ekstrand's rule.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Sat, 11 Feb 2023 02:21:12 +0000 (21:21 -0500)]
panfrost: Add NIR-based sysval lowering pass
Add a NIR pass to lower all the sysvals seen in the GL driver to load_ubo
intrinsics. These load_ubo intrinsics will be pushed to uniforms by the backend
compiler as usual. This will let us remove all sysval handling from the backend
compilers.
This is a direct NIR port of the existing pan_sysvals.c infrastructure and the
consumers in the Midgard/Bifrost compilers. It aims to be bug-for-bug compatible
to ease bisection.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Tue, 7 Feb 2023 17:01:33 +0000 (12:01 -0500)]
panvk: Inline blend constants as syvals
Blend constants are sysvals, it's just that they can sometimes be inlined
depending on the pipeline state. The old "inline blend constant" pass is a
special case of the new "lower all sysvals" pass in panvk.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Tue, 7 Feb 2023 17:01:20 +0000 (12:01 -0500)]
panvk: Don't use vec4 for vertex_instance_offsets
Not needed with the new lowering.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Tue, 7 Feb 2023 16:49:22 +0000 (11:49 -0500)]
panvk: Lower sysvals in NIR
Per Ekstrand's Rule. This avoids the "fixed sysval" hack that Faith introduced
to get this behaviour with the GL sysval handling.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Tue, 7 Feb 2023 15:31:54 +0000 (10:31 -0500)]
panfrost: Remove stale TODO
While the text here is still nominally accurate, we should be seeing so few
shader variants at this point that the locking contention isn't a big deal.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Tue, 7 Feb 2023 05:15:23 +0000 (00:15 -0500)]
panfrost: Preprocess shaders at CSO create time
Now the only passes that depend on the shader key can run late, so we can
preprocess ahead-of-time once and throw away the original shader. This reduces
the cost of shader variants, as well as deduplicates some lowering for
transform feedback shaders.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Tue, 7 Feb 2023 05:02:51 +0000 (00:02 -0500)]
panfrost: Effectively lower gl_FragColor late
nir_lower_fragcolor takes the number of colour buffers as input, but it's an
early pass, so we don't want to use the key for it. Instead, we can overestimate
and then optimize out late with an easy pass.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Tue, 7 Feb 2023 04:54:42 +0000 (23:54 -0500)]
panfrost: Lower texcoords late
Use the _late version of this lowering instead of the early one.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Tue, 7 Feb 2023 04:53:35 +0000 (23:53 -0500)]
panfrost: Lower clip_fs late
This pass works both early and late, so this is an easy one to sink down.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Tue, 7 Feb 2023 04:38:12 +0000 (23:38 -0500)]
pan/lower_framebuffer: Lower MSAA blend shaders
Do it explicitly in NIR rather than implicitly in the Midgard compiler. This
avoids a nasty sideband input for the render target formats and sample count,
for blend shaders on midgard only.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 22:23:19 +0000 (17:23 -0500)]
panfrost: Preprocess shaders in the driver
This is a flag-day change to how we compile. We split preprocessing NIR into a
separate step from compiling, giving the driver a chance to apply its own
lowerings on the preprocessed NIR before the final optimization loop. During
that time, the different producers of NIR (panfrost, panvk, blend shaders, blit
shaders...) will be able to (differently) lower system values.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Tue, 7 Feb 2023 04:23:59 +0000 (23:23 -0500)]
pan/blit: Lower load_sampler_lod_parameters_pan
This will be needed to decouple the lowering in the Midgard compiler from the
specific sampler descriptors used in the blit code.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 16:37:13 +0000 (11:37 -0500)]
pan/lower_framebuffer: Use nir_shader_instructions_pass
Removes a lot of indentation, and improves metadata handling.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 16:34:02 +0000 (11:34 -0500)]
pan/lower_framebuffer: Only call for FS
It doesn't make sense for shader stages other than fragment (and blend which is
fragment-like), assert this.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 16:11:10 +0000 (11:11 -0500)]
pan/mdg: Split out early preprocessing from late
To prepare for the new compile flow, where this will be called by the driver
instead of internally in the compiler.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 16:16:08 +0000 (11:16 -0500)]
pan/bi: Split out early preprocessing from late
To prepare for the new compile flow, where this will be called by the driver
instead of internally in the compiler.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 15:58:33 +0000 (10:58 -0500)]
pan/mdg: Only lower once
Nothing in the optimization loop should remat the lowered instructions, so
there's no need to do it inside the loop.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 15:57:15 +0000 (10:57 -0500)]
pan/bi: Only lower once
Nothing in the optimization loop should remat the lowered instructions, so
there's no need to do it inside the loop.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 15:50:00 +0000 (10:50 -0500)]
panfrost: Remove unused inputs.nr_cbufs
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 15:49:58 +0000 (10:49 -0500)]
panfrost: Remove inputs->blend.rt
This sideband input is now unused, as the information is available locally
within the NIR as it should be.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 15:49:57 +0000 (10:49 -0500)]
pan/mdg: Use I/O semantics for MRT blend stores
This avoids the silly reliance on the sideband.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 15:49:56 +0000 (10:49 -0500)]
pan/bi: Remove bi_load_sysval
It is unused and should stay unused, as any use is a violation of Ekstrand's
rule.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 15:49:54 +0000 (10:49 -0500)]
pan/bi: Lower gl_VertexID in NIR
This gets rid of the hidden gl_BaseVertex system value which violates Ekstrand's
rule.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 15:49:52 +0000 (10:49 -0500)]
pan/bi: Allow specializing bifrost_nir_options by arch
We need different settings for Bifrost and Valhall. Keeping everything static
simplifies lifetimes.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 15:49:50 +0000 (10:49 -0500)]
pan/bi: Lower load_output to make sysval explicit
See previous commits for justification. Later, we'll split up NIR processing in
a few steps to give the caller a chance to lower the sysval, at which point the
goofy inputs here will go away.
v2: Only lower in fragment shaders. Likely harmless to run elsewhere but still
wrong because the location enum is defined per-stage.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 15:49:47 +0000 (10:49 -0500)]
pan/bi: Lower sample mask writes in NIR
This uses the new NIR sysvals to avoid materializing magic sysvals in the
driver, getting us closer to the Ekstrand Rule.
v2: Only lower for fragment shaders. Lowering in vertex shaders should be a
no-op, except that FRAG_RESULT_SAMPLE_MASK shadows a VARYING_SLOT for fog
coords, causing v1 of this patch to regress fog. Caught by the G52 piglit job in
CI. Thank you, Marge.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 15:49:44 +0000 (10:49 -0500)]
pan/bi: Don't duplicate texture op cases
These two switches are redundant.
Furthermore, bi_tex_op could previously assume its input was a supported texop,
so it returned undefined values for unsupported texops. Now, without the guard
in front of it, bi_tex_op should check for supported texops, so we need to drop
the unsupported texops from the switch.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 15:49:38 +0000 (10:49 -0500)]
panfrost: Use 0/~0 boolean for MSAA sysval
For consistency with NIR.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 15:49:32 +0000 (10:49 -0500)]
nir: Add Mali load_output taking converison
Mali's LD_TILE instruction (mapping to NIR's load_output) requires a "conversion
descriptor" specifying how to convert from the register foramt to the tilebuffer
format. To implement framebuffer fetch on OpenGL without shader variants, we
generate these descriptors in the driver and pass them in a uniform. However, to
comply with the Ekstrand Rule, we can't have magically materialized system
values -- they should come only from the NIR where the driver can lower as it
pleases (e.g. PanVK can lower to a constant because it knows the framebuffer
format at pipeline create time). Add intrinsics to model this.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Alyssa Rosenzweig [Mon, 6 Feb 2023 15:49:29 +0000 (10:49 -0500)]
nir: Add Panfrost intrinsics to lower sample mask
We want to lower this in NIR instead of the backend IR to give the driver a
chance to lower the "is multisampled?" system value, which makes more sense to
do in NIR. This gets rid of one of the magic compiler materialized sysvals.
Plus, this will let us constant fold away the lowering in Vulkan when we know
that the pipeline is single-sampled / multi-sampled.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>
Mark Janes [Wed, 15 Mar 2023 20:45:22 +0000 (13:45 -0700)]
intel/dev: use GFX_VERx10 to detect genX compilation
Depending on the ordering of includes, GFX_VER may not defined for
intel_device_info.h. The failure mode of this case is silent:
BITSET_TEST will be called when it could be compiled out.
GFX_VERx10 should be used in place of GFX_VER. GFX_VERx10 is defined
by a compiler flag, and is always present for genX compilation units.
Fixes:
3c9a8f7a6d2 ("intel/dev: generate helpers to identify platform workarounds")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21908>
Mark Janes [Wed, 15 Mar 2023 20:53:29 +0000 (13:53 -0700)]
intel/dev: fix macro naming convention in gen_wa_helpers.py
intel_device_info.h tests macros in the form `INTEL_WA_{id}_GFX_VER`.
gen_wa_helpers.py produced macros in the form `INTEL_GFX_VER_WA_{id}`
Change the generated code to follow intel_device_info.h
Fixes:
3c9a8f7a6d2 ("intel/dev: generate helpers to identify platform workarounds")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21908>
Mark Janes [Tue, 14 Mar 2023 17:19:17 +0000 (10:19 -0700)]
intel/dev: fix macro string concatenation for INTEL_WA_{id}_GFX_VER
`INTEL_WA_##id_GFX_VER` evaluates to `INTEL_WA_id_GFX_VER`
instead of numbered identifiers like `INTEL_WA_220579888_GFX_VER`.
Fixes:
3c9a8f7a6d2 ("intel/dev: generate helpers to identify platform workarounds")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21908>
Jesse Natalie [Thu, 23 Mar 2023 15:41:00 +0000 (08:41 -0700)]
dzn: Use mesa_loge for DXIL validation errors
This allows them to be printed to OutputDebugString
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>
Jesse Natalie [Fri, 17 Mar 2023 15:18:45 +0000 (08:18 -0700)]
dzn: Enable variable size bindings
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>
Jesse Natalie [Mon, 13 Mar 2023 21:36:20 +0000 (14:36 -0700)]
dzn: Support descriptor indexing via bindless
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>
Jesse Natalie [Mon, 13 Mar 2023 19:45:15 +0000 (12:45 -0700)]
dzn: Add a debug option for enabling bindless mode
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>
Jesse Natalie [Mon, 13 Mar 2023 19:44:43 +0000 (12:44 -0700)]
dzn: Apply bindless lowering when compiling pipelines
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>
Jesse Natalie [Thu, 23 Mar 2023 15:33:18 +0000 (08:33 -0700)]
dzn: Only bind descriptor sets up to the used amount of the current layout
Prevents setting a root SRV into a slot that's not declared as an SRV
in the root signature if a set is bound into a higher slot from a previous
draw/dispatch op.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>
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