Alyssa Rosenzweig [Sat, 20 May 2023 17:44:37 +0000 (13:44 -0400)]
agx: Translate texture bindless handles
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Sat, 20 May 2023 17:46:50 +0000 (13:46 -0400)]
agx: Pack bindless textures
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Thu, 25 May 2023 18:22:40 +0000 (14:22 -0400)]
agx: Handle bindless properly for txs lowering
When I wrote this pass I mostly guessed what our bindless handles would look
like. Now that we know we can do it right.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Sat, 20 May 2023 17:36:10 +0000 (13:36 -0400)]
agx: Model texture bindless base
Extra source we need to implement bindless.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Fri, 19 May 2023 17:07:52 +0000 (13:07 -0400)]
agx: Add image write instruction
Model and pack what's in the hardware for this.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Fri, 19 May 2023 17:06:41 +0000 (13:06 -0400)]
agx: Generalize texture/PBE packing
For the generic image write instruction we'll want the full forms of these
fields.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Thu, 25 May 2023 20:51:20 +0000 (16:51 -0400)]
agx: Lower image size to txs
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Thu, 25 May 2023 19:01:22 +0000 (15:01 -0400)]
agx: Legalize image LODs to be 16-bit
Required by the hardware. Do it in NIR so we can optimize the conversion.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Tue, 27 Jun 2023 22:33:57 +0000 (18:33 -0400)]
asahi: Use nir_lower_robust_access
This makes images robust as required by the OpenGL ES spec.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Wed, 28 Jun 2023 19:43:22 +0000 (15:43 -0400)]
asahi: Extend PBE packing for image support
We need to support arrayed images and sRGB images, which are hardware. For
atomics, we need to pack the augmented software data structure. Finally, we need
to support buffer images. Like their texture counterparts, these get lowered to
2D images.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Wed, 28 Jun 2023 19:39:57 +0000 (15:39 -0400)]
asahi: Augment PBE descriptor for software access
For implementing image atomics (and multisample image writes), we need
information about the image layout in the shader. It's a lot nicer to determine
the image layouts on the CPU (where we have ail) and stash the results in the
PBE descriptor, where we have a convenient hole to do so, rather than trying to
do all the layout calculations on the GPU on the fly. Add a data structure that
the driver will fill out and the image atomic lowering will consider as part of
the hardware.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Asahi Lina [Mon, 10 Jul 2023 15:45:17 +0000 (00:45 +0900)]
asahi: Add a shared library interface for decode
Add a simple API so that decode can be used as a shared library by the
Python hypervisor. Note that this is not thread-safe. If we ever want to
use this in other contexts with thread safety, it will need a refactor
(along with the core decode code anyway).
Signed-off-by: Asahi Lina <lina@asahilina.net>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Asahi Lina [Mon, 10 Jul 2023 15:43:57 +0000 (00:43 +0900)]
asahi: decode: Add a function to construct decode_params from a chip_id
Should be useful on macOS later to properly support detecting the right
GPU, but for now just hardcode T8103/G13G.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Asahi Lina [Mon, 10 Jul 2023 15:42:52 +0000 (00:42 +0900)]
asahi: decode: Refactor to always copy GPU mem to local buffers
We want to plug this library into the hypervisor, but there we don't
have all GPU memory already mapped in our address space. Refactor the
GPU mem read function to always allocate local buffers and copy in the
data there.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Asahi Lina [Mon, 10 Jul 2023 17:23:33 +0000 (02:23 +0900)]
asahi: wrap: Handle freeing shmems
Needed for some Metal demos that end up creating multiple queues.
This is still definitely broken/not fully correct, but it at least
gets things working for those.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Asahi Lina [Fri, 7 Jul 2023 10:45:28 +0000 (19:45 +0900)]
asahi: Add extra CDM header block for G14X
Looks like we finally found our first properly divergent codepath.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Asahi Lina [Fri, 7 Jul 2023 10:41:48 +0000 (19:41 +0900)]
asahi: decode: Add a params argument to pass through
Sooner or later we were going to need divergent codepaths in decode, and
it looks like now is the time. Add a `params` typedef and pass it
through all the decoder callbacks. This is an alias for
drm_asahi_params_global, but use a typedef so we can change that later
without changing dozens of instances.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Sun, 2 Jul 2023 17:30:44 +0000 (13:30 -0400)]
agx: Fix bogus assert
Dolphin uses all the uniforms.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Sat, 1 Jul 2023 18:43:53 +0000 (14:43 -0400)]
agx: Reduce un/packs with mem access lowering
Often not needed and makes the NIR harder to read.
shader-db is noise.
total instructions in shared programs: 1752712 -> 1752688 (<.01%)
instructions in affected programs: 8338 -> 8314 (-0.29%)
helped: 21
HURT: 8
Inconclusive result (%-change mean confidence interval includes 0).
total bytes in shared programs:
11943572 ->
11943434 (<.01%)
bytes in affected programs: 56716 -> 56578 (-0.24%)
helped: 21
HURT: 8
Inconclusive result (%-change mean confidence interval includes 0).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Sun, 2 Jul 2023 13:57:26 +0000 (09:57 -0400)]
agx: Vectorize 16-bit parallel copies
If we have two 16-bit copies to/from adjacent 16-bit registers, we can instead
use a single 32-bit copy from the 32-bit register pair. Since 32-bit integer
arithmetic is (almost) as efficient as 16-bit on AGX, this (almost) doubles
performance of affected parallel copies.
total instructions in shared programs: 1788606 -> 1788301 (-0.02%)
instructions in affected programs: 17057 -> 16752 (-1.79%)
helped: 150
HURT: 0
Instructions are helped.
total bytes in shared programs:
12196492 ->
12194662 (-0.02%)
bytes in affected programs: 122894 -> 121064 (-1.49%)
helped: 150
HURT: 0
Bytes are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Sun, 2 Jul 2023 13:46:12 +0000 (09:46 -0400)]
agx: Try to allocate phi sources with loop phis
total instructions in shared programs: 1788666 -> 1788606 (<.01%)
instructions in affected programs: 7953 -> 7893 (-0.75%)
helped: 29
HURT: 0
Instructions are helped.
total bytes in shared programs:
12196852 ->
12196492 (<.01%)
bytes in affected programs: 53908 -> 53548 (-0.67%)
helped: 29
HURT: 0
Bytes are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Sat, 1 Jul 2023 17:11:46 +0000 (13:11 -0400)]
agx: Try to allocate phi sources with phis
Not meaningfully using more registers since this is just about how we assign
registers after fixing the maximum # of registers used (note that thread count
is unaffected).
total instructions in shared programs: 1790901 -> 1788666 (-0.12%)
instructions in affected programs: 230680 -> 228445 (-0.97%)
helped: 681
HURT: 2
Instructions are helped.
total bytes in shared programs:
12210266 ->
12196852 (-0.11%)
bytes in affected programs: 1634100 -> 1620686 (-0.82%)
helped: 682
HURT: 2
Bytes are helped.
total halfregs in shared programs: 532130 -> 532218 (0.02%)
halfregs in affected programs: 848 -> 936 (10.38%)
helped: 3
HURT: 13
Halfregs are HURT.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Sat, 1 Jul 2023 16:56:02 +0000 (12:56 -0400)]
agx: Try to allocate phis compatibly with sources
All shaders affected for thread count are in pubg... by chance the allocation
before used fewer registers than the calculated register demand (I guess because
we're conservative with our vector handling) and so got lucky and got higher
thread count. That shader is also helped massively for instructions.
The halfreg change doesn't matter -- we're not actually increasing register
demand, we're just being more choosy about our registers.
total instructions in shared programs: 1799738 -> 1790901 (-0.49%)
instructions in affected programs: 306081 -> 297244 (-2.89%)
helped: 889
HURT: 14
Instructions are helped.
total bytes in shared programs:
12263290 ->
12210266 (-0.43%)
bytes in affected programs: 2150966 -> 2097942 (-2.47%)
helped: 889
HURT: 14
Bytes are helped.
total halfregs in shared programs: 531981 -> 532130 (0.03%)
halfregs in affected programs: 1925 -> 2074 (7.74%)
helped: 0
HURT: 26
Halfregs are HURT.
total threads in shared programs:
18885184 ->
18884224 (<.01%)
threads in affected programs: 13440 -> 12480 (-7.14%)
helped: 0
HURT: 15
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Sun, 2 Jul 2023 13:33:53 +0000 (09:33 -0400)]
agx: Add try_coalesce_with helper
Common logic the next few patches will use to try to assign something to the
same register as something else. "If it's already been assigned a register and
that register is free now, use it, otherwise bail."
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Tue, 6 Jun 2023 22:57:47 +0000 (18:57 -0400)]
asahi: Forbid 2D Linear with images
There's no known use case, so forbidding this reduces the combinatorics required
in the texture atomic lowering.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Thu, 25 May 2023 19:58:19 +0000 (15:58 -0400)]
asahi: Don't restrict sampler views
We now emulate an infinitely large binding table with bindless, so the sky is
the limit for this CAP. Note we still have the limit for samplers, so this
probably doesn't do anything for OpenGL.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Wed, 28 Jun 2023 19:41:28 +0000 (15:41 -0400)]
asahi: Make clear the non-sRGBness of EOT images
For sRGB render targets, we encode sRGB when writing pixels into the tilebuffer
(in the fragment shader), not when writing out the image. When we actually write
out the tilebuffer to the image, we don't use the PBE's sRGB conversion, we just
bind it as a UNORM 8 image and blit the pre-transformed pixels.
We're about to add real sRGB support for the PBE, so make this linearization
explicit.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Thu, 25 May 2023 20:21:20 +0000 (16:21 -0400)]
asahi: Upload image descriptors
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Thu, 25 May 2023 20:02:44 +0000 (16:02 -0400)]
asahi: Upload at most the max texture state registers
The rest are bindless now.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Sat, 20 May 2023 17:24:13 +0000 (13:24 -0400)]
asahi: Add texture/image indexing lowering pass
Both textures and images share a unified indexing scheme in AGX. When binding
tables are used, they can be mapped to texture state registers. Otherwise, there
is bindless access available.
It would be nice to map OpenGL's binding table based textures and images to AGX
texture state registers 1:1. The problem is that OpenGL allows more combined
textures and images than we necessarily have texture state registers. So, we use
as many texture state registers as we can, and then we fallback on an internal
bindless scheme mapping an extended binding table.
Add and use a lowering pass to map all of the API-level texture/image indices to
either texture state registers or bindless handles as required.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Fri, 19 May 2023 20:03:15 +0000 (16:03 -0400)]
asahi: Add agx_batch_track_image helper
Adapted from Panfrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Wed, 7 Jun 2023 00:28:11 +0000 (20:28 -0400)]
asahi: Reallocate to set the writeable image flag
...If needed, for array images.
But avoid doing so for non-array images.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Tue, 6 Jun 2023 23:44:40 +0000 (19:44 -0400)]
asahi: Mark writeable images as such
ail needs this information to select the appropriate layout.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Fri, 19 May 2023 22:12:22 +0000 (18:12 -0400)]
ail: Page-align layers for writable images
This appears to be necessary for PBE writes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Wed, 5 Jul 2023 16:19:51 +0000 (12:19 -0400)]
asahi,agx: Set coherency bit for clustered targets
We need to set a particular bit on atomics for them to be coherent across
clusters. Fixes atomics on G13X.
Setting this bit on the single-cluster G13G, on the other hand, wedges the GPU.
So best be careful ;-)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Janne Grunau [Wed, 5 Jul 2023 18:58:48 +0000 (20:58 +0200)]
asahi: toggle more barrier bits after transform feedback
Fixes KHR-GLES31.core.draw_indirect.advanced-twoPass-transformFeedback-arrays
and KHR-GLES31.core.draw_indirect.advanced-twoPass-transformFeedback-elements
on M1 Ultra (G13D). Let's assume that same bits are required on M1 Pro
and Max.
Signed-off-by: Janne Grunau <j@jannau.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Thu, 20 Jul 2023 13:58:26 +0000 (09:58 -0400)]
asahi: Identify background/EOT counts
Similar to the counts for VDM/PDM/CDM.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Thu, 29 Jun 2023 00:24:40 +0000 (20:24 -0400)]
asahi: Serialize NIR in memory
Deserializing isn't expected to be much more expensive than cloning, and the
serialized NIR is *significantly* smaller. So store the serialized instead of
the deserialized, and deserialize on the fly.
This reduces a lot of noise in valgrind due to random crap alloc'd against the
NIR shader by lowering passes that now get properly freed.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Thu, 25 May 2023 18:34:42 +0000 (14:34 -0400)]
asahi: Extract shader_initialize helper
To fill out an agx_uncompiled_shader struct, since the logic was duplicated
between graphics and compute.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Asahi Lina [Wed, 5 Jul 2023 11:28:46 +0000 (20:28 +0900)]
asahi: Add nomsaa debug flag
This forces off MSAA, which together with smalltile mode helps test more
combinations.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Asahi Lina [Wed, 5 Jul 2023 11:25:01 +0000 (20:25 +0900)]
asahi: Add smalltile debug option
This lets us force small tiles when they otherwise would not be
necessary, which is useful for decoupling tile size and the logic that
depends on it from things like MSAA and MRT which can trigger small
tiles.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Asahi Lina [Wed, 5 Jul 2023 11:16:19 +0000 (20:16 +0900)]
asahi: Add synctvb debug flag
This requests synchronous TVB growth (instead of split renders). Mostly
for testing at this point.
Only works with newer kernels and the kernel will complain on dmesg for
now.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Fri, 19 May 2023 18:09:17 +0000 (14:09 -0400)]
asahi: Refactor PBE upload routine
In general, PBE descriptors map pipe_image_views for the hardware. That we use a
writeable shader image internally for render targets is an implementation-detail
of the end-of-tile program. So, refactor the PBE upload routine to take a
pipe_image_view (not a pipe_surface), and translate the pipe_surface into an
internal pipe_image_view for end-of-tile programs.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Wed, 5 Jul 2023 02:26:36 +0000 (22:26 -0400)]
asahi: Remove unused #define
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Wed, 5 Jul 2023 02:24:28 +0000 (22:24 -0400)]
asahi: Use nir_builder_at more
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Alyssa Rosenzweig [Thu, 20 Jul 2023 14:45:18 +0000 (10:45 -0400)]
asahi: Augment fake drm_asahi_params_global
Stub out a bit more UAPI so we can build with the additions in this patch
series.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
Sergi Blanch Torne [Mon, 17 Jul 2023 06:54:58 +0000 (08:54 +0200)]
Integrate ci-kdl in the building process and launch process.
Modify the build process for the images to include the build to have ci-kdl
available in the Mesa jobs. Modify also the init-stage2 to launch in the
background the process that will collect data and store a json file with the
relative changes on the recorded data.
Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24177>
Sergi Blanch Torne [Mon, 17 Jul 2023 06:51:00 +0000 (08:51 +0200)]
Introduce ci-kdl builder and launcher.
A tool to collect relative changes in some registers of sysfs can be used in
the Mesa jobs to record information while the tests are being executed.
Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24177>
Vignesh Raman [Thu, 20 Jul 2023 03:47:53 +0000 (09:17 +0530)]
ci: add Vignesh Raman into restricted traces access list
Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24247>
Eric Engestrom [Mon, 17 Jul 2023 11:22:17 +0000 (12:22 +0100)]
ci: delete install.tar after extracting it to avoid re-uploading it
Leaving it means it gets re-uploaded when sync'ing the artifacts back
from the DUT to GitLab.
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24196>
Pavel Ondračka [Thu, 20 Jul 2023 08:40:09 +0000 (10:40 +0200)]
r300: fix cycles calculation
There might be more texture semaphores per begin tex block, just do the
cycles calculation on the first one.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24250>
Lionel Landwerlin [Thu, 20 Jul 2023 05:42:10 +0000 (08:42 +0300)]
ci/a530: switch a few tests to flakes to unblock CI
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24248>
Felix DeGrood [Tue, 18 Jul 2023 18:48:48 +0000 (18:48 +0000)]
intel/compiler: use shader source hash in shader dump code
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23942>
Felix DeGrood [Wed, 28 Jun 2023 21:15:45 +0000 (21:15 +0000)]
intel: use shader source hash in INTEL_MEASURE
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23942>
Felix DeGrood [Tue, 18 Jul 2023 18:02:36 +0000 (18:02 +0000)]
mesa: propagate shader source sha1 from gl_shader to nir_shader
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23942>
Felix DeGrood [Wed, 28 Jun 2023 23:40:46 +0000 (23:40 +0000)]
iris: save shader source sha1 in ish
Save lowest dword of shader source sha1 in pipeline object for use
later as hash for uniquely identifying shader in debug outputs.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23942>
Felix DeGrood [Thu, 29 Jun 2023 04:03:03 +0000 (04:03 +0000)]
anv: Add Source hash field to VkPipelineExecutableStatisticKHR
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23942>
Felix DeGrood [Wed, 28 Jun 2023 20:58:33 +0000 (20:58 +0000)]
anv: save a shader source uint32_t hash in gfx/compute pipelines
Save lowest dword of shader source sha1 in pipeline object for use
later as hash for uniquely identifying shader in debug outputs.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23942>
Lionel Landwerlin [Thu, 13 Jul 2023 23:10:20 +0000 (02:10 +0300)]
intel/compiler: rework input parameters
Use a struct for various common parameters rather than per stage
structure or arguments to stage specific entrypoints.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23942>
Konstantin Seurer [Tue, 18 Jul 2023 13:12:15 +0000 (15:12 +0200)]
radv/meta_buffer: Rename size_minus16 to max_offset
It's just better.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24213>
Konstantin Seurer [Tue, 18 Jul 2023 12:53:24 +0000 (14:53 +0200)]
radv/meta_buffer: Stop setting RADV_META_SAVE_DESCRIPTORS
Everything is done via push constants.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24213>
Konstantin Seurer [Tue, 18 Jul 2023 12:39:27 +0000 (14:39 +0200)]
radv: Stop using the misleading round_up_u* functions
The functions had the same behavior as DIV_ROUND_UP but their names do
not mention a division.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24210>
Pavel Ondračka [Fri, 14 Jul 2023 08:05:35 +0000 (10:05 +0200)]
r300: cycles estimate for shader-db
To account for:
- macro MAD in vs
- NOPs needed before presubtract
- texture scheduling and a proper texture semaphore usage
The docs don't mention any other references to extra cycles, so otherwise
we assume 1 instruction = 1 cycle.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7573
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24152>
Pavel Ondračka [Fri, 14 Jul 2023 08:05:27 +0000 (10:05 +0200)]
r300: add a helper for checking number of temporary sources
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24152>
Pavel Ondračka [Fri, 14 Jul 2023 06:22:23 +0000 (08:22 +0200)]
r300: normal instruction can't have presubtract op
Only fs have presubtract ops and by the time we gather the stats,
all normal instructions were converted to pair ones.
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24152>
Pavel Ondračka [Fri, 14 Jul 2023 10:22:15 +0000 (12:22 +0200)]
r300: bump the RC_MAX_INDEX_BITS
We skip ntt regalloc for vertex shaders and we have 1024 instruction
limit for R500 vs, so in theory we could run some shaders with more that
1024 ssa registers (if we can optimize the number of instruction in the
backend). So add one more bit.
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24154>
Pavel Ondračka [Fri, 14 Jul 2023 10:21:06 +0000 (12:21 +0200)]
r300: source register index is always unsigned
This was forgotten when we converted to the NIR lowering of negative
indirect adressing.
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24154>
Pavel Ondračka [Fri, 14 Jul 2023 10:16:28 +0000 (12:16 +0200)]
r300: check for index overflow when translating from TGSI
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24154>
David Heidelberg [Sat, 8 Jul 2023 12:06:02 +0000 (14:06 +0200)]
ci/panfrost: introduce OpenGL testing with Mali-G57 MP5 on Asurada chromebook
Copy-paste *-skips,fails,flakes from g52.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24198>
Alyssa Rosenzweig [Wed, 19 Jul 2023 12:42:35 +0000 (08:42 -0400)]
panfrost: Fix transform feedback on v9 harder
We might need more push uniforms (FAU) than the currently bound program. Update
that too for correct results on v9.
Fixes:
c282f80c988 ("panfrost: Fix transform feedback on v9")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24198>
Alyssa Rosenzweig [Wed, 19 Jul 2023 12:02:22 +0000 (08:02 -0400)]
panfrost: Lower vertex_id for XFB
Even on Valhall, vertex_id is zero-based in a transform feedback program. Lower
that for transform feedback programs properly since it wouldn't happen
automatically on Valhall. Fixes assertion fails.
Fixes:
91ffd103510 ("pan/bi: Lower gl_VertexID in NIR")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24198>
Chia-I Wu [Wed, 19 Jul 2023 20:46:39 +0000 (13:46 -0700)]
amd/ci: update radv-stoney-aco-fails.txt for depth/stencil clear
This MR fixes the
stencil_d32_sfloat_s8_uint_load_op_none_store_op_none_write_off one.
The rest appears to be outdated.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22114>
Chia-I Wu [Tue, 27 Jun 2023 18:00:41 +0000 (11:00 -0700)]
radv: fix separate depth/stencil layouts in clear meta
Depth and stencil can be in different layouts.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22114>
Chia-I Wu [Tue, 27 Jun 2023 19:22:16 +0000 (12:22 -0700)]
radv: refactor depth clear in clear meta
Modify what we pass to radv_fast_clear_depth and emit_depthstencil_clear
in preparation for separate depth/stencil layouts.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22114>
Chia-I Wu [Tue, 27 Jun 2023 18:00:41 +0000 (11:00 -0700)]
radv: fix separate depth/stencil layouts in resolve meta
Depth and stencil can be in different layouts.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22114>
Chia-I Wu [Tue, 27 Jun 2023 20:48:12 +0000 (13:48 -0700)]
radv: fix separate depth/stencil layouts in fb state
Set S_028000_DEPTH_COMPRESS_DISABLE/S_028000_STENCIL_COMPRESS_DISABLE
depending on the depth/stencil layouts respectively.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22114>
Dave Airlie [Thu, 12 Jan 2023 02:49:47 +0000 (12:49 +1000)]
ci: remove binding model from the asan skips for lavapipe.
These should be fine now.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20661>
Asahi Lina [Fri, 7 Apr 2023 14:14:24 +0000 (23:14 +0900)]
docs/tgsi: Specify that depth texture fetches are replicated
This is what drivers do, and code like u_blitter expects this.
Commit
6cac9c748eb8 implied that this was already specified, but only
stencil actually was, depth was still listed as TBD. Let's actually
specify this for future reference.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22361>
José Roberto de Souza [Tue, 18 Jul 2023 16:05:21 +0000 (09:05 -0700)]
anv: Add support for userptr in Xe KMD
Xe KMD only requires userptr to be bound to VM, so here reusing
workaround_bo->gem_handle id to all userptr bos in Xe version of
gem_create_userptr(). The Xe version of gem_close() will make sure
that workaround_bo->gem_handle is not closed when userptr bos
are closed.
With the same gem_handle for all userptr bos, it was also necessary
skip the anv_device_lookup_bo() and manually allocate memory to store
anv_bo in host heap memory, what lead to some small changes in
anv_device_release_bo() as well.
The remaining changes are the support to VM bind userptr bos and the
gem_vm_bind() call in anv_device_import_bo_from_host_ptr().
Fixes: dEQP-VK.memory.external_memory_host*
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23787>
José Roberto de Souza [Tue, 18 Jul 2023 16:03:13 +0000 (09:03 -0700)]
anv: Replace handle by anv_bo in the gem_close()
struct anv_bo will be needed in the next patch to properly handle
closure of userptr bos.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23787>
José Roberto de Souza [Wed, 21 Jun 2023 23:30:39 +0000 (16:30 -0700)]
anv: Add gem_create_userptr() to KMD backend
Xe support of userptr will be implemented in the next patch,
this is just moving the i915 and stub functions to KMD backend.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23787>
Lionel Landwerlin [Wed, 19 Jul 2023 13:55:21 +0000 (16:55 +0300)]
intel/fs: fix missing predicate on SEL instruction
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
d8dfd153c5 ("intel/fs: Make per-sample and coarse dispatch tri-state")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9381
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24236>
Mike Blumenkrantz [Mon, 26 Jun 2023 12:43:33 +0000 (08:43 -0400)]
zink: set feedback attachments on batch init
just to be safe
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23766>
Mike Blumenkrantz [Wed, 21 Jun 2023 11:44:28 +0000 (07:44 -0400)]
zink: set pipeline dynamic state count after all dynamic states are set
Fixes:
d17c081b7c6 ("zink: use dynamic state for feedback loops when available")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23766>
Caio Oliveira [Tue, 18 Jul 2023 18:55:01 +0000 (11:55 -0700)]
nir: Use instructions_pass() for nir_fixup_deref_modes()
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24220>
Danylo Piliaiev [Tue, 18 Jul 2023 12:41:03 +0000 (14:41 +0200)]
ir3: Fix FS quad ops returning wrong values from helper invocations
Without SP_FS_CTRL_REG0.LODPIXMASK quad ops don't get values from
helper invocations, but from the current one.
Fixes:
dEQP-VK.glsl.derivate.dfdxsubgroup.*
dEQP-VK.glsl.derivate.dfdysubgroup.*
Cc: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24211>
Danylo Piliaiev [Wed, 19 Jul 2023 15:37:53 +0000 (17:37 +0200)]
freedreno/regs: Rename SP_FS_CTRL_REG0.DIFF_FINE into LODPIXMASK
That's the "real" name of the field.
It enables ALL helper invocations in a quad, which is necessary for
fine derivatives and quad subgroup ops.
While PIXLODENABLE by itself enables only 3 out 4 fragments in a quad.
Cc: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24211>
Gert Wollny [Wed, 19 Jul 2023 15:27:19 +0000 (17:27 +0200)]
r600/sfn: remove debug output leftovers
Fixes:
ae7d904a73b57f6f019346b3926cde5263bff787
r600/sfn: Implement source mod optimization in backend
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24239>
David Rosca [Mon, 17 Jul 2023 10:57:34 +0000 (12:57 +0200)]
radeonsi/vcn: Fix setting color range in AV1 bitstream
As per spec color_range and chroma_sample_position parameters
are always set, not conditional on color_description_present_flag.
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24179>
José Roberto de Souza [Mon, 10 Jul 2023 18:24:22 +0000 (11:24 -0700)]
intel/aux_map: Add function and macro to return l2 and l1 table masks
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24077>
José Roberto de Souza [Mon, 10 Jul 2023 16:54:05 +0000 (09:54 -0700)]
intel/aux_map: Drop magic sub table size number
Each entry is a uint64_t, L2 and L1 maps 12 bits so:
(1 << 12) = 4096
sizeof(uint64_t) = 8
4096 * 8 = 32768 = 32K
Same value but easier to understand.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24077>
José Roberto de Souza [Mon, 10 Jul 2023 17:42:43 +0000 (10:42 -0700)]
intel/aux_map: Convert l1_entry_addr_out to canonical
The expression 'l1_gpu_addr + l1_index * sizeof(*l1_map)' could cause
bit 47 to be set so it needs to be converted to canonical.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24077>
José Roberto de Souza [Mon, 10 Jul 2023 17:36:49 +0000 (10:36 -0700)]
intel/aux_map: Mask out bits above index 47 in intel_aux_get_meta_address_mask()
The bits above index 47 in l1 entry are used to define format,
depth and luminance.
aux_address is formated as canonical, so bits above 47 could all be
set to 1 causing wrong values being set to format, depth and luminance.
intel_aux_get_meta_address_mask() was previously using 2 shifts to
mask out bits above index 47, what is not so obvious and are 2
operations, so here doing a AND with VALID_ADDRESS_MASK to make it
easier to understand.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24077>
José Roberto de Souza [Fri, 7 Jul 2023 17:02:59 +0000 (10:02 -0700)]
intel/aux_map: Rename some variables to improve readability
No changes in behavior here, mostly doing this types of renames:
- address to main_address, to know that addresses refers to main
surface address or aux surface address
- gpu to addr
- main_map_addr to main_inc_addr
- aux_dest_addr to aux_inc_addr
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24077>
José Roberto de Souza [Fri, 7 Jul 2023 17:04:25 +0000 (10:04 -0700)]
intel/aux_map: Replace magic number by INTEL_AUX_MAP_ENTRY_VALID_BIT
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24077>
José Roberto de Souza [Mon, 10 Jul 2023 19:04:57 +0000 (12:04 -0700)]
intel/aux_map: Use get_aux_entry() in remove_mapping()
remove_mapping() duplicated almost half of get_aux_entry(), it is
only dropping the cases were entries are not alocated but during
removal it is expected that entries were already alocated so we can
reuse get_aux_entry() and drop duplicated code.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24077>
José Roberto de Souza [Mon, 10 Jul 2023 20:29:16 +0000 (13:29 -0700)]
intel/aux_map: Nuke format_enum
The only user of format_enum is intel_aux_map_get_alignment() that
can easily use information in format->main_page_size.
This allow us to nuke format_enum and remove duplicated information
in intel_aux_map_get_alignment().
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24077>
Lucas Stach [Fri, 14 Jul 2023 21:32:06 +0000 (23:32 +0200)]
etnaviv: initialize VIVS_GL_BUG_FIXES
Same as the blob, always initialize this state when feature
BUG_FIXES18 is present.
Fixes spec@!opengl 2.0@occlusion-query-discard on GC3000.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24166>
Samuel Pitoiset [Wed, 19 Jul 2023 08:37:30 +0000 (10:37 +0200)]
zink/ci: update list of expected failures for NAVI10
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24232>
Robert Mader [Tue, 11 Jul 2023 14:24:41 +0000 (16:24 +0200)]
egl/wayland: wait for compositor to release shm buffers
Some Wayland compositors, notably Exo, do not always release buffers
fast enough, and not in sync with their frame callbacks, to guarantee
that a free buffer is available the next time a client calls
`eglSwapBuffers()`.
This currently leads to a crash in `dri2_wl_swrast_get_backbuffer_data()`
with the swrast backend. To avoid this, simply block until the
compositor releases a buffer eventually.
While arguably compositors should release buffers they don't need any
more for the next frame, this can be quite complex depending on
the architecture - notably multi-process/IPC in case of Exo.
cc: mesa-stable
Signed-off-by: Robert Mader <robert.mader@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24091>
projects / platform / upstream / mesa.git / log