Chuanqi Xu [Mon, 7 Feb 2022 04:47:14 +0000 (12:47 +0800)]
[NFC] Precommit test case for PR53357
zhongyunde 00443407 [Mon, 10 Jan 2022 01:18:57 +0000 (09:18 +0800)]
[DAGCombiner][AArch64] Enhance to support for scalar CSINC
Enhance to fold csel into csinc instruction.
Fix https://github.com/llvm/llvm-project/issues/53071
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D116915
Phoebe Wang [Mon, 7 Feb 2022 01:22:19 +0000 (09:22 +0800)]
[X86] Add pre-commit test for bit test optimization. NFC
Jacques Pienaar [Mon, 7 Feb 2022 01:21:48 +0000 (17:21 -0800)]
[mlir][bazel] Update post ControlFlow dialect split
Kazu Hirata [Mon, 7 Feb 2022 00:36:29 +0000 (16:36 -0800)]
[IR] Use default member initialization in GlobalValue (NFC)
Kazu Hirata [Mon, 7 Feb 2022 00:36:27 +0000 (16:36 -0800)]
[Transforms] Use default member initialization in LibCallSimplifier (NFC)
Kazu Hirata [Mon, 7 Feb 2022 00:36:25 +0000 (16:36 -0800)]
[Transforms] Use default member initialization in LoopVersioning (NFC)
Benjamin Kramer [Sun, 6 Feb 2022 13:06:34 +0000 (14:06 +0100)]
[mlir] Use SmallBitVector instead of SmallDenseSet for AffineMap::compressSymbols
This is both more efficient and more ergonomic to use, as inverting a
bit vector is trivial while inverting a set is annoying.
Sadly this leaks into a bunch of APIs downstream, so adapt them as well.
This would be NFC, but there is an ordering dependency in MemRefOps's
computeMemRefRankReductionMask. This is now deterministic, previously it
was dependent on SmallDenseSet's unspecified iteration order.
Differential Revision: https://reviews.llvm.org/D119076
River Riddle [Sun, 6 Feb 2022 23:10:03 +0000 (15:10 -0800)]
[mlir] Fix GpuToLLVM conversion pass after ControlFlow operations were split from Standard
Stella Laurenzo [Sun, 6 Feb 2022 05:50:27 +0000 (21:50 -0800)]
[mlir] Fixup python bindings after splitting cf ops from std.
River Riddle [Fri, 4 Feb 2022 04:59:43 +0000 (20:59 -0800)]
[mlir] Split out a new ControlFlow dialect from Standard
This dialect is intended to model lower level/branch based control-flow constructs. The initial set
of operations are: AssertOp, BranchOp, CondBranchOp, SwitchOp; all split out from the current
standard dialect.
See https://discourse.llvm.org/t/standard-dialect-the-final-chapter/6061
Differential Revision: https://reviews.llvm.org/D118966
Eugene Zhulenev [Sun, 6 Feb 2022 22:38:33 +0000 (14:38 -0800)]
[mlir] Add canonicalizer to remove redundant shape.cstr_broadcastable ops
Depends On D119025
Reviewed By: frgossen
Differential Revision: https://reviews.llvm.org/D119043
Congzhe Cao [Sun, 6 Feb 2022 21:55:20 +0000 (16:55 -0500)]
[LoopInterchange] Support loop interchange with floating point reductions
Enabled loop interchange support for floating point reductions
if it is allowed to reorder floating point operations.
Previously when we encouter a floating point PHI node in the
outer loop exit block, we bailed out since we could not detect
floating point reductions in the early days. Now we remove this
limiation since we are able to detect floating point reductions.
Reviewed By: #loopoptwg, Meinersbur
Differential Revision: https://reviews.llvm.org/D117450
Mehdi Amini [Sun, 6 Feb 2022 19:48:25 +0000 (19:48 +0000)]
Remove dead forward declaration (NFC)
Simon Pilgrim [Sun, 6 Feb 2022 19:40:08 +0000 (19:40 +0000)]
[KnownBits] Add support for X*X self-multiplication (update)
Rename the SelfMultiply argument to make it clearer that the argument must not be undef
Differential Revision: https://reviews.llvm.org/D108992
Simon Pilgrim [Sun, 6 Feb 2022 19:13:11 +0000 (19:13 +0000)]
[InstCombine] Add mul(x,x) tests showing miscompile
As raised by @efriedma on D117995 - the source must not be undef to demand any bits in mul(x,x) other than bit[1]
https://alive2.llvm.org/ce/z/Cxkjen
Craig Topper [Sun, 6 Feb 2022 18:44:05 +0000 (10:44 -0800)]
[DAGCombiner][RISCV] Allow rotates by non-constant to be matched for i32 on riscv64 with Zbb.
rv64izbb has a RORW/ROLW instructions that operate on the lower
32-bits of a 64-bit value and sign extend bit 31 of the result.
DAGCombiner won't match rotate idioms because the i32 type isn't Legal
on riscv64.
This patch teaches DAGCombiner to allow it if the type is going to
be promoted and the target has Custom type legalization for ISD::ROTL
or ISD::ROTR. I've restricted this to scalar types. It doesn't appear
any in tree targets other than riscv64 have custom type legalization
for rotates.
If this patch isn't acceptable, I guess I can match SRLW, SLLW, and OR
after type legalization, but I'd like to avoid that if possible.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D119062
Kazu Hirata [Sun, 6 Feb 2022 18:54:48 +0000 (10:54 -0800)]
[llvm] Fix header guards (NFC)
Identified with llvm-header-guard.
Kazu Hirata [Sun, 6 Feb 2022 18:54:46 +0000 (10:54 -0800)]
[Breakpoint] Remove redundant member initialization (NFC)
Identified with readability-redundant-member-init.
Kazu Hirata [Sun, 6 Feb 2022 18:54:44 +0000 (10:54 -0800)]
[CodeGen] Use = default (NFC)
Identified with modernize-use-equals-default
Kazu Hirata [Sun, 6 Feb 2022 18:54:42 +0000 (10:54 -0800)]
[Driver] Remove redundant string initialization (NFC)
Identified with readability-redundant-string-init.
Jared Irwin [Sun, 6 Feb 2022 17:36:12 +0000 (12:36 -0500)]
[lld-macho] Add -pagezero_size
Adds `-pagezero_size`. `-pagezero_size` commonly used for kernel development.
`-pagezero_size` changes the `__PAGEZERO` size, removing that segment if it is set to zero.
One of the four flags from {D118570}
Now with error messages and tests.
Differential Revision: https://reviews.llvm.org/D118724
Bjorn Pettersson [Wed, 2 Feb 2022 09:20:00 +0000 (10:20 +0100)]
[DAGCombiner] Fold SSHLSAT/USHLSAT to SHL when no saturation will occur
When the shift amount is known and a known sign bit analysis of
the shiftee indicates that no saturation will occur, then we can
replace SSHLSAT/USHLSAT by SHL.
Differential Revision: https://reviews.llvm.org/D118765
Bjorn Pettersson [Wed, 2 Feb 2022 09:08:26 +0000 (10:08 +0100)]
Pre-commit test cases for DAG combine folds of SSHLSAT/USHLSAT -> SHL
It should be possible to replace SSHLSAT and USHLSAT with SHL when
it is known that no saturation will take place (e.g. by analysing
known sign bits in the first shift operand).
Differential Revision: https://reviews.llvm.org/D118764
Simon Pilgrim [Sun, 6 Feb 2022 17:19:23 +0000 (17:19 +0000)]
Revert rG7275de7fb2f087871611d037d1b529b226dd0521 "[AArch64] translateLocChar - silence dead code warning"
Seems to cause some buildbot misbehaviour (+ there's a dumb copy+paste typo in the commit message....)
Simon Pilgrim [Sun, 6 Feb 2022 17:17:28 +0000 (17:17 +0000)]
[clang][CodeGen] Add _BitInt test coverage to builtins-elementwise-math.c
As suggested on D117898, we should be testing irregular _BitInt types with the __builtin_elementwise_* intrinsics
Simon Pilgrim [Sun, 6 Feb 2022 16:52:23 +0000 (16:52 +0000)]
Fix Wdocumentation unknown parameter warning
Florian Hahn [Sun, 6 Feb 2022 16:37:20 +0000 (16:37 +0000)]
[LV] Use VPReplicateRecipe::isUniform instead isUniformAfterVec (NFCI).
In scalarizeInstruction(), isUniformAfterVectorization is used to detect
cases where it is sufficient to always access the first lane. This
should map directly checking whether the operand is a uniform replicate
recipe.
Differential Revision: https://reviews.llvm.org/D116654
Simon Pilgrim [Sun, 6 Feb 2022 16:32:16 +0000 (16:32 +0000)]
[AArch64] translateLocChar - silence dead code warning
Remove default case from switch and return None after the switch()
Simon Pilgrim [Sun, 6 Feb 2022 16:29:38 +0000 (16:29 +0000)]
[AArch64] LowerVectorSRA_SRL_SHL - silence dead code warning
Remove default case from switch and move llvm_unreachable to after the switch()
Simon Pilgrim [Sun, 6 Feb 2022 16:25:44 +0000 (16:25 +0000)]
[Support] Use llvm_unreachable instead of LLVM_BUILTIN_UNREACHABLE internal define
David Green [Sun, 6 Feb 2022 16:17:06 +0000 (16:17 +0000)]
[ARM] Mark i64 and f64 shuffles as Custom for MVE
This way they get lowered through the ARMISD::BUILD_VECTOR, which can
produce more efficient D register moves.
Also helps D115653 not get stuck in a loop.
David Green [Sun, 6 Feb 2022 14:12:28 +0000 (14:12 +0000)]
[ARM] Add extra vabd, vhadd and vmulh tests. NFC
This is some extra testing for vabd, vhadd and vmulh. Some of the tests
have also be reordered.
Simon Pilgrim [Sun, 6 Feb 2022 12:53:11 +0000 (12:53 +0000)]
[X86] Fold ZERO_EXTEND_VECTOR_INREG(BUILD_VECTOR(X,Y,?,?)) -> BUILD_VECTOR(X,0,Y,0)
Helps avoid some unnecessary shift by splat amount extensions before shuffle combining gets limited by with one use checks
Fangrui Song [Sun, 6 Feb 2022 07:34:14 +0000 (23:34 -0800)]
[ELF] Fix crash when an input is incompatible with a lazy object file
The diagnostic is concise. It is ok because the case is rare.
Stella Laurenzo [Sun, 6 Feb 2022 06:04:19 +0000 (22:04 -0800)]
[mlir] Do not use an empty source file when building aggregate libraries.
See discussion: https://discourse.llvm.org/t/check-mlir-times-examples-standalone-testing-time/6073/7
It turns out that it has been legal since CMake 3.11 to omit sources at library creation time if they are added later via target_sources, as is done here. This side-steps the issue of having a file that changes and invalidates the build of leaves.
Differential Revision: https://reviews.llvm.org/D119069
Rong Xu [Fri, 4 Feb 2022 20:23:47 +0000 (12:23 -0800)]
[SampleFDO] Enable FSAFDO loading passes if --enable-fs-discriminator is enabled
FSAFDO profile loader is currently disabled even --enable-fs-discriminator is enabled.
They need to be turned on by options which makes it cumbersome for experiments.
This patch changes the FSAFDO profile loader enabled by default. Since they are
guarded by EnableFSDiscriminator, they will only be turned on if
--enable-fs-discriminator is enabled. Note that --enable-fs-discriminator is
still disabled by default.
Differential Revision: https://reviews.llvm.org/D119033
Kazu Hirata [Sun, 6 Feb 2022 05:39:27 +0000 (21:39 -0800)]
[Transforms] Use default member initialization in SCEVFindUnsafe (NFC)
Kazu Hirata [Sun, 6 Feb 2022 05:39:25 +0000 (21:39 -0800)]
[Transforms] Use default member initialization in AAIsDeadCallSiteReturned (NFC)
Kazu Hirata [Sun, 6 Feb 2022 05:39:23 +0000 (21:39 -0800)]
[Transforms] Use default member initialization in TruncInstCombine (NFC)
Kazu Hirata [Sun, 6 Feb 2022 05:39:21 +0000 (21:39 -0800)]
[Transforms] Use default member initialization in MaskOps (NFC)
Kazu Hirata [Sun, 6 Feb 2022 05:39:19 +0000 (21:39 -0800)]
[Transforms] Use default member initialization in EscapeEnumerator (NFC)
Kazu Hirata [Sun, 6 Feb 2022 05:39:17 +0000 (21:39 -0800)]
[IR] Use default member initialization in PMDataManager (NFC)
Craig Topper [Sat, 5 Feb 2022 21:54:38 +0000 (13:54 -0800)]
[RISCV] Add signext test for llvm.abs.i32 for rv64 Zbb.
This shows that we don't preserve sign bits across the
abs expansion, but I think we could if we used negw+max.
Fangrui Song [Sun, 6 Feb 2022 04:43:51 +0000 (20:43 -0800)]
[ELF] SharedFile::parse: move verdefIndex assignment outside of ctor. NFC
SharedSymbol::SharedSymbol initializes verdefIndex and Symbol::replace
copies verdefIndex.
By move verdefIndex assignment outside of ctor, Symbol::replace can be changed
to not copy verdefIndex. This can be used to decrease work for for
ObjKind/BitcodeKind.
Ruiling Song [Mon, 17 Jan 2022 06:54:38 +0000 (14:54 +0800)]
AMDGPU: Don't clobber source register for V_SET_INACTIVE_*
The WWM register has unmodeled register liveness, For v_set_inactive_*,
clobberring source register is dangerous because it will overwrite the
inactive lanes. When the source vgpr is dead at v_set_inactive_lane,
the inactive lanes may be not really dead. This may make common
optimizations doing wrong.
For example in a simple if-then cfg in Machine IR:
bb.if:
%src =
bb.then:
%src1 = COPY %src
%dst = V_SET_INACTIVE %src1(tied-def 0), %inactive
bb.end
... = PHI [0, %bb.then] [%src, %bb.if]
The register coalescer will think it is safe to optimize "%src1 = COPY %src"
in bb.then. And at the same time, there is no interference for the PHI in
bb.end. The source and destination values of the PHI will be assigned
the same register. The single PHI register will be overwritten by the
v_set_inactive, then we would get wrong value in bb.end.
With this change, we will copy the content of the source register before
setting inactive lanes after register allocation. Yes, this will sacrifice
the WWM code generation a little, but I don't have any better idea to do things
correctly.
Differential Revision: https://reviews.llvm.org/D117482
Ruiling Song [Tue, 18 Jan 2022 00:29:10 +0000 (08:29 +0800)]
AMDGPU: add test to show wwm register overwrite issue
Pre-commit the test to make the diff easy to read later.
Differential Revision: https://reviews.llvm.org/D117527
Krystian Kuzniarek [Sun, 6 Feb 2022 03:51:53 +0000 (19:51 -0800)]
[clang-format][docs] Fix incorrect 'clang-format 14' option markers
Introduced by
23a5090c6, some style option markers indicated 'clang-format 14',
though their respective options were available in earlier releases.
Note: Even though the value type of 'SpacesInAngles' option changed,
this option has been already present since version 3.4.
Differential Revision: https://reviews.llvm.org/D118991
Fangrui Song [Sun, 6 Feb 2022 00:34:02 +0000 (16:34 -0800)]
[ELF] Symbol::replace: use the old nameData/nameSize. NFC
Currently `this->getName() == newSym.getName()`.
By keeping the old nameData/nameSize, newSym's nameData/nameSize will be
ignored. The call sites can avoid calling getName().
printTraceSymbol needs to take the symbol name since `other`'s name is empty.
Adrian Prantl [Sun, 6 Feb 2022 00:27:47 +0000 (16:27 -0800)]
fix module build failure
Adrian Prantl [Sun, 6 Feb 2022 00:23:12 +0000 (16:23 -0800)]
fix module build failure
Adrian Prantl [Sun, 6 Feb 2022 00:20:15 +0000 (16:20 -0800)]
fix module build failure
Kazu Hirata [Sun, 6 Feb 2022 00:29:28 +0000 (16:29 -0800)]
[Support] Use default member initialization in ScopedPrinter (NFC)
Kazu Hirata [Sun, 6 Feb 2022 00:29:26 +0000 (16:29 -0800)]
[IR] Use default member initialization in GlobalObject (NFC)
Kazu Hirata [Sun, 6 Feb 2022 00:29:24 +0000 (16:29 -0800)]
[ADT] Use default member initialization in OptionalStorage (NFC)
Kazu Hirata [Sun, 6 Feb 2022 00:29:22 +0000 (16:29 -0800)]
[Transforms] Use default member initialization in SimplifyIndvar (NFC)
Kazu Hirata [Sun, 6 Feb 2022 00:29:20 +0000 (16:29 -0800)]
[ADT] Use default member initialization in DebugEpochBase (NFC)
Kazu Hirata [Sun, 6 Feb 2022 00:29:18 +0000 (16:29 -0800)]
[MC] Use default member initialization in WasmCustomSection (NFC)
Benjamin Kramer [Sat, 5 Feb 2022 23:48:05 +0000 (00:48 +0100)]
[SLP] Skip a DenseSet<unsigned> -> bit vector conversion. NFCI.
Fangrui Song [Sat, 5 Feb 2022 23:25:23 +0000 (15:25 -0800)]
[ELF] Don't access other eSym members it st_shndx == SHN_UNDEF. NFC
Fangrui Song [Sat, 5 Feb 2022 23:03:55 +0000 (15:03 -0800)]
[ELF] De-template reportUndefinedSymbols. NFC
My x86-64 lld executable is 16KiB smaller.
Adrian Prantl [Sat, 5 Feb 2022 22:54:41 +0000 (14:54 -0800)]
Revert "Disable TestLldbGdbServer on Dwarf2 and clang versions below 14"
This reverts commit
867fdec1945df3c1031d3cefdc97903131a3482b.
Adrian Prantl [Sat, 5 Feb 2022 22:54:37 +0000 (14:54 -0800)]
Revert "Fixed typos in TestLldbGdbServer.py"
This reverts commit
cf93a085754e221f73a2877c946dcb2beb6039d7.
Fangrui Song [Sat, 5 Feb 2022 22:40:15 +0000 (14:40 -0800)]
[ELF] Move Symbol::needsTlsLd to config->needsTlsLd. NFC
to decrease sizeof(SymbolUnion) from 72 to 64 on ELF64 platforms.
Benjamin Kramer [Sat, 5 Feb 2022 22:33:06 +0000 (23:33 +0100)]
Simplify mask creation with llvm::seq. NFCI.
Yaxun (Sam) Liu [Fri, 4 Feb 2022 23:18:14 +0000 (18:18 -0500)]
[HIPSPV] Fix literals are mapped to Generic address space
This issue is an oversight in D108621.
Literals in HIP are emitted as global constant variables with default
address space which maps to Generic address space for HIPSPV. In
SPIR-V such variables translate to OpVariable instructions with
Generic storage class which are not legal. Fix by mapping literals
to CrossWorkGroup address space.
The literals are not mapped to UniformConstant because the “flat”
pointers in HIP may reference them and “flat” pointers are modeled
as Generic pointers in SPIR-V. In SPIR-V/OpenCL UniformConstant
pointers may not be casted to Generic.
Patch by: Henry Linjamäki
Reviewed by: Yaxun Liu
Differential Revision: https://reviews.llvm.org/D118876
Fangrui Song [Sat, 5 Feb 2022 22:11:37 +0000 (14:11 -0800)]
[ELF] Reorder Symbol members to improve access locality. NFC
* partition and isPreemptible are frequently used. Move it to the front
* move used beside isUsedInRegularObj. They are similar and accessed together in .symtab finalizing
* move auxIdx/dynsymIndex/verdefIndex to the end.
This decreases code size.
Koakuma [Sat, 5 Feb 2022 21:08:26 +0000 (13:08 -0800)]
[libunwind] [sparc] Add SPARCv9 support
Adds libunwind support for SPARCv9 (aka sparc64). This is a rebase of @kettenis' patch D32450, which I created (with his permission) because the original review has become inactive.
The changes are of a cosmetic nature to make it fit better with the new code style, and to reuse the existing SPARCv8 code, whenever possible.
Please let me know if I posted this on the wrong place. Also, the summary of the original review is reproduced below:
> This adds unwinder support for 64-bit SPARC (aka SPARCv9). The implementation was done on OpenBSD/sparc64, so it takes StackGhost into account:
>
> https://www.usenix.org/legacy/publications/library/proceedings/sec01/full_papers/frantzen/frantzen_html/index.html
>
> Since StackGhost xor's return addresses with a random cookie before storing them on the stack, the unwinder has to do some extra work to recover those. This is done by introducing a new kRegisterInCFADecrypt "location" type that is used to implement the DW_CFA_GNU_window_save opcode. That implementation is SPARC-specific, but should work for 32-bit SPARC as well. DW_CFA_GNU_window_save is only ever generated on SPARC as far as I know.
Co-authored-by: Mark Kettenis
Reviewed By: #libunwind, thesamesam, MaskRay, Arfrever
Differential Revision: https://reviews.llvm.org/D116857
Simon Pilgrim [Sat, 5 Feb 2022 21:03:51 +0000 (21:03 +0000)]
[libunwind] Attempt to fix broken sphinx doc link
bbce75e352be0637305a1b59ac5eca7175bceece replaced `LLVM Bugzilla` with `LLVM bug tracker`
Craig Topper [Sat, 5 Feb 2022 20:51:01 +0000 (12:51 -0800)]
Revert "[RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X)."
This reverts commit
673d68cd923a9daa5065b929453bf4a4b8d39650.
This hadn't been reviewed yet.
Craig Topper [Sat, 5 Feb 2022 20:39:23 +0000 (12:39 -0800)]
[RISCV] Add more tests for rotate idioms. Add more RUN lines. NFC
We were only testing rotate idioms on rv32i. DAGCombiner won't
form ISD::ROTL/ROTR unless those operations are Legal or Custom.
They aren't for rv32 so we were only testing shift lowering.
This commit adds i64 idioms and the idioms that mask the shift
amount to avoid UB for a rotate of 0. I've added riscv64 and Zbb
RUN lines to show that we do match rotate for XLen types when
available. We currently miss i32 on rv64izbb.
Craig Topper [Fri, 4 Feb 2022 07:28:47 +0000 (23:28 -0800)]
[RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X).
Add a new ISD opcode to represent the sign extending behavior of
vmv.x.h. Keep the previous anyext opcode to allow the existing
(fmv_x_anyexth (fmv_h_x X)) combine to keep working without needing
to generate a sign extend.
For fmv.x.w we are able to match the sext_inreg in an isel pattern,
but a 16-bit sext_inreg is lowered to a shift pair before isel. This
seemed like a larger match than we should do in isel.
Differential Revision: https://reviews.llvm.org/D118974
Fangrui Song [Sat, 5 Feb 2022 20:00:34 +0000 (12:00 -0800)]
[ELF] Merge canInline into scriptDefined
They perform similar tasks and are essentially the same after
d28c26bbdd9e6e55cc0a6156e9879f7e0ca36329.
Simon Pilgrim [Sat, 5 Feb 2022 19:30:03 +0000 (19:30 +0000)]
[llvm-remark-size-diff] Don't use enum name as auto variable name
This was confusing the clang-cmake-x86_64-avx2-linux buildbot (gcc version 5.4.0).
Fangrui Song [Sat, 5 Feb 2022 19:21:44 +0000 (11:21 -0800)]
[ELF] Simplify shouldKeepInSymtab after Symbol::used is false by default. NFC
Fangrui Song [Sat, 5 Feb 2022 19:18:08 +0000 (11:18 -0800)]
[ELF] Simplify includeInSymtab. NFC
Fangrui Song [Sat, 5 Feb 2022 19:09:39 +0000 (11:09 -0800)]
[ELF] Refactor how Symbol::used is set. NFC
Simon Pilgrim [Sat, 5 Feb 2022 18:56:38 +0000 (18:56 +0000)]
[X86] Add some better common check-prefixes to slow-pmulld.ll
Try to reduce at least some of the duplication
Fangrui Song [Sat, 5 Feb 2022 18:25:25 +0000 (10:25 -0800)]
[ELF] Refactor how exportDynamic is set. NFC
Fangrui Song [Sat, 5 Feb 2022 17:56:29 +0000 (09:56 -0800)]
[ELF] --wrap: don't copy exportDynamic
For -no-pie/-pie, when `__real_foo` is interposable in a shared object, `foo` is
exported. This rule does not match GNU ld and is unneeded because:
* the exported `foo` does not interpose `__real_foo` at run-time
* the similar `__wrap_foo` <-> `foo` relation does not have the rule
Jonas Devlieghere [Sat, 5 Feb 2022 17:48:14 +0000 (09:48 -0800)]
[lldb] Use mangled symbol name to look for __asan::AsanDie()
After aed965d we no longer demangle full symbol names while indexing the
symbol table which means we have to use the mangled name instead of the
demangled name to find the symbol for __asan::AsanDie().
This fixes the following two tests:
lldb-api :: functionalities/asan/TestMemoryHistory.py
lldb-api :: functionalities/asan/TestReportData.py
Piotr Kubaj [Sat, 5 Feb 2022 17:13:42 +0000 (01:13 +0800)]
[PowerPC] Fix SSE translation on FreeBSD
This patch drops throws specifier in posix_memalign declaration because
that's different between glibc and other libc, and Clang has a hack.
Differential Revision: https://reviews.llvm.org/D117972
Simon Pilgrim [Sat, 5 Feb 2022 15:21:51 +0000 (15:21 +0000)]
[InstCombine] Add PR34063 test coverage
Sanjay Patel [Sat, 5 Feb 2022 14:05:21 +0000 (09:05 -0500)]
[InstCombine] SimplifyDemandedBits - mul(x,x) - if only demand bit[1] then fold to zero
This is a translation of the fold added to codegen with:
2d1390efbe61
Part of solving issue #48027
Nikolas Klauser [Sat, 5 Feb 2022 13:09:45 +0000 (14:09 +0100)]
[libc++] Add Unstable ABI CI run
Reviewed By: ldionne, #libc, Mordante
Spies: mgorny, Mordante, libcxx-commits, arichardson
Differential Revision: https://reviews.llvm.org/D118725
Sander de Smalen [Sat, 5 Feb 2022 14:07:44 +0000 (14:07 +0000)]
[DAGCombiner] Fold vecreduce_or/and if operand is insert_subvector.
Fold:
vecreduce_or(insert_subvec(zeroinitializer, vec))
-> vecreduce_or(vec)
vecreduce_and(insert_subvec(allones, vec))
-> vecreduce_and(vec)
vecreduce_and/or(insert_subvec(undef, vec))
-> vecreduce_and/or(vec)
This is useful for SVE which uses insert/extract subvector
to convert fixed-width to/from scalable vectors.
Reviewed By: bsmith
Differential Revision: https://reviews.llvm.org/D118919
Florian Hahn [Sat, 5 Feb 2022 14:17:07 +0000 (14:17 +0000)]
[ConstraintElimination] Add test with trivially false condition in and.
Arjun P [Wed, 2 Feb 2022 15:01:22 +0000 (20:31 +0530)]
[MLIR][Presburger] MaybeLocalRepr: add explicit bool() for convenience
This also slightly simplifies some code.
Reviewed By: Groverkss
Differential Revision: https://reviews.llvm.org/D118790
Dávid Bolvanský [Sat, 5 Feb 2022 13:26:17 +0000 (14:26 +0100)]
[clang] added allocsize attribute to allocation functions
Groverkss [Sat, 5 Feb 2022 12:38:08 +0000 (18:08 +0530)]
[MLIR][Presburger][NFC] Use getters for IntegerPolyhedron members
This patch makes IntegerPolyhedron and derived classes use of getters to access
IntegerPolyhedron space information (`numIds, numDims, numSymbols`) instead of
directly accessing them.
This patch makes it easier to change the underlying implementation of the way
identifiers are stored, making it easier to extend/modify existing implementation.
Reviewed By: arjunp
Differential Revision: https://reviews.llvm.org/D118888
Wael Yehia [Sat, 5 Feb 2022 05:08:21 +0000 (00:08 -0500)]
[AIX][PowerPC][PGO] Generate .ref for some PGO sections
For PGO on AIX, when we switch to the linux-style PGO variable access
(via _start and _stop labels), we need the compiler to generate a .ref
assembly for each of the three csects:
- __llvm_prf_data[RW]
- __llvm_prf_names[RO]
- __llvm_prf_vnds[RW]
We insert the .ref inside the __llvm_prf_cnts[RW] csect so that if it's
live then the 3 csects are live.
For example, for a testcase with at least one function definition, when
compiled with -fprofile-generate we should generate:
.csect __llvm_prf_cnts[RW],3
.ref __llvm_prf_data[RW] <<============ needs to be inserted
.ref __llvm_prf_names[RO] <<===========
the __llvm_prf_vnds is not always present, so we reference it only when
it's present.
Reviewed By: sfertile, daltenty
Differential Revision: https://reviews.llvm.org/D116607
Nikolas Klauser [Fri, 4 Feb 2022 13:28:19 +0000 (14:28 +0100)]
[libc++] __config cleanup; _LIBCPP_ABI_UNSTABLE should set _LIBCPP_ABI_VERSION
Some `__config` cleanup and `_LIBCPP_ABI_UNSTABLE` should set `_LIBCPP_ABI_VERSION`, since the latest ABI version //is// the unstable ABI.
Reviewed By: ldionne, #libc
Spies: libcxx-commits
Differential Revision: https://reviews.llvm.org/D118989
Dávid Bolvanský [Sat, 5 Feb 2022 10:44:32 +0000 (11:44 +0100)]
[clang] added alloc allign attr to memalign
Fangrui Song [Sat, 5 Feb 2022 09:10:43 +0000 (01:10 -0800)]
[ELF] Allow STV_PROTECTED shared definition to set exportDynamic
A STV_PROTECTED shared definition does not set exportDynamic of a defined
symbol. This is on the basis that a protected definition cannot be preempted so
the export is unnecessary. However, the condition is imperfect because we don't
know whether the shared object was built with a symbolic option. Since dropping
the condition simplifies code and matches GNU ld, let's do it.
Jason Molenda [Sat, 5 Feb 2022 07:53:27 +0000 (23:53 -0800)]
Increase memory buffer for scanning objc classes on darwin systems
iOS systems are getting near this limit; double itfrom a 150kb
buffer to a 300kb buffer, which is freed after processing the
list of classes.
rdar://
88454594
Differential Revision: https://reviews.llvm.org/D118972
Craig Topper [Sat, 5 Feb 2022 07:16:36 +0000 (23:16 -0800)]
[RISCV] Remove a ComputeNumSignBits call from an isel special case.
Only isel (and (srl (sexti32 Y), c2), c1) -> (srliw (sraiw Y, 31), c3 - 32)
when there is a sext_inreg present. Don't both checking for Y
having 32 sign bits.
Groverkss [Sat, 5 Feb 2022 06:25:09 +0000 (11:55 +0530)]
[MLIR][Presburger][NFC] Fix clang-tidy warnings
This patch changes variable naming to lowerCamelCase to remove
clang-tidy warning in Presburger/Utils.cpp.
Tom Stellard [Sat, 5 Feb 2022 06:22:01 +0000 (22:22 -0800)]
github: Fix automated PR creation for backports
GitHub Actions stores the token used for checking out a git repo in
the git configuration and then uses that token for pushes from that
repo too. We need to use a different token for push because we
are pushing to the llvmbot/llvm-project repo and not the upstream repo,
so we need to disable persist-credentials when checking out the source.
Bill Wendling [Sat, 5 Feb 2022 05:16:20 +0000 (21:16 -0800)]
[NFC] Remove unnecessary #includes
An attempt to reduce the number of files that are recompiled due to a change.
Differential Revision: https://reviews.llvm.org/D119055
James Y Knight [Sat, 5 Feb 2022 04:39:18 +0000 (23:39 -0500)]
Don't assume that a new cleanup was added to InnermostEHScope.
After
fa87fa97fb79, this was no longer guaranteed to be the cleanup
just added by this code, if IsEHCleanup got disabled. Instead, use
stable_begin(), which _is_ guaranteed to be the cleanup just added.
This caused a crash when a object that is callee destroyed (e.g. with the MS ABI) was passed in a call from a noexcept function.
Added a test to verify.
Fixes:
fa87fa97fb79