Igor Mammedov [Tue, 19 Jun 2012 12:46:29 +0000 (14:46 +0200)]
target-i386: drop usage of prev_debug_excp_handler
Chains of exception handlers are currently unused feature, drop it
for now so as not to expose prev_debug_excp_handler at global
scope when moving tcg initialization into target-i386/cpu.c
Later we probably could re-invent better interface for this.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Stefan Weil [Sun, 24 Jun 2012 04:18:41 +0000 (04:18 +0000)]
target-ppc: Fix 2nd parameter for tcg_gen_shri_tl
This fixes a compiler error when QEMU was configured with --enable-debug.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Stefan Weil [Sun, 24 Jun 2012 04:04:17 +0000 (04:04 +0000)]
target-ppc: Fix build with --enable-debug
The order of the arguments was wrong (copy+paste error).
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Scott Wood [Tue, 19 Jun 2012 02:31:36 +0000 (21:31 -0500)]
tci: don't write zero for reloc in tci_out_label
If tci_out_label is called in the context of tcg_gen_code_search_pc, we
could be overwriting an already patched relocation with zero -- and not
repatch it because the set_label is past search_pc, causing a QEMU crash
when it tries to branch to a zero label.
Not writing anything to the relocation area seems to be in line with what
other backends do from the couple I looked at (x86, ppc).
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Stefan Weil [Thu, 21 Jun 2012 20:18:39 +0000 (22:18 +0200)]
make: Fix dependencies for fpu/*.c and tcg/*.c
Commit
dcff25f2cd8c11a9368cc2369aeb0319c32d9e26 removed too many *.d
files. The directories fpu/ and tcg/ still don't use the recursive
subdir rules.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Stefan Weil [Sat, 23 Jun 2012 18:41:10 +0000 (20:41 +0200)]
qemu-log: Add GCC format attribute
The new inline function qemu_log_vprintf should use this attribute.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Blue Swirl [Sun, 24 Jun 2012 10:48:56 +0000 (10:48 +0000)]
Merge branch 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf
* 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf: (72 commits)
PPC: BookE206: Bump MAS2 to 64bit
PPC: BookE: Support 32 and 64 bit wide MAS2
PPC: Extract SPR dump generation into its own function
PPC: Add e5500 CPU target
PPC: BookE: Make ivpr selectable by CPU type
PPC: BookE: Implement EPR SPR
PPC: Add support for MSR_CM
PPC: Add some booke SPR defines
uImage: increase the gzip load size
PPC: e500: allow users to set the /compatible property via -machine
dt: make setprop argument static
PPC: e500: Refactor serial dt generation
dt: Add global option to set phandle start offset
PPC: e500: Extend address/size of / to 64bit
PPC: e500: Define addresses as always 64bit
PPC: e500: Use new SOC dt format
PPC: e500: Use new MPIC dt format
Revert "dt: temporarily disable subtree creation failure check"
PPC: e500: enable manual loading of dtb blob
PPC: e500: dt: use target_phys_addr_t for ramsize
...
Blue Swirl [Sun, 24 Jun 2012 10:48:01 +0000 (10:48 +0000)]
Merge branch 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
* 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: (33 commits)
target-arm: Remove ARM_CPUID_* macros
target-arm: Remove remaining old cp15 infrastructure
target-arm: Move block cache ops to new cp15 framework
target-arm: Remove c0_cachetype CPUARMState field
target-arm: Convert final ID registers
target-arm: Convert MPIDR
target-arm: Convert cp15 cache ID registers
target-arm: Convert cp15 crn=0 crm={1,2} feature registers
target-arm: Convert cp15 crn=1 registers
target-arm: Convert cp15 crn=9 registers
target-arm: Convert cp15 crn=6 registers
target-arm: convert cp15 crn=7 registers
target-arm: Convert cp15 VA-PA translation registers
target-arm: Convert cp15 MMU TLB control
target-arm: Convert cp15 crn=15 registers
target-arm: Convert cp15 crn=10 registers
target-arm: Convert cp15 crn=13 registers
target-arm: Convert cp15 crn=2 registers
target-arm: Convert MMU fault status cp15 registers
target-arm: Convert cp15 c3 register
...
Blue Swirl [Sun, 24 Jun 2012 10:45:55 +0000 (10:45 +0000)]
Merge branch 's390-for-upstream' of git://repo.or.cz/qemu/agraf
* 's390-for-upstream' of git://repo.or.cz/qemu/agraf:
s390: stop target cpu on sigp initial reset
s390: make kvm_stat work on s390
kvm: Update kernel headers
s390x: fix s390 virtio aliases
Blue Swirl [Sun, 24 Jun 2012 07:09:30 +0000 (07:09 +0000)]
Merge branch 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
* 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm:
arm_boot: Conditionalised DTB command line update
cadence_ttc: changed master clock frequency
cadence_gem: avoid stack-writing buffer-overrun
hw/a9mpcore: Fix compilation failure if physaddrs are 64 bit
hw/omap.h: Drop broken MEM_VERBOSE tracing
hw/armv7m_nvic: Make the NVIC a freestanding class
hw/arm_gic: Move CPU interface memory region setup into arm_gic_init
hw/arm_gic.c: Make NVIC interrupt numbering a runtime setting
hw/arm_gic: Make CPU target registers RAZ/WI on uniprocessor
hw/arm_gic: Add qdev property for GIC revision
hw/armv7m_nvic: Use MemoryRegions for NVIC specific registers
hw/arm_gic: Move NVIC specific reset to armv7m_nvic_reset
hw/arm_gic: Remove the special casing of NCPU for the NVIC
hw/arm_gic: Remove NVIC ifdefs from gic_state struct
arm_boot: Fix typos in comment
ARM: Exynos4210 IRQ: Introduce new IRQ gate functionality.
Alexander Graf [Thu, 21 Jun 2012 11:34:20 +0000 (13:34 +0200)]
PPC: BookE206: Bump MAS2 to 64bit
On 64bit capable systems, MAS2 can actually hold a 64bit virtual page
address. So increase the mask for its EPN.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 21 Jun 2012 12:01:06 +0000 (14:01 +0200)]
PPC: BookE: Support 32 and 64 bit wide MAS2
The MAS registers on BookE are all 32 bit wide, except for MAS2, which
can hold up to 64 bit on 64 bit capable CPUs. Reflect this in the SPR
setting code, so that the guest can never write invalid values in them.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 21 Jun 2012 11:39:48 +0000 (13:39 +0200)]
PPC: Extract SPR dump generation into its own function
This patch moves the debug #ifdef'ed SPR trace generation into its
own function, so we can call it from multiple places.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 20 Jun 2012 19:55:55 +0000 (21:55 +0200)]
PPC: Add e5500 CPU target
This patch adds e5500's CPU initialization to the TCG CPU initialization
code.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 21 Jun 2012 13:17:59 +0000 (15:17 +0200)]
PPC: BookE: Make ivpr selectable by CPU type
IVPR can either hold 32 or 64 bit addresses, depending on the CPU type. Let
the CPU initialization function pass in its mask itself, so we can easily
extend it.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 20 Jun 2012 19:27:02 +0000 (21:27 +0200)]
PPC: BookE: Implement EPR SPR
On the e500 series, accessing SPR_EPR magically turns into an access at
that CPU's IACK register on the MPIC. Implement that logic to get kernels
that make use of that feature work.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 20 Jun 2012 19:20:29 +0000 (21:20 +0200)]
PPC: Add support for MSR_CM
The BookE variant of MSR_SF is MSR_CM. Implement everything it takes in TCG to
support running 64bit code with MSR_CM set.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 20 Jun 2012 19:19:09 +0000 (21:19 +0200)]
PPC: Add some booke SPR defines
The number of SPRs avaiable in different PowerPC chip is still increasing. Add
definitions for the MAS7_MAS3 SPR and all currently known bits in EPCR.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 20 Jun 2012 18:58:27 +0000 (20:58 +0200)]
uImage: increase the gzip load size
Recent u-boot has different defines for its gzip extract buffer, but the
common ground seems to be 64MB. So let's bump it up to that, enabling me
to load my test image again ;).
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 20 Jun 2012 18:46:22 +0000 (20:46 +0200)]
PPC: e500: allow users to set the /compatible property via -machine
Device trees usually have a node /compatible, which indicate which machine
type we're looking at. For quick prototyping, it can be very useful to change
the contents of that node via the command line.
Thus, introduce a new option to -machine called dt_compatible, which when
set changes the /compatible contents to its value.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Wed, 20 Jun 2012 18:39:59 +0000 (20:39 +0200)]
dt: make setprop argument static
Whatever we pass in to qemu_devtree_setprop to put into the device tree
will not get modified by that function, so it can easily be declared const.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>
Alexander Graf [Tue, 5 Jun 2012 23:19:40 +0000 (01:19 +0200)]
PPC: e500: Refactor serial dt generation
When generating serial port device tree nodes, we duplicate quite a bit
of code, because there are 2 of them in the mpc8544ds board we emulate.
Shove the generating code into a function, so we duplicate less code.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Tue, 5 Jun 2012 23:01:23 +0000 (01:01 +0200)]
dt: Add global option to set phandle start offset
If anyone outside of QEMU wants to mess with a QEMU generated device tree,
he needs to know which range phandles are valid in. So let's expose a
machine option that an external program can use to set the start allocate
id for phandles in QEMU.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Tue, 5 Jun 2012 22:25:06 +0000 (00:25 +0200)]
PPC: e500: Extend address/size of / to 64bit
We want to be able to support >= 4GB of RAM. To do so, we need to be able
to tell the guest OS how much RAM it has.
However, that information today is capped to 32bit. So let's extend the
offset and size fields to 64bit, so we can fit in big addresses and even
one day - if we wish to do so - map devices above 32bit.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Tue, 5 Jun 2012 22:30:36 +0000 (00:30 +0200)]
PPC: e500: Define addresses as always 64bit
Every time we use an address constant, it needs to potentially fit into
a 64bit physical address space. So let's define things accordingly.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Tue, 5 Jun 2012 22:20:20 +0000 (00:20 +0200)]
PPC: e500: Use new SOC dt format
Due to popular demand, let's clean up the soc node a bit and use
more recent dt notions.
Requested-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Tue, 5 Jun 2012 22:14:34 +0000 (00:14 +0200)]
PPC: e500: Use new MPIC dt format
Due to popular demand, we're updating the way we generate the MPIC
node and interrupt lines based on what the current state of art is.
Requested-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 17 May 2012 23:45:01 +0000 (01:45 +0200)]
Revert "dt: temporarily disable subtree creation failure check"
This reverts commit "dt: temporarily disable subtree creation
failure check" which was meant as a temporary solution to keep
external and dynamic device tree construction intact.
Now that we switched to fully dynamic dt construction, it's no
longer necessary.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Tue, 22 May 2012 12:28:50 +0000 (14:28 +0200)]
PPC: e500: enable manual loading of dtb blob
We want to be able to override the automatically created device tree
by using the -dtb option. Implement this for the mpc8544ds machine.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Fri, 18 May 2012 00:14:46 +0000 (02:14 +0200)]
PPC: e500: dt: use target_phys_addr_t for ramsize
We're passing the ram size as uint32_t, capping it to 32 bits atm.
Change to target_phys_addr_t (uint64_t) to make sure we have all
the bits.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 17 May 2012 23:56:46 +0000 (01:56 +0200)]
PPC: e500: dt: use 64bit cell helper
We have a nice 64bit helper to ease the device tree generation and
make the code more readable when creating 64bit 2-cell parameters.
Use it when generating the device tree.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 17 May 2012 22:11:33 +0000 (00:11 +0200)]
dt: Add -machine dumpdtb option to dump the current dtb
Now that we are dynamically creating the dtb, it's really useful to
be able to dump the created blob for debugging.
This patch implements a -machine dumpdtb=<file> option for e500 that
dumps the dtb exactly in the form the guest would get it to disk. It
can then be analyzed by dtc to get information about the guest
configuration.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 17 May 2012 13:50:14 +0000 (15:50 +0200)]
PPC: e500: dt: start with empty device tree
Now that all of the device tree bits are generated during runtime, we
can get rid of the device tree blob and instead start from scratch with
an empty device tree.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 17 May 2012 13:34:34 +0000 (15:34 +0200)]
PPC: e500: dt: create pci node dynamically
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 17 May 2012 12:52:46 +0000 (14:52 +0200)]
PPC: e500: dt: create global-utils node dynamically
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 17 May 2012 12:51:51 +0000 (14:51 +0200)]
PPC: e500: dt: create mpic node dynamically
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 17 May 2012 12:51:34 +0000 (14:51 +0200)]
PPC: e500: dt: create serial nodes dynamically
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 17 May 2012 12:51:07 +0000 (14:51 +0200)]
PPC: e500: dt: create /soc8544 node dynamically
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 17 May 2012 12:49:20 +0000 (14:49 +0200)]
PPC: e500: dt: create /chosen node dynamically
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 17 May 2012 10:20:50 +0000 (12:20 +0200)]
PPC: e500: dt: create / node dynamically
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 17 May 2012 09:50:05 +0000 (11:50 +0200)]
PPC: e500: dt: create /hypervisor node dynamically
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 17 May 2012 09:48:16 +0000 (11:48 +0200)]
PPC: e500: dt: create /cpus node dynamically
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 17 May 2012 09:34:50 +0000 (11:34 +0200)]
PPC: e500: dt: create memory node dynamically
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 17 May 2012 10:23:41 +0000 (12:23 +0200)]
PPC: e500: require libfdt
Now that we're moving all of the device tree generation from an external
pre-execution generated blob to runtime generation using libfdt, we absolutely
must have libfdt around.
This requirement was there before already, as the only way to not require libfdt
with e500 was to not use -kernel, which was the only way to boot the mpc8544ds
machine. This patch only manifests said requirement in the build system.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 17 May 2012 23:53:01 +0000 (01:53 +0200)]
dt: add helper for 64bit cell adds
Some times in the device tree, we find an array of 2 u32 cells that
really are a single u64 value. This patch adds a helper to make the
creation of these easy.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>
Alexander Graf [Thu, 17 May 2012 14:58:55 +0000 (16:58 +0200)]
dt: add helper for phandle allocation
Phandle references work by having 2 pieces:
- a "phandle" 1-cell property in the device tree node
- a reference to the same value in a property we want to point
to the other node
To generate the 1-cell property, we need an allocation mechanism that
gives us a unique number space. This patch adds an allocator for these
properties.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 17 May 2012 13:33:54 +0000 (15:33 +0200)]
dt: add helper for empty dt creation
We want to get rid of the concept of loading an external device tree and instead
generate our own. However, to do this we need to also create a device tree
template programatically.
This patch adds a helper to create an empty device tree in memory.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>
Alexander Graf [Thu, 17 May 2012 13:23:39 +0000 (15:23 +0200)]
dt: add helper for phandle enumeration
This patch adds a helper to search for a node's phandle by its path. This
is especially useful when the phandle is part of an array, not just a single
cell in which case qemu_devtree_setprop_phandle would be the easy choice.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>
Alexander Graf [Thu, 17 May 2012 12:12:57 +0000 (14:12 +0200)]
dt: temporarily disable subtree creation failure check
Usually we want to know when creating a subtree fails. However, while
introducing this patch set we have to modify the device tree and some
times have the code to create a subtree in both the binary tree and
the dynamically created tree.
So ignore failures about this for now and enable them once we got rid
of the binary device tree.
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 17 May 2012 12:11:52 +0000 (14:11 +0200)]
dt: add helper for phandle references
Phandles are the fancy device tree name for "pointer to another node".
To create a phandle property, we most likely want to reference to the
node we're pointing to by its path. So create a helper that allows
us to do so.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>
Alexander Graf [Thu, 17 May 2012 10:47:57 +0000 (12:47 +0200)]
dt: add helpers for multi-cell adds
We have device tree helpers that allow us to create single cell (u32)
wide properties. However, when creating properties that contain an array of
cells, we need to jump through hoops, manually passing in an array with
converted endianness.
To ease the pain of this, create a generic macro helper that allows us
to pass the cells as arguments.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>
Alexander Graf [Thu, 17 May 2012 09:40:42 +0000 (11:40 +0200)]
dt: allow add_subnode to create root subnodes
Our subnode creation helper can't handle creation of root subnodes,
like "/memory". Fix this by allowing the parent node to be an empty
string, indicating the root node.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@petalogix.com>
Kevin Wolf [Tue, 19 Jun 2012 22:02:51 +0000 (22:02 +0000)]
raw-posix: Fix build without is_allocated support
Move the declaration of s into the #ifdef sections that actually make
use of it.
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Benjamin Herrenschmidt [Mon, 18 Jun 2012 20:21:37 +0000 (20:21 +0000)]
spapr: Add "memop" hypercall
This adds a qemu-specific hypervisor call to the pseries machine
which allows to do what amounts to memmove, memcpy and xor over
regions of physical memory such as the framebuffer.
This is the simplest way to get usable framebuffer speed from
SLOF since the framebuffer isn't mapped in the VRMA and so would
otherwise require an hcall per 8 bytes access.
The performance is still not great but usable, and can be improved
with a more complex implementation of the hcall itself if needed.
This also adds some documentation for the qemu-specific hypercalls
that we add to PAPR along with a new qemu,hypertas-functions property
that mirrors ibm,hypertas-functions and provides some discoverability
for the new calls.
Note: I chose note to advertise H_RTAS to the guest via that mechanism.
This is done on purpose, the guest uses the normal RTAS interfaces
provided by qemu (including SLOF) which internally calls H_RTAS.
We might in the future implement part (or even all) of RTAS inside the
guest like IBM's firmware does and replace H_RTAS with some finer grained
set of private hypercalls.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Benjamin Herrenschmidt [Mon, 18 Jun 2012 20:02:38 +0000 (20:02 +0000)]
spapr_vscsi: Error handling fixes
We were incorrectly g_free'ing an object that isn't allocated
in one error path and failed to release it completely in another
This fixes qemu crashes with some cases of IO errors.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Benjamin Herrenschmidt [Mon, 18 Jun 2012 19:56:30 +0000 (19:56 +0000)]
pseries: Correctly create ibm,segment-page-sizes property
The core tcg/kvm code for ppc64 now has at least the outline
capability to support pagesizes beyond the standard 4k and 16MB. The
CPUState is initialized with information advertising the available
pagesizes and their correct encodings, and under the right KVM setup
this will be populated with page sizes beyond the standard.
Obviously guests can't use the extra page sizes unless they know
they're present. For the pseries machine, at least, there is a
defined method for conveying exactly this information, the
"ibm-segment-page-sizes" property in the guest device tree.
This patch generates this property using the supported page size
information that's already in the CPUState.
Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Benjamin Herrenschmidt [Mon, 18 Jun 2012 19:56:25 +0000 (19:56 +0000)]
ppc64: Rudimentary Support for extra page sizes on server CPUs
More recent Power server chips (i.e. based on the 64 bit hash MMU)
support more than just the traditional 4k and 16M page sizes. This
can get quite complicated, because which page sizes are supported,
which combinations are supported within an MMU segment and how these
page sizes are encoded both in the SLB entry and the hash PTE can vary
depending on the CPU model (they are not specified by the
architecture). In addition the firmware or hypervisor may not permit
use of certain page sizes, for various reasons. Whether various page
sizes are supported on KVM, for example, depends on whether the PR or
HV variant of KVM is in use, and on the page size of the memory
backing the guest's RAM.
This patch adds information to the CPUState and cpu defs to describe
the supported page sizes and encodings. Since TCG does not yet
support any extended page sizes, we just set this to NULL in the
static CPU definitions, expanding this to the default 4k and 16M page
sizes when we initialize the cpu state. When using KVM, however, we
instead determine available page sizes using the new
KVM_PPC_GET_SMMU_INFO call. For old kernels without that call, we use
some defaults, with some guesswork which should do the right thing for
existing HV and PR implementations. The fallback might not be correct
for future versions, but that's ok, because they'll have
KVM_PPC_GET_SMMU_INFO.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
Fabien Chouteau [Mon, 21 May 2012 06:11:06 +0000 (06:11 +0000)]
booke_206_tlbwe: Discard invalid bits in MAS2
The size of EPN field in MAS2 depends on page size. This patch adds a
mask to discard invalid bits in EPN field.
Definition of EPN field from e500v2 RM:
EPN Effective page number: Depending on page size, only the bits
associated with a page boundary are valid. Bits that represent offsets
within a page are ignored and should be cleared.
There is a similar (but more complicated) definition in PowerISA V2.06.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Fabien Chouteau [Mon, 14 May 2012 23:39:09 +0000 (23:39 +0000)]
Avoid segfault in cpu_dump_state
Do not call cpu_dump_state if logfile is NULL.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
[agraf: adjust to inline functions]
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Fri, 18 May 2012 22:48:50 +0000 (00:48 +0200)]
PPC: mpc8544ds: Span initial TLB entry over as much RAM as we need
The initial TLB entry is supposed to help us run the guest -kernel payload.
This means the guest needs to be able to access its own memory, the initrd
memory and the device tree.
So far we only statically reserved a TLB entry from [0;256M[. This patch
fixes it to span from [0;dt_end[, allowing the guest payload to access
everything initially.
Reported-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:42 +0000 (04:23 +0000)]
ppc: Make hbrev table const
Lookup table 'hbrev' is never written to, so add a 'const' qualifier.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:41 +0000 (04:23 +0000)]
ppc: Add missing break
Add obviously missing 'break' statement.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:40 +0000 (04:23 +0000)]
ppc: Move load and store helpers, switch to AREG0 free mode
Add an explicit CPUPPCState parameter instead of relying on AREG0
and rename op_helper.c (which only contains load and store helpers)
to mem_helper.c. Remove AREG0 swapping in
tlb_fill().
Switch to AREG0 free mode. Use cpu_ld{l,uw}_code in translation
and interrupt handling, cpu_{ld,st}{l,uw}_data in loads and stores.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:39 +0000 (04:23 +0000)]
ppc: Move misc helpers from helper.c to misc_helper.c
Move more misc helpers from helper.c to misc_helper.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:38 +0000 (04:23 +0000)]
ppc: Avoid AREG0 for misc helpers
Add an explicit CPUPPCState parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:37 +0000 (04:23 +0000)]
ppc: Split off misc helpers
Move misc helpers from op_helper.c to misc_helpers.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:36 +0000 (04:23 +0000)]
ppc: Avoid AREG0 for timebase helpers
Add an explicit CPUPPCState parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:35 +0000 (04:23 +0000)]
ppc: Split off timebase helpers
Move decrementer and timebase helpers to a dedicated file.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:34 +0000 (04:23 +0000)]
ppc: Cleanup MMU merge
Remove useless wrappers. In some cases 'int' parameters are
changed to uint32_t.
Make internal functions static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
[agraf: fix kvm compilation]
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:33 +0000 (04:23 +0000)]
ppc: Move MMU helpers from helper.c to mmu_helper.c
Move more MMU helpers from helper.c to mmu_helper.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
[update to current helper.c state]
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:32 +0000 (04:23 +0000)]
ppc: Avoid a warning with the next patch
When the code is moved together by the next patch, compiler
detects a possible uninitialized variable use. Avoid the warning
by initializing the variables.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:31 +0000 (04:23 +0000)]
ppc: Avoid AREG0 for MMU etc. helpers
Add an explicit CPUPPCState parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:30 +0000 (04:23 +0000)]
ppc: Split MMU etc. helpers from op_helper.c
Move MMU, TLB, SLB and BAT ops to mmu_helper.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:29 +0000 (04:23 +0000)]
ppc: Avoid AREG0 for integer and vector helpers
Add an explicit CPUPPCState parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
[fix unwanted whitespace line in Makefile.target]
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:28 +0000 (04:23 +0000)]
ppc: Split integer and vector ops
Move integer and vector ops to int_helper.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:27 +0000 (04:23 +0000)]
ppc: Avoid AREG0 for FPU and SPE helpers
Add an explicit CPUPPCState parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:26 +0000 (04:23 +0000)]
ppc: Split FPU and SPE ops
Move FPU and SPE helpers from op_helper.c to fpu_helper.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:25 +0000 (04:23 +0000)]
ppc: Move exception helpers from helper.c to excp_helper.c
Move exception helpers from helper.c to excp_helper.c and
make cpu_dump_rfi() static.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:24 +0000 (04:23 +0000)]
ppc: Fix coding style in helper.c
helper.c will be spilt by the next patches, fix
style issues before that.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:23 +0000 (04:23 +0000)]
ppc: Avoid AREG0 for exception helpers
Add an explicit CPUPPCState parameter instead of relying on AREG0.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:22 +0000 (04:23 +0000)]
ppc: Split exception helpers
Move exception helpers from op_helper.c to excp_helper.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Wed, 30 May 2012 04:23:21 +0000 (04:23 +0000)]
ppc: Fix coding style in op_helper.c
op_helper.c will be split by the next patches, fix
style issues before that.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Sat, 23 Jun 2012 22:05:36 +0000 (00:05 +0200)]
TCG: Fix compile breakage in tcg_dump_ops
Commit
eeacee4d865 changed the syntax of tcg_dump_ops, but didn't convert
all users (notably missing the ppc ones) to it. Fix them to the new syntax.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: malc <av1474@comtv.ru>
Blue Swirl [Sun, 10 Jun 2012 10:18:54 +0000 (10:18 +0000)]
libcacard: build fixes
Link trace objects to fix these errors:
LINK vscclient
oslib-posix.o: In function `trace_qemu_vfree':
/src/qemu/obj-amd64/./trace.h:39: undefined reference to `trace1'
oslib-posix.o: In function `trace_qemu_memalign':
/src/qemu/obj-amd64/./trace.h:31: undefined reference to `trace3'
oslib-posix.o: In function `trace_qemu_vmalloc':
/src/qemu/obj-amd64/./trace.h:35: undefined reference to `trace2'
Add LDFLAGS to vscclient link command.
Clean up also in subdirectories of libcacard.
Use quiet-command for sed invocation.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Acked-by: Alon Levy <alevy@redhat.com>
Blue Swirl [Thu, 17 May 2012 18:55:58 +0000 (18:55 +0000)]
qtest: add a fuzz test to fdc-test
Add a simple register fuzzing test to floppy controller tests.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Blue Swirl [Sun, 3 Jun 2012 17:16:14 +0000 (17:16 +0000)]
fdc: use LOG_UNIMP logging
Convert uses of FLOPPY_ERROR to either FLOPPY_DPRINTF
(for implemented cases) or to use LOG_UNIMP (unimplemented).
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Blue Swirl [Sun, 3 Jun 2012 17:06:07 +0000 (17:06 +0000)]
qemu-log: use LOG_UNIMP for some target CPU cases
Use LOG_UNIMP for some target CPU cases.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Acked-by: Alexander Graf <agraf@suse.de>
Blue Swirl [Sun, 3 Jun 2012 17:04:28 +0000 (17:04 +0000)]
qemu-log: add log category for unimplemented functionality
Add new log category (LOG_UNIMP) for unimplemented functionality.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Blue Swirl [Sun, 3 Jun 2012 16:35:32 +0000 (16:35 +0000)]
qemu-log: cleanup
Don't use global variables directly but via accessor functions. Rename globals.
Convert macros to functions, add GCC format attributes.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Blue Swirl [Sun, 3 Jun 2012 15:03:23 +0000 (15:03 +0000)]
qemu-log: move logging to qemu-log.c
Move logging functions from exec.c to qemu-log.c,
compile it only once.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Peter A. G. Crosthwaite [Sat, 16 Jun 2012 05:20:59 +0000 (15:20 +1000)]
xilinx_timer: Fixed deadlock issue
The timer was deadlocking when the interval was set too low. It would cause a
flood of timer events and the CPU would halt indefinately. This is a known issue
and theres a generic workaround in place in ptimer on ptimer_set_limit(),
however the Xilinx timer uses ptimer_set_count() instead of set_limit. Changed
the call to set_count() to an equivalent call of set_limit() instead, which
brings the workaround into play.
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Peter A. G. Crosthwaite [Sat, 16 Jun 2012 05:20:58 +0000 (15:20 +1000)]
xilinx_timer: Removed include of qemu-timer
The Xilinx timer does not interact with the qemu_timer API, so dont include it.
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Peter Maydell [Wed, 20 Jun 2012 11:57:23 +0000 (11:57 +0000)]
target-arm: Remove ARM_CPUID_* macros
All the uses of ARM_CPUID() to vary behaviour have now been
removed, so we can delete the ARM_CPUID_* macros now.
The one exception is the TI915T/925T, because of its odd behaviour
where the MIDR value can be changed at runtime.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Peter Maydell [Wed, 20 Jun 2012 11:57:22 +0000 (11:57 +0000)]
target-arm: Remove remaining old cp15 infrastructure
There are now no uses of the old cp15 infrastructure,
so it can be deleted.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Wed, 20 Jun 2012 11:57:22 +0000 (11:57 +0000)]
target-arm: Move block cache ops to new cp15 framework
Move the v6 optional block cache ops to the new cp15 framework.
This includes only providing them on the CPUs which implemented
them, rather than the previous blunderbuss approach of making
all MCRR instructions on all CPUs act as NOPs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Wed, 20 Jun 2012 11:57:21 +0000 (11:57 +0000)]
target-arm: Remove c0_cachetype CPUARMState field
Remove the no-longer-used CPUARMState c0_cachetype field.
Although this was a constant register we had it in our
migration state. Drop this (with resulting version bump)
because for ARM currently we prefer cleaner migration
code and have not stabilised migration format yet.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Wed, 20 Jun 2012 11:57:20 +0000 (11:57 +0000)]
target-arm: Convert final ID registers
Convert the final ID registers to the new cp15 scheme.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Wed, 20 Jun 2012 11:57:20 +0000 (11:57 +0000)]
target-arm: Convert MPIDR
Convert the MPIDR to the new cp15 register scheme.
This includes giving it its own feature bit rather
than doing a CPUID value check.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Wed, 20 Jun 2012 11:57:19 +0000 (11:57 +0000)]
target-arm: Convert cp15 cache ID registers
Convert the cp15 cache ID registers to the new scheme.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Wed, 20 Jun 2012 11:57:19 +0000 (11:57 +0000)]
target-arm: Convert cp15 crn=0 crm={1,2} feature registers
Convert the cp15 crn=0 crm={1,2} features registers to
the new cp reg framework.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>