mesa: don't set CallList* redundantly in _mesa_initialize_save_table

It's set by _mesa_install_save_vtxfmt.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14000>

glapi: rename exec="dynamic" to exec "vtxfmt" to make it self-explanatory

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14000>

mesa: move the ES2 check from vbo_init_tmp.h to install_vtxfmt

It's where other API checks are done.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14000>

mesa: inline _vbo_install_exec_vtxfmt

also remove unused vbo_initialize_exec_dispatch

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14000>

mesa: move _mesa_initialize_vbo_vtxfmt calls to a common place and inline

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14000>

mesa: inline _mesa_install_dlist_vtxfmt

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14000>

mesa: inline _mesa_install_eval_vtxfmt

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14000>

mesa: inline _mesa_install_arrayelt_vtxfmt

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14000>

mesa: inline vbo_initialize_save_dispatch and rename the functions

_mesa_initialize_save_table will be autogenerated.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14000>

mesa: include less stuff in dlist.c

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14000>

virgl: Enable higher compatibility profiles if host supports it

v2: Update CI expectations

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12542>

ci: pin virglrenderer version

Currently we always just pull in whatever version of
virglrenderer happens to be TOT in googlesource.

Instead, pin a specific version, and this should also
trigger an update of the container when this versions
is changed.

v2: Fix spelling error (tomeu)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12542>

radv: have the null winsys set more fields

I copied stuff from ac_gpu_info.c until there were no Sienna Cichild or
Polaris10 fossil-db changes between real hardware and RADV_FORCE_FAMILY.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14126>

radv: Expose the ETC2 emulation.

As needed on Android (as it is required) and by driconf flag otherwise.
The non-Android case would be on the host side for an Android VM.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14071>

radv: Deal with border colors with emulated ETC2.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14071>

radv: Add ETC2 decode shader.

To make sure that apps actually get something when the HW doesn't
support ETC2. To do that we decompress after every copy operation.

Includes a quite complicated decode shader. It is not bit-to-bit
equivalent to AMD APUs that support ETC2, but close enough to
pass CTS. Likely missing bits are related to the R11 and R11G11
formats where we decode to 16 bits but likely do the extension
differently.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14071>

radv: Add extra plane for decoding ETC images with emulation.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14071>

radv: Use the correct base format for reintepretation.

Going to hit it when emulating ETC2 through another plane.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14071>

radv: Set up ETC2 emulation wiring.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14071>

v3d: Don't force SCANOUT for PIPE_BIND_SHARED requests

This was workaround for the users of gbm_bo_create_with_modifiers(),
which were unable to specify the buffer usage (GPU / GPU+DISPLAY).

But after the commit [1] this become possible. And forcing usage to
GBM_BO_USE_SCANOUT migrated directly into gbm_bo_create_with_modifiers
[2], allowing us to remove such workarounds from the drivers.

This makes possible to allocate the buffers in VRAM using
{gbm_bo_create_with_modifiers2 | gbm_bo_create} and providing correct
use flag thus saving CMA memory.

This should also enable tiling for such buffers.

[1]: 268e12c60534 ("gbm: add gbm_{bo,surface}_create_with_modifiers2")
[2]: ad50b47a14e9 ("gbm: assume USE_SCANOUT in create_with_modifiers")

Signed-off-by: Roman Stratiienko <roman.o.stratiienko@globallogic.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14151>

v3dv: Hotfix: Rename remaining V3DV_HAS_SURFACE->V3DV_USE_WSI_PLATFORM

This was somehow missed by me and during review.

Fixes fcfc4ddfccd5: ("v3dv: Fix V3DV_HAS_SURFACE preprocessor condition")

Signed-off-by: Roman Stratiienko <roman.o.stratiienko@globallogic.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14190>

broadcom/compiler: improve thrsw merge

Instead of stopping the merge process when we find an instruction
with an incompatible signal (such as an small immediate), keep
going and see if we can merge the thrsw in a previous instruction
that is compatible.

total instructions in shared programs: 13409835 -> 13356648 (-0.40%)
instructions in affected programs: 3556860 -> 3503673 (-1.50%)
helped: 17457
HURT: 18
Instructions are helped.

total max-temps in shared programs: 2353971 -> 2352956 (-0.04%)
max-temps in affected programs: 13960 -> 12945 (-7.27%)
helped: 703
HURT: 0
Max-temps are helped.

total spills in shared programs: 12301 -> 12301 (0.00%)
total sfu-stalls in shared programs: 32596 -> 32499 (-0.30%)
sfu-stalls in affected programs: 225 -> 128 (-43.11%)
helped: 79
HURT: 3
Sfu-stalls are helped.

total nops in shared programs: 347204 -> 325234 (-6.33%)
nops in affected programs: 99834 -> 77864 (-22.01%)
helped: 11515
HURT: 158
Nops are helped.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14172>

util/ra: use adjacency matrix for undirected graph

Since this graph is actually not oriented, its adjacency matrix can be
represented using less than half bits required by full adjacency matrix.
It reduces memory consumption and number of cache misses. It also simplifies
logic of growing this matrix - no need to touch adjacency bits for previously
allocated number of nodes.

Move adjacency bits from nodes to graph to reduce the number of allocations.

No changes to shader-db.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kostiantyn Lazukin <kostiantyn.lazukin@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14189>

lvp: Free the driver_data pointer for all commands

We were only freeing it for commands that had a struct as their
parameter, but all commands can have driver_data.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5715
Reported-by: Jose Fonseca <jfonsec@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14081>

nir: use call_once() to init debug variable

For data-race safety, let's use this function to ensure NIR debug is
initialized only once.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14057>

tgsi-to-nir: initialize NIR_DEBUG envvar

This envvar is initialized when creating a NIR shader, but it needs to
be used before. So initialize it here.

v2 (Juan):
 - Use static variable for first initialization.

Fixes: f77ccdfb4a2 ("nir: add NIR_DEBUG envvar")
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14057>

iris: Disable the SMEM fallback for CCS on XeHP

On XeHP, CCS is only supported in local memory.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14012>

iris: Rework the DEVICE_LOCAL heap

Split it into a local-only heap (which keeps the original enum) and a
local-preferred heap (which has a new enum).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14012>

iris: Add and use bucket_info_for_heap

Add a helper that maps a heap to the related cache bucket information.
This avoids complicating existing ternaries when new cache buckets are
added.

Rework:
 * Jordan: Add default and set pointers in default branch of
   bucket_info_for_heap to prevent "may be used uninitialized" warning
   in release builds.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14012>

iris: Add and use BUCKET_ARRAY_SIZE

This improves an assert in add_bucket.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14012>

iris: Replace "local" with "heap" in bufmgr fn params

We'll want to describe more than two placement options for BOs. Switch
to using the more flexible heap enum.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14012>

iris: Use a num_buckets pointer in add_bucket

Store a pointer to the appropriate cache bucket counter, then increment
the integer it points to. This keeps us from having to add code for
incrementing when a new cache bucket is added.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14012>

iris: Add and use flags_to_heap

Reduces duplicated calculations.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14012>

iris: Replace bo->real.local with bo->real.heap

We'll want to describe more than two placement options for BOs. Switch
to using the more flexible heap enum.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14012>

iris: Free the local cache bucket in bufmgr_destroy

Fixes: 55be94dcab4 ("iris/bufmgr: Add new set of buckets for local memory.")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14012>

venus: fix vn_buffer_get_max_buffer_size

The binary search can lead to infinite loop.  Fixes
dEQP-VK.api.object_management.alloc_callback_fail.device where
vn_CreateBuffer can always fail.

Fixes: a74f2495ca0 ("venus: implement vn_buffer_get_max_buffer_size")
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14184>

pan/mdg: Fix definition of UBO unpack

Needed to link the disassembler separate from the rest of the compiler,
as in out-of-tree pandecode builds. Which I haven't done for Midgard in
well over a year, enough time for this to bit rot.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14185>

intel/compiler: Assert that unsupported tg4 offsets were lowered for XeHP

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14142>

intel/compiler: Use nir_lower_tex_options::lower_offset_filter for tg4 on XeHP

Based on Rafael's:
 * "nir/lower_tex: Add option to lower offset for tg4 too."
 * "intel/compiler: Lower offsets for tg4 on gen9+."
 * "WIP: Do not lower basic offsets."
 * "WIP: intel/compiler: Enable lowering offsets restriction."

But, with these changes:
 * Fixed range checking to be signed 4 bits
 * Converted to filter
 * Apply only to gfx12.5+
 * Use nir_src_is_const / nir_src_comp_as_int (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14142>

nir/lower_tex: Add filter for tex offset lowering

Rework:
 * Add callback_data (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14142>

iris: Align buffer VMA to 2MiB for XeHP

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14155>

anv: Align buffer VMA to 2MiB for XeHP

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14155>

iris: Not all gfx12+ have aux_map_ctx

This code matches other similar cases in iris.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14152>

glapi: Never use dllimport/dllexport for TLS vars on Windows

Fixes: c691149f ("win32: Fixes thread local on win32 with clang/mingw")
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14162>

radv,aco: don't lower some ffma instructions

GFX10.3 has no v_mad_f32 and we can't recombine exact ffma into a
v_fma_f32 if they're split. GFX9+ only has v_fma_f16 and no generation has
a 64-bit MAD.

fossil-db (GFX10.3):
Totals from 84040 (57.46% of 146267) affected shaders:
VGPRs: 3717256 -> 3688064 (-0.79%); split: -0.87%, +0.08%
SpillSGPRs: 10419 -> 10403 (-0.15%)
CodeSize: 263064884 -> 262442820 (-0.24%); split: -0.31%, +0.07%
MaxWaves: 2036908 -> 2038374 (+0.07%); split: +0.10%, -0.03%
Instrs: 49849448 -> 49572182 (-0.56%); split: -0.60%, +0.04%
Latency: 908130602 -> 907764246 (-0.04%); split: -0.18%, +0.14%
InvThroughput: 207051300 -> 206762704 (-0.14%); split: -0.24%, +0.10%

fossil-db (GFX10):
Totals from 2 (0.00% of 146267) affected shaders:
Latency: 8123 -> 8107 (-0.20%)

fossil-db (GFX9):
Totals from 2 (0.00% of 146401) affected shaders:
(no statistics affected)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9805>

radv,aco: implement nir_op_ffma

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9805>

aco: swap multiplication operands if needed to create v_fmac_f32/etc

For v_pk_fma_f32 and v_fma_f32 from nir_op_ffma, we don't try to put
scalars in the first operand.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9805>

aco: swap operands if necessary to create v_madak/v_fmaak

Also rewrite the check_literal logic to be more straightforward.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9805>

aco: create v_fmamk_f32/v_fmaak_f32 from nir_op_ffma

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9805>

aco: use more predictable tiebreaker when forming MADs

fossil-db (GFX10.3):
Totals from 84981 (58.10% of 146267) affected shaders:
VGPRs: 3829896 -> 3820480 (-0.25%); split: -0.33%, +0.08%
CodeSize: 270860472 -> 270850132 (-0.00%); split: -0.08%, +0.08%
MaxWaves: 2035822 -> 2042516 (+0.33%); split: +0.39%, -0.06%
Instrs: 51285526 -> 51308869 (+0.05%); split: -0.03%, +0.08%
Latency: 931503706 -> 932556231 (+0.11%); split: -0.19%, +0.30%
InvThroughput: 217084232 -> 217070849 (-0.01%); split: -0.12%, +0.11%

fossil-db (GFX10):
Totals from 85520 (58.47% of 146267) affected shaders:
VGPRs: 3729132 -> 3725344 (-0.10%); split: -0.21%, +0.10%
CodeSize: 272796500 -> 272783084 (-0.00%); split: -0.09%, +0.08%
MaxWaves: 2246410 -> 2249012 (+0.12%); split: +0.17%, -0.05%
Instrs: 51643962 -> 51664865 (+0.04%); split: -0.04%, +0.08%
Latency: 932331949 -> 933274979 (+0.10%); split: -0.19%, +0.29%
InvThroughput: 214187040 -> 214130994 (-0.03%); split: -0.13%, +0.11%

fossil-db (GFX9):
Totals from 84619 (57.80% of 146401) affected shaders:
SGPRs: 5366240 -> 5366944 (+0.01%); split: -0.09%, +0.10%
VGPRs: 3765608 -> 3764972 (-0.02%); split: -0.23%, +0.22%
CodeSize: 263634732 -> 263616320 (-0.01%); split: -0.08%, +0.08%
MaxWaves: 546617 -> 547091 (+0.09%); split: +0.18%, -0.09%
Instrs: 51426195 -> 51458334 (+0.06%); split: -0.03%, +0.10%
Latency: 1164445660 -> 1161923480 (-0.22%); split: -0.46%, +0.24%
InvThroughput: 542964697 -> 542329595 (-0.12%); split: -0.26%, +0.14%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9805>

radv: ignore dynamic inheritance if the render pass isn't NULL

From the Vulkan spec:

    "If the pNext chain of VkCommandBufferInheritanceInfo includes a
     VkCommandBufferInheritanceRenderingInfoKHR structure, then that
     structure controls parameters of dynamic render pass instances
     that the VkCommandBuffer can be executed within. If
     VkCommandBufferInheritanceInfo::renderPass is not VK_NULL_HANDLE,
     or VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT is not
     specified in VkCommandBufferBeginInfo::flags, parameters of this
     structure are ignored."

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14109>

radv: fix dynamic rendering inheritance if the subpass index isn't 0

The driver will always create only one subpass in the render pass
for inheritance but the subpass index isn't always zero.

This fixes dEQP-VK.multiview.dynamic_rendering.secondary_cmd_buffer*.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14109>

radv: enable lower_lod_zero_width

This fixes dEQP-VK.glsl.texture_functions.query.texturequerylod.*.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14147>

nir/lower_tex: add lower_lod_zero_width

On AMD, the hardware will return 0 for the raw LOD if the sum of the
absolute values of derivatives is 0 but Vulkan expects the value to
be in the [-inf, -22.0f] range.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14147>

radeonsi: use max_zplanes after the last write

Fixes: c0f723ce2b8 ("radeonsi: allow and finish TC-compatible MSAA HTILE")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14089>

radeonsi: silence a warning

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14089>

radeonsi: fix fast clear / depth decompression corruption

Insert a flush after a depth decompression pass if the texture
was fast cleared.
This fixes a corruption which seems to only affect gfx10.3 chips.

Ideally we should also clear tex->need_flush_after_depth_decompression
after a flush but there's no easy way for this so this commit will
introduce extra flushes.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14089>

nir: limit lower_clip_cull_distance_arrays input to traditional stages

Compute, task, mesh & raytracing stages don't support
ClipDistance/CullDistance as input.

This change is not needed for correctness. Just something I stumbled on.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14149>

v3dv: Fix V3DV_HAS_SURFACE preprocessor condition

Currently V3DV_HAS_SURFACE is always defined.
There is no WSI for Android in mesa3d, therefore WSI related extensions
should not be exposed.

1. Define V3DV_HAS_SURFACE only for platforms which has WSI implemented.
2. Rename V3DV_HAS_SURFACE -> V3DV_USE_WSI_PLATFORM to align naming
with other platforms.

Fixes dEQP-VK.wsi.android.surface#query_protected_capabilities

Fixes: 79e445143054 ("v3dv: move extensions table to v3dv_device")
Signed-off-by: Roman Stratiienko <roman.o.stratiienko@globallogic.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14144>

intel/compiler: Use a struct for brw_compile_bs parameters

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14139>

intel/compiler: Use a struct for brw_compile_gs parameters

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14139>

intel/compiler: Use a struct for brw_compile_tes parameters

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14139>

intel/compiler: Use a struct for brw_compile_tcs parameters

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14139>

crocus: cleanup bo exports for external objects

This might have led to a leak in firefox/webrender/webgl scenarios

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: f3630548f1da ("crocus: initial gallium driver for Intel gfx 4-7")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14167>

radeonsi: unroll loops of up to 128 iterations

It's not exactly 128 because longer loop bodies scale the number down.

This improves perf for VP13/Creo and Piano. Most other tests either didn't
show any difference or are CPU-bound.

v2:
- The lowering passes had to be moved to the optimization loop because unrolling creates lowerable variables.
- Piano has some pattern that looks like corruption and the pattern changed with loop unrolling.
  The pattern is present on other drivers as well.

v3:
- I removed the Piano test from CI traces because the image is random. The output was wrong even before
  this MR, and now it's randomly wrong.

|   PERCENTAGE DELTAS    |  Shaders |    SGPRs |    VGPRs |SpillSGPR |SpillVGPR | PrivVGPR |  Scratch | CodeSize | MaxWaves |
|------------------------|----------|----------|----------|----------|----------|----------|----------|----------|----------|
| alien_isolation        |      2936|    .     |    0.02 %|    .     |    .     |    .     |    .     |    0.83 %|    .     |
| deadcore               |        76|   18.47 %|    .     |    .     |    .     |    .     |    .     |  167.69 %|    .     |
| deus_ex_mankind_div..  |      1410|    0.10 %|    0.15 %|    .     |    .     |    .     |    .     |    1.70 %|    .     |
| f1-2015                |       775|    0.37 %|    0.16 %|    .     |    .     |    .     |    .     |    3.25 %|   -0.07 %|
| hitman                 |      1413|    0.10 %|   -0.03 %|    6.45 %|    .     |    .     |    .     |    0.61 %|    0.03 %|
| metro_2033_redux       |      2670|    .     |    .     |    .     |    .     |    .     |    .     |    0.13 %|    0.01 %|
| pixmark-piano-0.7.0    |         2|    .     |   14.29 %| -100.00 %|    .     |    .     |    .     |   78.07 %|   -4.76 %|
| reflections_subway     |        98|   -0.53 %|    .     |    .     |    .     |    .     |    .     |    7.64 %|    .     |
| thea                   |       172|    0.12 %|   -0.81 %|    .     |    .     |    .     |    .     |    0.65 %|    0.15 %|
| ubershaders            |        54|    .     |    .     |    .     |    .     |    .     |    .     |   61.13 %|    .     |
| ue4_effects_cave       |       290|    0.05 %|    .     |    .     |    .     |    .     |    .     |    2.62 %|    .     |
| vp13-creo              |        26|   -3.38 %|   -4.20 %|    .     |    .     |    .     |    .     |   88.56 %|    2.62 %|
| vp13-sw                |       100|   -0.36 %|   -9.14 %|    .     | -100.00 %|    .     | -100.00 %|  -17.97 %|    0.39 %|
| vp20-creo              |        22|   -0.82 %|   -3.33 %|    .     |    .     |    .     |    .     |   81.59 %|    1.51 %|
| vp20-sw                |       296|   -4.51 %|   -0.63 %|    .     |    .     |    .     |    .     |   58.93 %|    0.20 %|
|------------------------|----------|----------|----------|----------|----------|----------|----------|----------|----------|
| All affected           |       189|    3.05 %|   -2.87 %|  500.00 %| -100.00 %|    .     | -100.00 %|  135.61 %|    1.32 %|
|------------------------|----------|----------|----------|----------|----------|----------|----------|----------|----------|
| Total                  |     57794|    0.01 %|   -0.02 %|    0.27 %|   -3.13 %|    .     |   -2.89 %|    1.73 %|    .     |

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>

radeonsi: add shader profiles that disable binning

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>

radeonsi: print more stats for shader-db

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>

radeonsi: add Wave32 heuristics and shader profiles

This generally works well.

There are new cases that select Wave32, and there are shader profiles
which adjust that.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>

glsl: fix setting compiled_source_sha1 without a shader cache

We need to set it even if Cache == NULL.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>

nir: add nir_has_divergent_loop function

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>

nir: serialize divergent fields

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>

nir: disable a NIR test due to undebuggable & locally unreproducible CI failures

debian-vulkan but not any other CI pipeline consistently fails with:
    FileNotFoundError: [Errno 2] No such file or directory: 'nir_tests.xml'

I have to assume that either debian-vulkan is broken, or the NIR test
infrastructure is broken. That's not all. I got the same failure when
I wanted to add a new test, which means the CI is preventing us from adding
new NIR tests, which is a very serious problem with the CI or NIR tests.
The python error doesn't imply that it's a test failure, so something else
is broken. If you don't want such commits to happen again, print better
error messages.

See also the discussion in the MR.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>

nir: handle more intrinsics in divergence analysis

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>

drisw: do an MSAA resolve when copying the backbuffer

When calling glXCopySubBuffer, we must resolve the backbuffer before
copying it the frontbuffer.

Fixes piglit's glx/glx-copy-sub-buffer on virgl.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11714>

virgl: flush cmd buffer when flushing frontbuffer

When a resource is multisampled, we usually submit a multisampling
resolving blit before we present it or use it in some other way, but
currently we don't always flush the cmd buffer before flushing the
frontbuffer, this commit fixes that.

Fixes piglit's glx/glx-copy-sub-buffer MSAA cases on vtest, in
conjunction with other commits of this series.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11714>

virgl/vtest: implement resource_create_front

This is required for glXCopySubBufferMESA to work.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11714>

virgl/vtest: use correct resource stride in flush_frontbuffer

The displaytarget's resource stride is alignment is currently 64-bytes,
where the shared resource stride is unaligned.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11714>

util: Use ralloc for strings in cache test

Also avoid warnings about asprintf result not being checked.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14054>

util: Convert cache test to use gtest

Replace a bunch of helper functions for checking results with ones
from GTest.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14054>

intel/dev: Add gtt_size to devinfo

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13647>

anv: Stop doing too much per-sample shading

We were setting anv_pipeline::sample_shading_enable based on
sampleShadingEnable without looking at minSampleShading.  We would then
pass this value into nir_lower_wpos_center which would add sample_pos to
frag_coord.  Then the back-end compiler picks up on the existence of
sample_pos and forces persample dispatch.  This leads to doing
per-sample dispatch whenever sampleShadingEnable = VK_TRUE regardless of
the value of minSampleShading.  This is almost certainly costing us
perf somewhere.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14022>

iris: Update the initial CCS state on XeHP

We can't map the CCS on this platform to initialize it into the
PASS_THROUGH state. This can cause issues with optimizations in the
driver that rely on this state.

For example, after rendering to a surface with AUX_NONE, we can then
render to it with AUX_CCS_E without an ambiguate in between (if the CCS
in the PASS_THROUGH state). If that state was incorrect and the aux was
actually compressed, there can be rendering corruption because the
contents may be misinterpreted on the second render.

Use a more accurate initial aux state to avoid these issues.

One notable change in behavior here is that aux surfaces can be created
with fast-cleared blocks even though the caller may specify a modifier
that doesn't support fast clears. This should be fine, so long as all HW
units that can access these surfaces can handle that bit-pattern. We
haven't seen an applicable restriction yet.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

iris: Modify the comment about zeroing CCS

Among other changes, we highlight the fact that we'll map the CCS -
something we can't do on XeHP.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

iris: Don't assert a NULL aux BO during aux config

The assert was introduced in a function that allocated an auxiliary
surface BO, iris_resource_alloc_aux. After refactors, the function it's
in now, iris_resource_configure_aux, no longer does this allocation.
Drop the assert because its purpose is unclear and it's no longer
relevant for CCS on XeHP.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

iris: Don't allocate and initialize CCS on XeHP

The memory for CCS on XeHP can't be mapped by the CPU.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

iris: Drop row pitch param from iris_get_ccs_surf

This parameter won't be used for XeHP, because we can't directly control
the row pitch of the CCS independently from the main surface.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

iris: Don't allocate a clear color BO for some Z/S

The only depth/stencil aux usage that can actually use the BO is
ISL_AUX_USAGE_HIZ_CCS_WT. Even with that aux usage, iris may disable
sampling depending on the surface configuration.

Allocate the clear color BO when it'd be usable, not just when the
auxiliary surface size is non-zero on ICL+. This prepares for CCS on
XeHP, which won't have an auxiliary surface.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

iris: Simplify iris_get_aux_clear_color_state_size

isl_dev.ss.clear_color_state_size is already zero on BDW and SKL. Drop
the redundant platform check and return the field directly.

We're going to have this function return zero more often and it will do
so uniformly using if-statements. We choose to remove the redundant
expression instead of adding a redundant if-statement.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

iris: Move some BO setup to iris_resource_init_aux_buf

To ease verification, place the assignment and reference of the aux BO
right before the same operations are done for the clear color BO. Also,
move the call to map_aux_addresses that's in the same if-block.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

iris: Use the aux BO and surf less during init

res->aux.bo and res->aux.surf will be NULL and zeroed, respectively, for
CCS on XeHP. Move and modify iris_resource_init_aux_buf to support this.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

iris: Change a param of iris_resource_init_aux_buf

Have iris_resource_init_aux_buf compute the clear color state size
(with an iris_screen struct) instead of passing it in directly.

We're going to move the function call soon. This keeps us from having to
move a passed in variable along with it.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

intel/blorp: Modify get_fast_clear_rect for XeHP

The alignment and scale down values have changed on this platform.

To support drivers that won't use a CCS surface on this platform, this
patch computes the CCS fast clear rectangle using the main surface.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

intel/blorp: Modify the SKL+ CCS resolve rectangle

According to Bspec 2424, "Render Target Resolve":

   The Resolve Rectangle size is same as Clear Rectangle size from SKL+.

Use get_fast_clear_rect in blorp_ccs_resolve for SKL+.

Note that the Bspec differs from Vol7 of the Sky Lake PRM, which only
specifies aligning by the scaledown factors.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

intel/isl: Require aux map for some 64K alignment

The comment states that 64K alignment of surfaces is required when an
aux map is present on the platform. However, the code checks for GFX12
instead of dev->info->has_aux_map. Update the code to match the comment.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

ci/windows: Remove line numbers from assertions in spirv2dxil tests

Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14156>

etnaviv: fix alpha blend with dither on older GPUs

While setting up DITHER_MODE allows alpha blending to work properly
together with dithering on new GPUs (those with PE_DITHER_FIX), older
cores still change the render target. As dithering is optional and
implementation defined we can simply disable it on the affected GPUs,
when alpha blending is enabled to work around this bug.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13396>

nir/nir_opt_move,sink: Include load_ubo_vec4 as a load_ubo instr.

We weren't doing much motion in nir-to-tgsi because we considered all our
lowered load-ubos as unmovable.

softpipe shader-db:

total temps in shared programs: 563942 -> 563136 (-0.14%)
temps in affected programs: 9833 -> 9027 (-8.20%)

r300 shader-db:

instructions in affected programs: 22858 -> 23575 (3.14%)
temps in affected programs: 2039 -> 1813 (-11.08%)

(NIR had given r300 -19% instrs for +40% temps, so this feels like a
worthwhile trade back).

Reivewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14138>

mesa: fix GL_MAX_SAMPLES with GLES2

EXT_multisampled_render_to_texture on GLES2 allows the
GL_MAX_SAMPLES_EXT enum to be used.

Move the condition from the GLES3 section to the GLES2 one so
that it stops returning GL_INVALID_ENUM in that case.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13967>

egl: add config debug printout

Feature to print out EGL returned configs for debug purposes.

'eglChooseConfig' and 'eglGetConfigs' debug information printout is
enabled when the log level equals '_EGL_DEBUG'. The configs are
printed, and if any of them are "chosen" they are marked with their
index in the chosen configs array.

v2:
   a) re-factor the code in line with review comments
   b) rename function _snprintfStrcat, split it out and put into the
      src/util/u_string.h, make it a separate patch.
v3:
   remove unnecessary 'const' qualifiers from the function prototype
v4:
   a) re-factor the code in line with review comments
   b) move util_strnappend from utils back to eglconfigdebug.c. In my
      opinion this function is the best way of achieving the desired
      result, so it still used but made private to eglconfigdebug.c.
v5:
   a) drop unused parameter from function signature
   b) more const annotations
   c) directly access config parameters instead of going
      through _eglGetConfigKey

Signed-off-by: Silvestrs Timofejevs <silvestrs.timofejevs@imgtec.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13705>

egl: introduce a log level getter function

Being able to retrieve the log level can be useful to enable/disable
debug code. The alternative, which is calling 'getenv' function every
time to retrieve the log level, is more "expensive".

Signed-off-by: Silvestrs Timofejevs <silvestrs.timofejevs@imgtec.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13705>