Krzysztof Kozlowski [Fri, 17 Feb 2023 15:58:37 +0000 (16:58 +0100)]
arm64: dts: qcom: sc7280-herobrine-audio-rt5682: add missing supplies
Bindings expect DBVDD-supply and LDO1-IN-supply:
sc7280-herobrine-evoker-lte.dtb: codec@1a: 'DBVDD-supply' is a required property
sc7280-herobrine-evoker-lte.dtb: codec@1a: 'LDO1-IN-supply' is a required property
In sc7180-trogdor.dtsi they come from the same regulator, so let's
assume intention was the same here.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230217155838.848403-2-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Fri, 17 Feb 2023 15:58:36 +0000 (16:58 +0100)]
arm64: dts: qcom: sc7180-trogdor-pazquel360: drop incorrect RT5682S VBAT-supply
It seems that the RT5682S codec does not use VBAT-supply:
sc7180-trogdor-pazquel360-lte.dtb: codec@1a: Unevaluated properties are not allowed ('VBAT-supply' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230217155838.848403-1-krzysztof.kozlowski@linaro.org
Kathiravan T [Fri, 17 Feb 2023 08:33:08 +0000 (14:03 +0530)]
arm64: dts: qcom: ipq5332: enable the CPUFreq support
Add the APCS, A53 PLL, cpu-opp-table nodes to bump the CPU frequency
above 800MHz.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230217083308.12017-6-quic_kathirav@quicinc.com
Johan Hovold [Tue, 21 Mar 2023 09:40:11 +0000 (10:40 +0100)]
arm64: dts: qcom: sc8280xp-x13s: add wifi calibration variant
Describe the bus topology for PCIe domain 6 and add the ath11k
calibration variant so that the board file (calibration data) can be
loaded.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=216246
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230321094011.9759-3-johan+linaro@kernel.org
Johan Hovold [Wed, 22 Mar 2023 11:33:18 +0000 (12:33 +0100)]
arm64: dts: qcom: sc8280xp-x13s: add hid 1.8V supplies
All the input devices use s10b as 1.8V supply.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230322113318.17908-7-johan+linaro@kernel.org
Johan Hovold [Wed, 22 Mar 2023 11:33:17 +0000 (12:33 +0100)]
arm64: dts: qcom: sc8280xp-x13s: add pmic regulator supplies
The s11b, s12b, s1c and bob supplies are used by several pmic
regulators. Add the missing description to the devicetree.
Note that there are still some consumers that are not (fully) described
in the devicetree so the supplies must remain marked as always-on for
now.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230322113318.17908-6-johan+linaro@kernel.org
Krzysztof Kozlowski [Wed, 8 Mar 2023 18:33:17 +0000 (19:33 +0100)]
arm64: dts: qcom: sm8450-hdk: align WCD9385 reset pin with downstream config
Downstream DTS uses 16 mA drive strength for the WCD9385 audio codec
RESET_N reset pin. It also pulls the pin down in shutdown mode, thus it
is more like a shutdown pin, not a reset. Use the same settings here
for HDK8450 and keep the WCD9385 by default in powered off (so pin as
low). Align the name of pin configuration node with other pins in the
DTS.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308183317.559253-2-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 8 Mar 2023 18:33:16 +0000 (19:33 +0100)]
arm64: dts: qcom: sm8450-hdk: use precise WCD9385 compatible
The HDK8450 uses WCD9385 audio codec, so use precise compatible, even
though WCD9380 and WCD9385 are both compatible.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308183317.559253-1-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 8 Mar 2023 14:27:12 +0000 (15:27 +0100)]
arm64: dts: qcom: sm8450-hdk: use recommended drive strength for speaker SD_N
Downstream DTS (and sc8280xp-lenovo-thinkpad-x13s with the same
speakers) uses 16 mA drive strength for the WSA8835 speaker SD_N
reset/shutdown pin. Use the same for HDK8450, as it is seem the
recommended value.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308142712.277659-1-krzysztof.kozlowski@linaro.org
Konrad Dybcio [Wed, 8 Mar 2023 01:27:05 +0000 (02:27 +0100)]
arm64: dts: qcom: sm8150: Add SoC-specific compatible to cpufreq_hw
Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308-topic-cpufreq_bindings-v1-8-3368473ec52d@linaro.org
Konrad Dybcio [Wed, 8 Mar 2023 01:27:04 +0000 (02:27 +0100)]
arm64: dts: qcom: sm6350: Add SoC-specific compatible to cpufreq_hw
Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308-topic-cpufreq_bindings-v1-7-3368473ec52d@linaro.org
Konrad Dybcio [Wed, 8 Mar 2023 01:27:03 +0000 (02:27 +0100)]
arm64: dts: qcom: sm6115: Add SoC-specific compatible to cpufreq_hw
Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308-topic-cpufreq_bindings-v1-6-3368473ec52d@linaro.org
Konrad Dybcio [Wed, 8 Mar 2023 01:27:02 +0000 (02:27 +0100)]
arm64: dts: qcom: sdm845: Add SoC-specific compatible to cpufreq_hw
Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308-topic-cpufreq_bindings-v1-5-3368473ec52d@linaro.org
Konrad Dybcio [Wed, 8 Mar 2023 01:27:01 +0000 (02:27 +0100)]
arm64: dts: qcom: sc7180: Add SoC-specific compatible to cpufreq_hw
Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308-topic-cpufreq_bindings-v1-4-3368473ec52d@linaro.org
Gergo Koteles [Mon, 6 Mar 2023 17:41:47 +0000 (18:41 +0100)]
arm64: dts: qcom: sdm845-oneplus-common: add Hall sensor
Enable the Hall effect sensor (flip cover) for OnePlus 6/6T.
The GPIO is mapped to SW_LID events as in msm8916, msm8994,
msm8998 devices.
Signed-off-by: Gergo Koteles <soyer@irl.hu>
Reviewed-by: Caleb Connolly <caleb@connolly.tech>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230306174147.185239-1-soyer@irl.hu
Krzysztof Kozlowski [Mon, 6 Mar 2023 08:14:30 +0000 (09:14 +0100)]
arm64: dts: qcom: drop redundant line breaks
Remove trailing, redundant line breaks.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230306081430.28491-2-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Mon, 6 Mar 2023 08:14:29 +0000 (09:14 +0100)]
arm64: dts: qcom: sdm845-db845c: drop empty node override
Drop empty override of pm8998_gpios.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230306081430.28491-1-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Sun, 5 Mar 2023 15:43:08 +0000 (16:43 +0100)]
arm64: dts: qcom: pm660: align thermal node names with bindings
Bindings expect thermal node names to end with '-thermal', so fix pm660
and pm660l:
sda660-inforce-ifc6560.dtb: thermal-zones: 'pm660', 'pm660l' do not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230305154308.241651-1-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Sat, 4 Mar 2023 13:03:15 +0000 (14:03 +0100)]
arm64: dts: qcom: sm8350-microsoft-surface: fix USB dual-role mode property
The "dr_mode" is a property of USB DWC3 node, not the Qualcomm wrapper
one:
sm8350-microsoft-surface-duo2.dtb: usb@a6f8800: 'dr_mode' does not match any of the regexes: '^usb@[0-9a-f]+$', 'pinctrl-[0-9]+'
Fixes:
c16160cfa565 ("arm64: dts: qcom: add minimal DTS for Microsoft Surface Duo 2")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230304130315.51595-2-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Sat, 4 Mar 2023 13:03:14 +0000 (14:03 +0100)]
arm64: dts: qcom: sm8250-xiaomi-elish: fix USB maximum speed property
Fix typo in USB DWC3 node maximum speed property.
Fixes:
a41b617530bf ("arm64: dts: qcom: sm8250: Add device tree for Xiaomi Mi Pad 5 Pro")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230304130315.51595-1-krzysztof.kozlowski@linaro.org
Bartosz Golaszewski [Thu, 9 Mar 2023 10:37:52 +0000 (11:37 +0100)]
arm64: dts: qcom: sa8775p-ride: enable the BT UART port
Enable the high-speed UART port connected to the Bluetooth controller on
the sa8775p-adp development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-10-brgl@bgdev.pl
Bartosz Golaszewski [Thu, 9 Mar 2023 10:37:51 +0000 (11:37 +0100)]
arm64: dts: qcom: sa8775p-ride: enable the GNSS UART port
Enable the high-speed UART port connected to the GNSS controller on the
sa8775p-adp development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-9-brgl@bgdev.pl
Bartosz Golaszewski [Thu, 9 Mar 2023 10:37:50 +0000 (11:37 +0100)]
arm64: dts: qcom: sa8775p: add high-speed UART nodes
Add two UART nodes that are known to be used by existing development
boards with this SoC.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-8-brgl@bgdev.pl
Bartosz Golaszewski [Thu, 9 Mar 2023 10:37:49 +0000 (11:37 +0100)]
arm64: dts: qcom: sa8775p-ride: enable the SPI node
Enable the SPI interface exposed on the sa8775p-ride development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-7-brgl@bgdev.pl
Bartosz Golaszewski [Thu, 9 Mar 2023 10:37:48 +0000 (11:37 +0100)]
arm64: dts: qcom: sa8775p: add the spi16 node
Add the SPI controller node for the interface exposed on the sa8775p-ride
development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-6-brgl@bgdev.pl
Bartosz Golaszewski [Thu, 9 Mar 2023 10:37:47 +0000 (11:37 +0100)]
arm64: dts: qcom: sa8775p-ride: enable i2c18
This enables the I2C interface on the sa8775p-ride development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-5-brgl@bgdev.pl
Bartosz Golaszewski [Thu, 9 Mar 2023 10:37:46 +0000 (11:37 +0100)]
arm64: dts: qcom: sa8775p: add the i2c18 node
Add a disabled node for the I2C interface that's exposed on the
sa8775p-ride development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-4-brgl@bgdev.pl
Bartosz Golaszewski [Thu, 9 Mar 2023 10:37:45 +0000 (11:37 +0100)]
arm64: dts: qcom: sa8775p-ride: enable QUPv3 #2
Enable the second instance of the QUPv3 engine on the sa8775p-ride board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-3-brgl@bgdev.pl
Bartosz Golaszewski [Thu, 9 Mar 2023 10:37:44 +0000 (11:37 +0100)]
arm64: dts: qcom: sa8775p: add the QUPv3 #2 node
Add the second instance of the QUPv3 engine to the sa8775p.dtsi.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-2-brgl@bgdev.pl
Danila Tikhonov [Tue, 21 Mar 2023 18:23:19 +0000 (21:23 +0300)]
arm64: dts: qcom: pm8150l: add spmi-flash-led node
Add a node describing the flash block found on pm8150l.
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230321182319.24958-1-danila@jiaxyga.com
Bhupesh Sharma [Tue, 21 Mar 2023 19:01:14 +0000 (00:31 +0530)]
arm64: dts: qcom: sdm845: Fix the BAM DMA engine compatible string
As per documentation, Qualcomm SDM845 SoC supports BAM DMA
engine v1.7.4, so use the correct compatible strings.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230321190118.3327360-2-bhupesh.sharma@linaro.org
Neil Armstrong [Tue, 21 Mar 2023 13:21:51 +0000 (14:21 +0100)]
arm64: dts: qcom: sm8550-mtp: add pmic glink node
Add the pmic glink node linked with the DWC3 USB controller
switched to OTG mode and tagged with usb-role-switch.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-11-552f3b721f9e@linaro.org
Neil Armstrong [Tue, 21 Mar 2023 13:21:50 +0000 (14:21 +0100)]
arm64: dts: qcom: sm8450-hdk: add pmic glink node
Add the pmic glink node linked with the DWC3 USB controller
switched to OTG mode and tagged with usb-role-switch.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-10-552f3b721f9e@linaro.org
Neil Armstrong [Tue, 21 Mar 2023 13:21:49 +0000 (14:21 +0100)]
arm64: dts: qcom: sm8350-hdk: add pmic glink node
Add the pmic glink node linked with the DWC3 USB controller
switched to OTG mode and tagged with usb-role-switch.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-9-552f3b721f9e@linaro.org
Neil Armstrong [Tue, 21 Mar 2023 13:21:48 +0000 (14:21 +0100)]
arm64: dts: qcom: sm8550: add port subnodes in dwc3 node
Add ports subnodes in dwc3 node to avoid repeating the
same description in each board DT.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-8-552f3b721f9e@linaro.org
Neil Armstrong [Tue, 21 Mar 2023 13:21:47 +0000 (14:21 +0100)]
arm64: dts: qcom: sm8450: add port subnodes in dwc3 node
Add ports subnodes in dwc3 node to avoid repeating the
same description in each board DT.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-7-552f3b721f9e@linaro.org
Neil Armstrong [Tue, 21 Mar 2023 13:21:46 +0000 (14:21 +0100)]
arm64: dts: qcom: sm8350: add port subnodes in dwc3 node
Add ports subnodes in dwc3 node to avoid repeating the
same description in each board DT.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-6-552f3b721f9e@linaro.org
Bhupesh Sharma [Tue, 14 Mar 2023 07:40:01 +0000 (13:10 +0530)]
arm64: dts: qcom: sm6115: Move SDHC node(s)'s 'pinctrl' properties to dts
Normally the 'pinctrl' properties of a SDHC controller and the
chip detect pin settings are dependent on the type of the slots
(for e.g uSD card slot), regulators and GPIO(s) available on the
board(s).
So, move the same from the sm6115 dtsi file to the respective
board file(s).
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314074001.1873781-1-bhupesh.sharma@linaro.org
Bhupesh Sharma [Tue, 14 Mar 2023 08:36:33 +0000 (14:06 +0530)]
arm64: dts: qcom: sm6115: Move USB node's 'maximum-speed' and 'dr_mode' properties to dts
Normally the 'maximum-speed' and 'dr_mode' properties
of a USB controller + port is dependent on the type of
the ports, regulators and mode change interrupt routing
available on the board(s).
So, move the same from the sm6115 dtsi file to respective
board file(s).
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314083633.1882214-3-bhupesh.sharma@linaro.org
Bhupesh Sharma [Tue, 14 Mar 2023 08:36:32 +0000 (14:06 +0530)]
arm64: dts: qcom: sm6115: Cleanup USB node's label
There is only one USB controller present on SM6115 / SM4250
Qualcomm SoC, so drop the numbering used with USB node's label
names in the dtsi and the related sm4250-oneplus-billie2.dts.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314083633.1882214-2-bhupesh.sharma@linaro.org
Johan Hovold [Thu, 16 Mar 2023 14:12:52 +0000 (15:12 +0100)]
arm64: dts: qcom: sc8280xp: fix external display power domain
Fix the external display controller nodes which erroneously described
the controllers as belonging to CX rather than MMCX.
Fixes:
19d3bb90754f ("arm64: dts: qcom: sc8280xp: Add USB-C-related DP blocks")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230316141252.2436-1-johan+linaro@kernel.org
Stephan Gerhold [Wed, 8 Mar 2023 12:36:17 +0000 (13:36 +0100)]
arm64: dts: qcom: msm8916: Fix tsens_mode unit address
The reg address of the tsens_mode nvmem cell is correct but the unit
address does not match (0xec vs 0xef). Fix it. No functional change.
Fixes:
24aafd041fb2 ("arm64: dts: qcom: msm8916: specify per-sensor calibration cells")
Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308123617.101211-1-stephan.gerhold@kernkonzept.com
Neil Armstrong [Wed, 8 Mar 2023 08:32:54 +0000 (09:32 +0100)]
arm64: dts: qcom: sm8550: misc style fixes
Miscellaneous DT fixes to remove spurious blank line and enhance readability.
Fixes:
ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi")
Fixes:
d7da51db5b81 ("arm64: dts: qcom: sm8550: add display hardware devices")
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308-topic-sm8550-upstream-dt-fixups-v1-3-595b02067672@linaro.org
Neil Armstrong [Wed, 8 Mar 2023 08:32:53 +0000 (09:32 +0100)]
arm64: dts: qcom: sm8550: fix qup_spi0_cs node
The node is incomplete and doesn't need a subnode, add the missing
properties and move everything to the root of qup-spi0-cs-state node.
Fixes:
ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi")
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308-topic-sm8550-upstream-dt-fixups-v1-2-595b02067672@linaro.org
Krzysztof Kozlowski [Sat, 4 Mar 2023 12:33:58 +0000 (13:33 +0100)]
arm64: dts: qcom: sm8250-xiaomi-elish: correct GPIO keys wakeup
gpio-keys,wakeup is a deprecated property:
sm8250-xiaomi-elish.dtb: gpio-keys: key-vol-up: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230304123358.34274-8-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Sat, 4 Mar 2023 12:33:57 +0000 (13:33 +0100)]
arm64: dts: qcom: sm8250-sony-xperia: correct GPIO keys wakeup
gpio-keys,wakeup is a deprecated property:
sm8250-sony-xperia-edo-pdx206.dtb: gpio-keys: key-vol-down: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230304123358.34274-7-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Sat, 4 Mar 2023 12:33:56 +0000 (13:33 +0100)]
arm64: dts: qcom: sm6115p-lenovo-j606f: correct GPIO keys wakeup
gpio-keys,wakeup is a deprecated property:
sm6115p-lenovo-j606f.dtb: gpio-keys: key-volume-up: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230304123358.34274-6-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Sat, 4 Mar 2023 12:33:55 +0000 (13:33 +0100)]
arm64: dts: qcom: sdm630-sony-xperia: correct GPIO keys wakeup
gpio-keys,wakeup is a deprecated property:
sdm630-sony-xperia-nile-voyager.dtb: gpio-keys: key-vol-down: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230304123358.34274-5-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Sat, 4 Mar 2023 12:33:54 +0000 (13:33 +0100)]
arm64: dts: qcom: sc7280-idp: correct GPIO keys wakeup
gpio-keys,wakeup is a deprecated property:
sc7280-idp.dtb: gpio-keys: key-volume-up: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230304123358.34274-4-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Sat, 4 Mar 2023 12:33:53 +0000 (13:33 +0100)]
arm64: dts: qcom: msm8998-sony-xperia: correct GPIO keys wakeup
gpio-keys,wakeup is a deprecated property:
msm8998-sony-xperia-yoshino-lilac.dtb: gpio-keys: button-vol-down: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230304123358.34274-3-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Sat, 4 Mar 2023 12:33:52 +0000 (13:33 +0100)]
arm64: dts: qcom: msm8998-fxtec: correct GPIO keys wakeup
gpio-keys,wakeup is a deprecated property:
msm8998-fxtec-pro1.dtb: gpio-hall-sensors: event-hall-sensor1: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230304123358.34274-2-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Sat, 4 Mar 2023 12:33:51 +0000 (13:33 +0100)]
arm64: dts: qcom: sm8150-kumano: correct GPIO keys wakeup
gpio-keys,wakeup is a deprecated property:
sm8150-sony-xperia-kumano-bahamut.dtb: gpio-keys: key-camera-focus: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230304123358.34274-1-krzysztof.kozlowski@linaro.org
Douglas Anderson [Thu, 2 Mar 2023 21:11:07 +0000 (13:11 -0800)]
arm64: dts: qcom: sc7180: Delete mrbland
The mrbland board was never actually produced and there has been no
activity around the board for quite some time. It seems highly
unlikely to magically get revived. There should be nobody in need of
these device trees, so let's delete them. If somehow the project
resurrects itself then we can re-add support, perhaps just for -rev1+.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230302131031.v2.4.I79eee3b8e9eb3086ae02760e97a2e12ffa8eb4f0@changeid
Douglas Anderson [Thu, 2 Mar 2023 21:11:06 +0000 (13:11 -0800)]
arm64: dts: qcom: sc7180: Delete lazor-rev0
lazor-rev0 was a pile of parts. While I kept the pile of parts for
lazor running on my desk for longer than I usually do, those days are
still long past. Let's finally delete support for lazor-rev0.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230302131031.v2.3.I30128a6f4b60b096770186430036afb40ede6f70@changeid
Douglas Anderson [Thu, 2 Mar 2023 21:11:05 +0000 (13:11 -0800)]
arm64: dts: qcom: sc7180: Delete kingoftown-rev0
The earliest kingoftown that I could find in my pile of boards was
-rev2 and even that revision looks pretty rough (plastics on the case
are very unfinished). Though I don't actually have details about how
many -rev0 devices were produced, I can't imagine anyone still using
one. Let's delete support.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230302131031.v2.2.I68cbe5d5d45074428469da8c52f1d6a78bdc62fc@changeid
Douglas Anderson [Thu, 2 Mar 2023 21:11:04 +0000 (13:11 -0800)]
arm64: dts: qcom: sc7180: Delete wormdingler-rev0
The earliest wormdingler I could find in my pile of hardware is
-rev1. I believe that -rev0 boards were just distributed as a pile of
components with no case. At this point I can't imagine anyone needing
to make wormdingler-rev0 work, so let's delete support for it.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230302131031.v2.1.Id0cd5120469eb200118c0c7b8ee8209f877767b4@changeid
Adam Skladowski [Thu, 2 Mar 2023 12:30:49 +0000 (13:30 +0100)]
arm64: dts: qcom: msm8976: Add and provide xo clk to rpmcc
In order for consumers of RPMCC XO clock to probe successfully
their parent needs to be feed with reference clock to obtain proper rate,
add fixed xo-board clock and supply it to rpmcc to make consumers happy.
Frequency setting is left per board basis just like on other recent trees.
Fixes:
0484d3ce0902 ("arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs")
Fixes:
ff7f6d34ca07 ("arm64: dts: qcom: Add support for SONY Xperia X/X Compact")
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
[bjorn: Squashed the two patches]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230302123051.12440-1-a39.skl@gmail.com
Link: https://lore.kernel.org/r/20230302123051.12440-2-a39.skl@gmail.com
Manivannan Sadhasivam [Tue, 28 Feb 2023 16:47:49 +0000 (22:17 +0530)]
arm64: dts: qcom: sm8350: Fix the PCI I/O port range
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x60200000, 0x40200000) specified in the ranges property for I/O region.
While at it, let's use the missing 0x prefix for the addresses.
Fixes:
6daee40678a0 ("arm64: dts: qcom: sm8350: add PCIe devices")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230228164752.55682-14-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 28 Feb 2023 16:47:48 +0000 (22:17 +0530)]
arm64: dts: qcom: sm8450: Fix the PCI I/O port range
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x60200000, 0x40200000) specified in the ranges property for I/O region.
While at it, let's use the missing 0x prefix for the addresses.
Fixes:
bc6588bc25fb ("arm64: dts: qcom: sm8450: add PCIe1 root device")
Fixes:
7b09b1b47335 ("arm64: dts: qcom: sm8450: add PCIe0 RC device")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230228164752.55682-13-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 28 Feb 2023 16:47:47 +0000 (22:17 +0530)]
arm64: dts: qcom: sm8150: Fix the PCI I/O port range
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x60200000, 0x40200000) specified in the ranges property for I/O region.
While at it, let's use the missing 0x prefix for the addresses.
Fixes:
a1c86c680533 ("arm64: dts: qcom: sm8150: Add PCIe nodes")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230228164752.55682-12-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 28 Feb 2023 16:47:46 +0000 (22:17 +0530)]
arm64: dts: qcom: sc8280xp: Fix the PCI I/O port range
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x30200000, 0x32200000, 0x34200000, 0x38200000, 0x3c200000) specified in
the ranges property for I/O region.
Fixes:
813e83157001 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230228164752.55682-11-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 28 Feb 2023 16:47:45 +0000 (22:17 +0530)]
arm64: dts: qcom: qcs404: Use 0x prefix for the PCI I/O and MEM ranges
To maintain the uniformity, let's use the 0x prefix for the values of
ranges property.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230228164752.55682-10-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 28 Feb 2023 16:47:44 +0000 (22:17 +0530)]
arm64: dts: qcom: sm8250: Fix the PCI I/O port range
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x60200000, 0x40200000, 0x64200000) specified in the ranges property for
I/O region.
While at it, let's use the missing 0x prefix for the addresses.
Fixes:
e53bdfc00977 ("arm64: dts: qcom: sm8250: Add PCIe support")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230228164752.55682-9-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 28 Feb 2023 16:47:43 +0000 (22:17 +0530)]
arm64: dts: qcom: msm8996: Fix the PCI I/O port range
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x0c200000, 0x0d200000, 0x0e200000) specified in the ranges property for
I/O region.
While at it, let's also align the entries.
Fixes:
ed965ef89227 ("arm64: dts: qcom: msm8996: add support to pcie")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230228164752.55682-8-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 28 Feb 2023 16:47:42 +0000 (22:17 +0530)]
arm64: dts: qcom: ipq6018: Fix the PCI I/O port range
For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI address
(0x20200000) specified in the ranges property for I/O region.
While at it, let's use the missing 0x prefix for the addresses.
Fixes:
095bbdd9a5c3 ("arm64: dts: qcom: ipq6018: Add pcie support")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230228164752.55682-7-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 28 Feb 2023 16:47:41 +0000 (22:17 +0530)]
arm64: dts: qcom: ipq8074: Fix the PCI I/O port range
For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI addresses
(0x10200000, 0x20200000) specified in the ranges property for I/O region.
While at it, let's use the missing 0x prefix for the addresses and align
them in a single line.
Fixes:
33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230228164752.55682-6-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 28 Feb 2023 16:47:40 +0000 (22:17 +0530)]
arm64: dts: qcom: sm8550: Fix the PCI I/O port range
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x60200000, 0x40200000) specified in the ranges property for I/O region.
While at it, let's use the missing 0x prefix for the addresses.
Fixes:
7d1158c984d3 ("arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230228164752.55682-5-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 28 Feb 2023 16:47:39 +0000 (22:17 +0530)]
arm64: dts: qcom: sc7280: Fix the PCI I/O port range
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI address
(0x40200000) specified in the ranges property for I/O region.
Fixes:
92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230228164752.55682-4-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 28 Feb 2023 16:47:38 +0000 (22:17 +0530)]
arm64: dts: qcom: msm8998: Fix the PCI I/O port range
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI address
(0x1b200000) specified in the ranges property for I/O region.
Fixes:
b84dfd175c09 ("arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230228164752.55682-3-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 28 Feb 2023 16:47:37 +0000 (22:17 +0530)]
arm64: dts: qcom: sdm845: Fix the PCI I/O port range
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are
located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses
(0x60200000, 0x40200000) specified in the ranges property for I/O region.
While at it, let's use the missing 0x prefix for the addresses.
Fixes:
42ad231338c1 ("arm64: dts: qcom: sdm845: Add second PCIe PHY and controller")
Fixes:
5c538e09cb19 ("arm64: dts: qcom: sdm845: Add first PCIe controller and PHY")
Reported-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230228164752.55682-2-manivannan.sadhasivam@linaro.org
Konrad Dybcio [Fri, 24 Feb 2023 13:07:58 +0000 (14:07 +0100)]
arm64: dts: qcom: sc8280xp: Use correct CPU compatibles
Cores 0-3 are CA78C r0p0, cores 4-7 are CX1C r0p0. Use the correct
compatibles instead of the placeholder qcom,kryo.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230224130759.45579-2-konrad.dybcio@linaro.org
Mao Jinlong [Tue, 17 Jan 2023 14:57:08 +0000 (06:57 -0800)]
arm64: dts: qcom: sm8250: Add tpdm mm/prng
Add tpdm mm and tpdm prng for sm8250.
+---------------+ +-------------+
| tpdm@6c08000 | |tpdm@684C000 |
+-------|-------+ +------|------+
| |
+-------|-------+ |
| funnel@6c0b000| |
+-------|-------+ |
| |
+-------|-------+ |
|funnel@6c2d000 | |
+-------|-------+ |
| |
| +---------------+ |
+----- tpda@6004000 -----------+
+-------|-------+
|
+-------|-------+
|funnel@6005000 |
+---------------+
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230117145708.16739-10-quic_jinlmao@quicinc.com
Vincent Guittot [Fri, 6 Jan 2023 16:46:18 +0000 (17:46 +0100)]
arm64: dts: qcom: sdm845: correct dynamic power coefficients
While stressing EAS on my dragonboard RB3, I have noticed that LITTLE cores
where never selected as the most energy efficient CPU whatever the
utilization level of waking task.
energy model framework uses its cost field to estimate the energy with
the formula:
nrg = cost of the selected OPP * utilization / CPU's max capacity
which ends up selecting the CPU with lowest cost / max capacity ration
as long as the utilization fits in the OPP's capacity.
If we compare the cost of a little OPP with similar capacity of a big OPP
like :
OPP(kHz) OPP capacity cost max capacity cost/max capacity
LITTLE 1766400 407 351114 407 863
big 1056000 408 520267 1024 508
This can be interpreted as the LITTLE core consumes 70% more than big core
for the same compute capacity.
According to [1], LITTLE consumes 10% less than big core for Coremark
benchmark at those OPPs. If we consider that everything else stays
unchanged, the dynamic-power-coefficient of LITTLE core should be
only 53% of the current value: 290 * 53% = 154
Set the dynamic-power-coefficient of CPU0-3 to 154 to fix the energy model.
[1] https://github.com/kdrag0n/freqbench/tree/master/results/sdm845/main
Fixes:
0e0a8e35d725 ("arm64: dts: qcom: sdm845: correct dynamic power coefficients")
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106164618.1845281-1-vincent.guittot@linaro.org
Kathiravan T [Fri, 10 Feb 2023 06:04:01 +0000 (11:34 +0530)]
arm64: dts: qcom: ipq5332: add SMEM support
Add SMEM support by adding required nodes.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230210060401.24383-3-quic_kathirav@quicinc.com
Kathiravan T [Fri, 10 Feb 2023 06:04:00 +0000 (11:34 +0530)]
arm64: dts: qcom: ipq5332: enable the download mode support
Enable the support for download mode to collect the RAM dumps if
system crashes, to perform the post mortem analysis.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230210060401.24383-2-quic_kathirav@quicinc.com
Kathiravan T [Tue, 7 Mar 2023 06:22:31 +0000 (11:52 +0530)]
arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support
Add initial device tree support for the Qualcomm IPQ5332 SoC and
MI01.2 board.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230307062232.4889-9-quic_kathirav@quicinc.com
Krzysztof Kozlowski [Wed, 8 Mar 2023 12:59:06 +0000 (13:59 +0100)]
arm64: dts: qcom: msm8996-oneplus: do not enable incomplete nodes
status=okay should appear in final place where all required properties
are provided, because that makes the code the easiest to read. Move the
status from common OnePlus DTSI to board DTS. No functional changes.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-11-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 8 Mar 2023 12:59:05 +0000 (13:59 +0100)]
arm64: dts: qcom: sc7280: fix EUD port properties
Nodes with unit addresses must have also 'reg' property:
sc7280-herobrine-crd.dtb: eud@88e0000: ports:port@0: 'reg' is a required property
Fixes:
0b059979090d ("arm64: dts: qcom: sc7280: Add EUD dt node and dwc3 connector")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-10-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 8 Mar 2023 12:59:04 +0000 (13:59 +0100)]
arm64: dts: qcom: msm8994: correct RPMCC node name
The bindings expect RPM clock controller subnode to be named
'clock-controller':
apq8094-sony-xperia-kitakami-karin_windy.dtb: smd: rpm:rpm-requests: 'rpmcc' does not match any of the regexes: '^regulators(-[01])?$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-9-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 8 Mar 2023 12:59:03 +0000 (13:59 +0100)]
arm64: dts: qcom: msm8953: drop clocks from RPMPD
The RPM power domain controller does not take XO clock as input
(according to bindings and Linux driver):
msm8953-xiaomi-vince.dtb: rpm-requests: power-controller: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-8-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 8 Mar 2023 12:59:02 +0000 (13:59 +0100)]
arm64: dts: qcom: msm8953: correct RPMCC node name
The bindings expect RPM clock controller subnode to be named
'clock-controller':
msm8953-motorola-potter.dtb: smd: rpm:rpm-requests: 'rpmcc' does not match any of the regexes: '^regulators(-[01])?$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-7-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 8 Mar 2023 12:59:01 +0000 (13:59 +0100)]
arm64: dts: qcom: ipq6018-cp01-c1: drop SPI cs-select
The SPI controller nodes do not use/allow cs-select property:
ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('cs-select' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-6-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 8 Mar 2023 12:59:00 +0000 (13:59 +0100)]
arm64: dts: qcom: apq8096-db820c: drop SPI label
The SPI controller nodes do not use/allow label property:
apq8096-db820c.dtb: spi@7575000: Unevaluated properties are not allowed ('label' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-5-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 8 Mar 2023 12:58:59 +0000 (13:58 +0100)]
arm64: dts: qcom: sdm845-db845c: drop SPI label
The SPI controller nodes do not use/allow label property:
sdm845-db845c.dtb: spi@888000: Unevaluated properties are not allowed ('label' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-4-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 8 Mar 2023 12:58:58 +0000 (13:58 +0100)]
arm64: dts: qcom: qdu1000: drop incorrect serial properties
The serial node does not use/allow address/size cells:
qdu1000-idp.dtb: geniqup@9c0000: serial@99c000: Unevaluated properties are not allowed ('#address-cells', '#size-cells' were unexpected)
Fixes:
6bd20c54b589 ("arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-3-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 8 Mar 2023 12:58:57 +0000 (13:58 +0100)]
arm64: dts: qcom: sm8250: drop incorrect Coresight funnel properties
There is only one output port, thus out-ports should not have
'address/size-cells' and unit addresses. 'reg-names' are also not
allowed by bindings.
qrb5165-rb5.dtb: funnel@6042000: out-ports: '#address-cells', '#size-cells', 'port@0' do not match any of the regexes: 'pinctrl-[0-9]+'
qrb5165-rb5.dtb: funnel@6b04000: Unevaluated properties are not allowed ('reg-names' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-2-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Wed, 8 Mar 2023 12:58:56 +0000 (13:58 +0100)]
arm64: dts: qcom: drop incorrect cell-index from SPMI
The SPMI controller (PMIC Arbiter)) does not use nor allow 'cell-index'
property:
sm8150-microsoft-surface-duo.dtb: spmi@c440000: Unevaluated properties are not allowed ('cell-index' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308125906.236885-1-krzysztof.kozlowski@linaro.org
Bartosz Golaszewski [Wed, 15 Mar 2023 20:27:51 +0000 (21:27 +0100)]
arm64: dts: qcom: sm8150: fix the uart9 label
There's a typo in the @<address> part of the uart9 label. Fix it.
Fixes:
10d900a834da ("arm64: dts: sm8150: add the QUPv3 high-speed UART node")
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230315202751.1518543-1-brgl@bgdev.pl
Manivannan Sadhasivam [Tue, 14 Mar 2023 08:04:40 +0000 (13:34 +0530)]
arm64: dts: qcom: sm6350: Fix the base addresses of LLCC banks
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.
On SM6350, there is only one LLCC bank available. So let's just pass that
as "llcc0_base".
Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Tested-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-12-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 14 Mar 2023 08:04:39 +0000 (13:34 +0530)]
arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.
Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-11-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 14 Mar 2023 08:04:38 +0000 (13:34 +0530)]
arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.
Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-10-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 14 Mar 2023 08:04:37 +0000 (13:34 +0530)]
arm64: dts: qcom: sm8250: Fix the base addresses of LLCC banks
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.
Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-9-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 14 Mar 2023 08:04:36 +0000 (13:34 +0530)]
arm64: dts: qcom: sm8150: Fix the base addresses of LLCC banks
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.
Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-8-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 14 Mar 2023 08:04:35 +0000 (13:34 +0530)]
arm64: dts: qcom: sc8280xp: Fix the base addresses of LLCC banks
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.
Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s
Tested-by: Andrew Halaney <ahalaney@redhat.com> # sa8540p-ride
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-7-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 14 Mar 2023 08:04:34 +0000 (13:34 +0530)]
arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.
While at it, let's also fix the size of the llcc_broadcast_base to cover
the whole region.
Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-6-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 14 Mar 2023 08:04:33 +0000 (13:34 +0530)]
arm64: dts: qcom: sc7180: Fix the base addresses of LLCC banks
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.
On SC7180, there is only one LLCC bank available. So let's just pass that
as "llcc0_base".
Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-5-manivannan.sadhasivam@linaro.org
Manivannan Sadhasivam [Tue, 14 Mar 2023 08:04:32 +0000 (13:34 +0530)]
arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.
On SDM845, the size of the LLCC bank 0 needs to be reduced to 0x4500 as
there are LLCC BWMON registers located after this range.
Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-4-manivannan.sadhasivam@linaro.org
Konrad Dybcio [Thu, 2 Mar 2023 01:18:49 +0000 (02:18 +0100)]
arm64: dts: qcom: msm8996: Add missing DWC3 quirks
Add missing dwc3 quirks from msm-3.18. Unfortunately, none of them
make `dwc3-qcom 6af8800.usb: HS-PHY not in L2` go away.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230302011849.1873056-1-konrad.dybcio@linaro.org
Mukesh Ojha [Wed, 22 Feb 2023 15:30:45 +0000 (21:00 +0530)]
arm64: dts: qcom: sm8450: Add IMEM and PIL info region
Add a simple-mfd representing IMEM on SM8450 and define the PIL
relocation info region, so that post mortem tools will be able
to locate the loaded remoteprocs.
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1677079845-17650-1-git-send-email-quic_mojha@quicinc.com
Bartosz Golaszewski [Tue, 21 Feb 2023 15:05:43 +0000 (16:05 +0100)]
arm64: dts: qcom: sa8775p: add cpufreq node
Add a node for the cpufreq engine and specify the frequency domains for
all CPUs.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230221150543.283487-3-brgl@bgdev.pl
projects / platform / kernel / linux-rpi.git / log