Wei Mi [Wed, 18 Jul 2018 16:56:33 +0000 (16:56 +0000)]
[RegAlloc][NFC] Fix the help string of the option "huge-size-for-split".
llvm-svn: 337402
Paul Semel [Wed, 18 Jul 2018 16:39:21 +0000 (16:39 +0000)]
[llvm-objdump] Add -demangle (-C) option
Differential Revision: https://reviews.llvm.org/D49043
llvm-svn: 337401
Roman Lebedev [Wed, 18 Jul 2018 16:19:06 +0000 (16:19 +0000)]
[NFC][X86][AArch64][DAGCombine] More tests for optimizeSetCCOfSignedTruncationCheck()
At least one of these cases is more canonical,
so we really do have to handle it.
https://godbolt.org/g/pkzP3X
https://rise4fun.com/Alive/pQyh
llvm-svn: 337400
Benjamin Kramer [Wed, 18 Jul 2018 16:17:53 +0000 (16:17 +0000)]
[llvm-objcopy] %python wants to be in quotes, because it might contain spaces
llvm-svn: 337399
Nirav Dave [Wed, 18 Jul 2018 16:17:03 +0000 (16:17 +0000)]
[MC] Fix nested macro body parsing
Add missing .rep case in nestlevel checking for macro body parsing.
llvm-svn: 337398
Stella Stamenova [Wed, 18 Jul 2018 15:50:24 +0000 (15:50 +0000)]
Fix variables.test after D49018
Summary: This one fixes variables.test after D49018. The test was broken because D49018 adds a location information to variables, but I hadn't noticed that, because I used 32-bit build to run tests, so the test looked to me already broken before that commit (the test relies on mangled names, but the mangling schemes are different for 32-bit and 64-bit).
Reviewers: stella.stamenova, lldb-commits
Reviewed By: stella.stamenova
Patch By: Aleksandr Urakov
Differential Revision: https://reviews.llvm.org/D49475
llvm-svn: 337397
Eric Liu [Wed, 18 Jul 2018 15:31:14 +0000 (15:31 +0000)]
[clangd] Also get scope for RK_pattern completion results.
For exmaple, clas field candidates in constructor initializers can be
RK_Pattern, but they can still have scopes.
llvm-svn: 337396
Stella Stamenova [Wed, 18 Jul 2018 15:21:54 +0000 (15:21 +0000)]
[windows] Use a well-known path for ComSpec if we fail to retrieve it
Summary: Right now we always try to retrieve ComSpec and if we fail, we give up. This rarely fails, but we can update the logic so that we fail even less frequently. Since there is a well-known path (albeit not always correct), try the path when we failed to retrieve it. Note that on other platforms, we generally just return a well-known path without any checking.
Reviewers: asmith, zturner, labath
Reviewed By: zturner, labath
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49451
llvm-svn: 337395
Eric Liu [Wed, 18 Jul 2018 15:17:52 +0000 (15:17 +0000)]
[CodeComplete] Allow getDeclaration on RK_Pattern result.
Summary:
RK_Pattern results can also have associated declarations e.g. field
decls in constructor initializers.
Reviewers: bkramer
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D49484
llvm-svn: 337394
Stella Stamenova [Wed, 18 Jul 2018 15:16:54 +0000 (15:16 +0000)]
[lit, lldbsuite] Remove tests that are duplicated between lit and lldb-suite
Summary: Several tests exist in both lit and lldbsuite. This removes the lit version of the duplicated tests.
Reviewers: asmith, zturner
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49450
llvm-svn: 337393
Simon Atanasyan [Wed, 18 Jul 2018 14:11:22 +0000 (14:11 +0000)]
[mips] Fix predicate for the MipsTruncIntFP pattern
This is a follow-up to the rL337171. This patch fixes regression
introduced by the r337171 and enables MipsTruncIntFP pattern.
Differential revision: https://reviews.llvm.org/D49469
llvm-svn: 337392
Chandler Carruth [Wed, 18 Jul 2018 14:05:14 +0000 (14:05 +0000)]
[x86/SLH] Add the design document for Speculative Load Hardening,
a Spectre v1 mitigation.
This was initially posted w/ the patch implementing this, got some basic
review there. Also, it is generated from a the Google doc that I shared
as part of the Speculative Load Hardening RFC and which has seen pretty
widespread review at this point.
However, as the patches are landing in LLVM, I wanted to land the docs
as well. But it seemed like a bad idea to have them in the same commit
in case of reverts or other things. So the docs are split out here.
Thanks for all the review so far, and further review and improvements to
the documentation here welcome. Please feel free to keep hammering on
the code review or Google document.
Note that this is a markdown document which Sphinx doesn't yet process.
But we can add support for that after and this should get picked up
(and I'm preparing patches for that). Also, this gets the document
itself into a nice shared place where we can iterate on it.
Differential Revision: https://reviews.llvm.org/D49433
llvm-svn: 337391
Simon Pilgrim [Wed, 18 Jul 2018 13:53:55 +0000 (13:53 +0000)]
[SLPVectorizer] Avoid duplicate scalar cost calculations in BoUpSLP::getEntryCost. NFCI.
Pulled out from D49225, we have a lot of repeated scalar cost calculations, often with arguments that don't look the same but turn out to be.
llvm-svn: 337390
Tim Northover [Wed, 18 Jul 2018 13:42:18 +0000 (13:42 +0000)]
[Support] Build fix for Haiku when checking for a local filesystem
Haiku does not expose information about local versus remote mounts, so just
return false, like Cygwin.
Patch by Niels Sascha Reedijk.
llvm-svn: 337389
Erich Keane [Wed, 18 Jul 2018 13:07:13 +0000 (13:07 +0000)]
Clear properties inadvertantly added to tests in R336379
llvm-svn: 337388
Simon Pilgrim [Wed, 18 Jul 2018 13:01:20 +0000 (13:01 +0000)]
[X86][SSE] Remove BLENDPD canonicalization from combineTargetShuffle
When rL336971 removed the scalar-fp isel patterns, we lost the need for this canonicalization - commutation/folding can handle everything else.
llvm-svn: 337387
Tim Northover [Wed, 18 Jul 2018 12:37:43 +0000 (12:37 +0000)]
ARM: stop explicitly marking armv7k libcalls as hard-float. NFC.
Since the triple's default is hard float, the libcalls will already use VFP
registers.
llvm-svn: 337386
Tim Northover [Wed, 18 Jul 2018 12:37:04 +0000 (12:37 +0000)]
ARM: switch armv7em triple to hard-float defaults and libcalls.
We were emitting incorrect calls to libm functions that LLVM had decided it
knew about because the default is soft-float.
llvm-svn: 337385
Tim Northover [Wed, 18 Jul 2018 12:36:25 +0000 (12:36 +0000)]
ARM: deduplicate hard-float detection code. NFC.
ARMSubtarget had a copy/pasted block to determine whether the target was
hard-float, but it just delegated to triple features anyway so it's better at
the TargetMachine level.
llvm-svn: 337384
Sander de Smalen [Wed, 18 Jul 2018 11:59:12 +0000 (11:59 +0000)]
[AArch64][SVE] Asm: Support for unpredicated FP operations.
This patch adds support for the following unpredicated
floating-point instructions:
FADD Floating point add
FSUB Floating point subtract
FMUL Floating point multiplication
FTSMUL Floating point trigonometric starting value
FRECPS Floating point reciprocal step
FRSQRTS Floating point reciprocal square root step
The instructions have the following assembly format:
fadd z0.h, z1.h, z2.h
and have variants for 16, 32 and 64-bit FP elements.
llvm-svn: 337383
George Rimar [Wed, 18 Jul 2018 11:56:53 +0000 (11:56 +0000)]
[ELF] - Stop silently producing a broken .eh_frame_hdr.
Currently, getFdePC() returns uint64_t. Its because the following
encodings might use 8 bytes: DW_EH_PE_absptr and DW_EH_PE_udata8.
But caller assigns returned value to uint32_t field:
https://github.com/llvm-mirror/lld/blob/master/ELF/SyntheticSections.cpp#L508
Value is used for building .eh_frame_hdr section.
We use DW_EH_PE_sdata4 encoding for building it at this moment:
https://github.com/llvm-mirror/lld/blob/master/ELF/SyntheticSections.cpp#L2545
And that means that an overflow issue might happen if
DW_EH_PE_absptr/DW_EH_PE_udata8 address encodings are present
in .eh_frame. In that case, before this patch, we silently would
truncate the address and produced broken .eh_frame_hdr section.
It would be not hard to support real 64-bit values for
DW_EH_PE_absptr/DW_EH_PE_udata8 encodings, but it is
unclear if it is usefull and if we should do it.
Since nobody faced/reported it, int this patch I only implement
a check to stop producing broken output silently for now.
llvm-svn: 337382
Nico Weber [Wed, 18 Jul 2018 11:55:03 +0000 (11:55 +0000)]
Mention clang-cl improvements from r335466 and r336379 in ReleaseNotes.rst
llvm-svn: 337381
Andrea Di Biagio [Wed, 18 Jul 2018 11:16:31 +0000 (11:16 +0000)]
[TargetInstPredicate] Add definition of CheckInvalidRegisterOperand.
This should have been part of r337378. I forgot to svn add it before committing
the change.
llvm-svn: 337380
Max Kazantsev [Wed, 18 Jul 2018 11:03:40 +0000 (11:03 +0000)]
[NFC] Make a test more neat
llvm-svn: 337379
Andrea Di Biagio [Wed, 18 Jul 2018 11:03:22 +0000 (11:03 +0000)]
[Tablegen][PredicateExpander] Add the ability to define checks for invalid registers.
This was discussed in review D49436.
llvm-svn: 337378
George Rimar [Wed, 18 Jul 2018 11:02:37 +0000 (11:02 +0000)]
[ELF] - Add a test case to check DW_EH_PE_absptr address encoding.
This covers the following line of the code:
https://github.com/llvm-mirror/lld/blob/master/ELF/SyntheticSections.cpp#L525
llvm-svn: 337377
Roman Lebedev [Wed, 18 Jul 2018 10:55:17 +0000 (10:55 +0000)]
[InstCombine] Re-commit: Fold 'check for [no] signed truncation' pattern
Summary:
[[ https://bugs.llvm.org/show_bug.cgi?id=38149 | PR38149 ]]
As discussed in https://reviews.llvm.org/D49179#1158957 and later,
the IR for 'check for [no] signed truncation' pattern can be improved:
https://rise4fun.com/Alive/gBf
^ that pattern will be produced by Implicit Integer Truncation sanitizer,
https://reviews.llvm.org/D48958 https://bugs.llvm.org/show_bug.cgi?id=21530
in signed case, therefore it is probably a good idea to improve it.
The DAGCombine will reverse this transform, see
https://reviews.llvm.org/D49266
This transform is surprisingly frustrating.
This does not deal with non-splat shift amounts, or with undef shift amounts.
I've outlined what i think the solution should be:
```
// Potential handling of non-splats: for each element:
// * if both are undef, replace with constant 0.
// Because (1<<0) is OK and is 1, and ((1<<0)>>1) is also OK and is 0.
// * if both are not undef, and are different, bailout.
// * else, only one is undef, then pick the non-undef one.
```
This is a re-commit, as the original patch, committed in rL337190
was reverted in rL337344 as it broke chromium build:
https://bugs.llvm.org/show_bug.cgi?id=38204 and
https://crbug.com/864832
Proofs that the fixed folds are ok: https://rise4fun.com/Alive/VYM
Differential Revision: https://reviews.llvm.org/D49320
llvm-svn: 337376
Simon Pilgrim [Wed, 18 Jul 2018 10:54:13 +0000 (10:54 +0000)]
[X86][SSE] Add extra scalar fop + blend tests for commuted inputs
While working on PR38197, I noticed that we don't make use of FADD/FMUL being able to commute the inputs to support the addps+movss -> addss style combine
llvm-svn: 337375
George Rimar [Wed, 18 Jul 2018 10:42:10 +0000 (10:42 +0000)]
[ELF] - Improve eh-frame-value-format7.s test case.
This adds .eh_frame_hdr content checking to test
that DW_EH_PE_udata2 address was decoded correctly.
llvm-svn: 337374
Daniel Cederman [Wed, 18 Jul 2018 10:05:30 +0000 (10:05 +0000)]
Revert "[Sparc] Use the IntPair reg class for r constraints with value type f64"
This reverts commit
55222c9183c6e07f53a54c4061677734f54feac1.
I missed that this patch has a dependency on https://reviews.llvm.org/D49219
that has not been approved yet.
llvm-svn: 337373
Sander de Smalen [Wed, 18 Jul 2018 09:37:51 +0000 (09:37 +0000)]
[AArch64][SVE] Asm: Support for UDOT/SDOT instructions.
The signed/unsigned DOT instructions perform a dot-product on
quadtuplets from two source vectors and accumulate the result in
the destination register. The instructions come in two forms:
Vector form, e.g.
sdot z0.s, z1.b, z2.b - signed dot product on four 8-bit quad-tuplets,
accumulating results in 32-bit elements.
udot z0.d, z1.h, z2.h - unsigned dot product on four 16-bit quad-tuplets,
accumulating results in 64-bit elements.
Indexed form, e.g.
sdot z0.s, z1.b, z2.b[3] - signed dot product on four 8-bit quad-tuplets
with specified quadtuplet from second
source vector, accumulating results in 32-bit
elements.
udot z0.d, z1.h, z2.h[1] - dot product on four 16-bit quad-tuplets
with specified quadtuplet from second
source vector, accumulating results in 64-bit
elements.
llvm-svn: 337372
George Rimar [Wed, 18 Jul 2018 09:25:36 +0000 (09:25 +0000)]
[llvm-objdump] - An attempt to fix BB after r337361.
Seems r337361 is the reason of the following ARM BB failures:
http://lab.llvm.org:8011/builders/clang-cmake-armv8-quick
http://lab.llvm.org:8011/builders/clang-cmake-armv8-full/builds/4633
Reason is unclear to me, other bots are OK.
If this will not help, I'll revert r337361.
llvm-svn: 337371
Daniel Cederman [Wed, 18 Jul 2018 09:25:33 +0000 (09:25 +0000)]
[Sparc] Use the IntPair reg class for r constraints with value type f64
Summary: This is how it appears to be handled in GCC and it prevents a
"Unknown mismatch" error in the SelectionDAGBuilder.
Reviewers: venkatra, jyknight, jrtc27
Reviewed By: jyknight, jrtc27
Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D49218
llvm-svn: 337370
Sander de Smalen [Wed, 18 Jul 2018 09:17:29 +0000 (09:17 +0000)]
[AArch64][SVE] Asm: Integer divide instructions.
This patch adds the following predicated instructions:
UDIV Unsigned divide active elements
UDIVR Unsigned divide active elements, reverse form.
SDIV Signed divide active elements
SDIVR Signed divide active elements, reverse form.
e.g.
udiv z0.s, p0/m, z0.s, z1.s
(unsigned divide active elements in z0 by z1, store result in z0)
sdivr z0.s, p0/m, z0.s, z1.s
(signed divide active elements in z1 by z0, store result in z0)
llvm-svn: 337369
Simon Pilgrim [Wed, 18 Jul 2018 09:10:18 +0000 (09:10 +0000)]
Fix -Wdocumentation warning. NFCI.
llvm-svn: 337368
Simon Pilgrim [Wed, 18 Jul 2018 09:07:54 +0000 (09:07 +0000)]
Fix -Wdocumentation warning. NFCI.
llvm-svn: 337367
Philip Pfaffe [Wed, 18 Jul 2018 08:53:31 +0000 (08:53 +0000)]
[CMake] Export the LLVM_LINK_LLVM_DYLIB setting
Summary:
When building out-of-tree tools, there are several macros available to
automate linking against llvm. An examples is `add_llvm_executable`, or
the clang variant of this.
These macros use the LLVM_LINK_LLVM_DYLIB option to decide whether to
link against libraries defined by setting LLVM_LINK_COMPONENTS or to
link against libLLVM instead. Currently this is problematic in
out-of-tree targets, because they cannot identify whether this option is
required or even available. If the option was enabled in LLVM's own
build, the clang libraries are built against libLLVM, so a client
linking against those must link against it too. On the other hand the
client can't just always link against it, because it might not be
available.
This is related to D44391, but that change assumed the client knew
whether they wanted the dylib or not.
Reviewers: mgorny, beanz, labath
Reviewed By: mgorny
Subscribers: bollu, llvm-commits
Differential Revision: https://reviews.llvm.org/D49193
llvm-svn: 337366
George Rimar [Wed, 18 Jul 2018 08:52:09 +0000 (08:52 +0000)]
[ELF] - Improve relocatable-many-sections.s test case. NFC.
This adds a check for .shstrtab section index.
llvm-svn: 337365
Roman Lebedev [Wed, 18 Jul 2018 08:49:51 +0000 (08:49 +0000)]
[NFC][InstCombine] i65 tests for 'check for [no] signed truncation' pattern
Those initially broke chromium build:
https://bugs.llvm.org/show_bug.cgi?id=38204 and
https://crbug.com/864832
llvm-svn: 337364
George Rimar [Wed, 18 Jul 2018 08:44:38 +0000 (08:44 +0000)]
[ELF] - Do not produce broken output when amount of sections is > ~65k
This is a part of ttps://bugs.llvm.org//show_bug.cgi?id=38119
We produce broken ELF header now when the number of output sections is >= SHN_LORESERVE (0xff00).
ELF spec says (http://www.sco.com/developers/gabi/2003-12-17/ch4.eheader.html):
e_shnum:
If the number of sections is greater than or equal to SHN_LORESERVE (0xff00), this member has the value zero
and the actual number of section header table entries is contained in the sh_size field of the section header at index 0.
(Otherwise, the sh_size member of the initial entry contains 0.)
e_shstrndx
If the section name string table section index is greater than or equal to SHN_LORESERVE (0xff00), this member has the
value SHN_XINDEX (0xffff) and the actual index of the section name string table section is contained in the sh_link field of
the section header at index 0. (Otherwise, the sh_link member of the initial entry contains 0.)
We did not set these fields correctly earlier. The patch fixes the issue.
Differential revision: https://reviews.llvm.org/D49371
llvm-svn: 337363
George Rimar [Wed, 18 Jul 2018 08:39:31 +0000 (08:39 +0000)]
[ELF] — Add a test case for DW_EH_PE_udata2 encoding.
This adds a test to check LLD can handle such address format correctly.
Test case covers the following line:
https://github.com/llvm-mirror/lld/blob/master/ELF/SyntheticSections.cpp#L519
llvm-svn: 337362
George Rimar [Wed, 18 Jul 2018 08:34:35 +0000 (08:34 +0000)]
[llvm-objdump] - Stop reporting bogus section IDs.
Imagine we have a file with few sections, and one of them is .foo
with index N != 0.
Problem is that when llvm-objdump is given a -section=.foo parameter
it lists .foo as a section at index 0. That makes impossible to write
test cases which needs to find the index of the particular section,
while ignoring dumping of others.
The patch fixes that.
Differential revision: https://reviews.llvm.org/D49372
llvm-svn: 337361
George Rimar [Wed, 18 Jul 2018 08:19:58 +0000 (08:19 +0000)]
[llvm-readobj] - Teach tool to dump objects with >= SHN_LORESERVE of sections.
http://www.sco.com/developers/gabi/2003-12-17/ch4.eheader.html
says that e_shnum and/or e_shstrndx may have special values if
"the number of sections is greater than or equal to SHN_LORESERVE" or
"the section name string table section index is greater than or equal to SHN_LORESERVE (0xff00)"
Previously llvm-readobj was unable to dump such files, patch changes that.
I had to add a precompiled test case because it does not seem possible to
prepare a test using yaml2obj or llvm-mc (not clear how to make .shstrtab
to have index >= SHN_LORESERVE).
Differential revision: https://reviews.llvm.org/D49369
llvm-svn: 337360
Roman Lebedev [Wed, 18 Jul 2018 08:15:13 +0000 (08:15 +0000)]
Revert test changes part of "Revert "[InstCombine] Fold 'check for [no] signed truncation' pattern""
We want the test to remain good anyway.
I think the fix is incoming.
This reverts part of commit rL337344.
llvm-svn: 337359
Sander de Smalen [Wed, 18 Jul 2018 08:10:03 +0000 (08:10 +0000)]
[AArch64][SVE] Asm: Support for integer MUL instructions.
This patch adds the following instructions:
MUL - multiply vectors, e.g.
mul z0.h, p0/m, z0.h, z1.h
- multiply with immediate, e.g.
mul z0.h, z0.h, #127
SMULH - signed multiply returning high half, e.g.
smulh z0.h, p0/m, z0.h, z1.h
UMULH - unsigned multiply returning high half, e.g.
umulh z0.h, p0/m, z0.h, z1.h
llvm-svn: 337358
Craig Topper [Wed, 18 Jul 2018 07:31:32 +0000 (07:31 +0000)]
[X86] Enable commuting of VUNPCKHPD to VMOVLHPS to enable load folding by using VMOVLPS with a modified address.
This required an annoying amount of tablegen multiclass changes to make only VUNPCKHPDZ128rr commutable.
llvm-svn: 337357
Craig Topper [Wed, 18 Jul 2018 07:31:30 +0000 (07:31 +0000)]
[X86] Add test case for missed opportunity to commute vunpckhpd to enable use of vmovlps to fold a load.
We do this transform for SSE, but not AVX or AVX512VL.
llvm-svn: 337356
Joachim Protze [Wed, 18 Jul 2018 07:23:46 +0000 (07:23 +0000)]
[libomptarget] Also support several images for elf
In revision r336569 (D49036) libomptarget support for multiple nvidia images
has been fixed in case a target region resides inside one or multiple
libraries and in the compiled application. But the issues is still present
for elf images.
This fix will also support multiple images for elf.
Patch by Jannis Klinkenberg
Reviewers: protze.joachim, ABataev, grokos
Reviewed By: protze.joachim, ABataev, grokos
Subscribers: openmp-commits
Differential Revision: https://reviews.llvm.org/D49418
llvm-svn: 337355
Craig Topper [Wed, 18 Jul 2018 07:08:28 +0000 (07:08 +0000)]
[X86] Regenerate fma.ll checks using current version of the script which produces different regular expressions on spills and reloads. NFC
llvm-svn: 337354
Vassil Vassilev [Wed, 18 Jul 2018 06:49:33 +0000 (06:49 +0000)]
[modules] Print input files when -module-file-info file switch is passed.
This patch improves traceability of duplicated header files which end
up in multiple pcms.
Differential Revision: https://reviews.llvm.org/D47118
llvm-svn: 337353
Martin Storsjo [Wed, 18 Jul 2018 06:15:09 +0000 (06:15 +0000)]
[AArch64] Define TARGET_HEADER_BUILTIN
Without it, the new intrinsics became available for all language
variants. This was missed in SVN r337327.
llvm-svn: 337352
Hiroshi Inoue [Wed, 18 Jul 2018 06:04:43 +0000 (06:04 +0000)]
[NFC] fix trivial typos in comments
llvm-svn: 337351
Justin Hibbits [Wed, 18 Jul 2018 05:19:25 +0000 (05:19 +0000)]
Fix build failures from r337347, found by clang
* Delete a no-longer-used override, and mark the other
getRegisterTypeForCallingConv() as override.
* SPE only supports i32, not i64, as the internal type, so simply remove
the type check, so that DestReg and Opc are provably always set.
GCC 6.4 did not warn about either of the above.
llvm-svn: 337350
Craig Topper [Wed, 18 Jul 2018 05:10:53 +0000 (05:10 +0000)]
[X86] Remove patterns that mix X86ISD::MOVLHPS/MOVHLPS with v2i64/v2f64 types.
The X86ISD::MOVLHPS/MOVHLPS should now only be emitted in SSE1 only. This means that the v2i64/v2f64 types would be illegal thus we don't need these patterns.
llvm-svn: 337349
Craig Topper [Wed, 18 Jul 2018 05:10:51 +0000 (05:10 +0000)]
[X86] Generate v2f64 X86ISD::UNPCKL/UNPCKH instead of X86ISD::MOVLHPS/MOVHLPS for unary v2f64 {0,0} and {1,1} shuffles with SSE2.
I'm trying to restrict the MOVLHPS/MOVHLPS ISD nodes to SSE1 only. With SSE2 we can use unpcks. I believe this will allow some patterns to be cleaned up to require fewer bitcasts.
I've put in an odd isel hack to still select MOVHLPS instruction from the unpckh node to avoid changing tests and because movhlps is a shorter encoding. Ideally we'd do execution domain switching on this, but the operands are in the wrong order and are tied. We might be able to try a commute in the domain switching using custom code.
We already support domain switching for UNPCKLPD and MOVLHPS.
llvm-svn: 337348
Justin Hibbits [Wed, 18 Jul 2018 04:25:10 +0000 (04:25 +0000)]
Introduce codegen for the Signal Processing Engine
Summary:
The Signal Processing Engine (SPE) is found on NXP/Freescale e500v1,
e500v2, and several e200 cores. This adds support targeting the e500v2,
as this is more common than the e500v1, and is in SoCs still on the
market.
This patch is very intrusive because the SPE is binary incompatible with
the traditional FPU. After discussing with others, the cleanest
solution was to make both SPE and FPU features on top of a base PowerPC
subset, so all FPU instructions are now wrapped with HasFPU predicates.
Supported by this are:
* Code generation following the SPE ABI at the LLVM IR level (calling
conventions)
* Single- and Double-precision math at the level supported by the APU.
Still to do:
* Vector operations
* SPE intrinsics
As this changes the Callee-saved register list order, one test, which
tests the precise generated code, was updated to account for the new
register order.
Reviewed by: nemanjai
Differential Revision: https://reviews.llvm.org/D44830
llvm-svn: 337347
Justin Hibbits [Wed, 18 Jul 2018 04:24:57 +0000 (04:24 +0000)]
Complete the SPE instruction set patterns
This is the lead-up to having SPE codegen. Add the rest of the
instructions, along with MC tests.
Differential Revision: https://reviews.llvm.org/D44829
llvm-svn: 337346
Justin Hibbits [Wed, 18 Jul 2018 04:24:49 +0000 (04:24 +0000)]
Add PowerPC e500(v2) core scheduler and directives.
Differential Revision: https://reviews.llvm.org/D44828
llvm-svn: 337345
Bob Haarman [Wed, 18 Jul 2018 02:18:28 +0000 (02:18 +0000)]
Revert "[InstCombine] Fold 'check for [no] signed truncation' pattern"
This reverts r337190 (and a few follow-up commits), which caused the
Chromium build to fail. See
https://bugs.llvm.org/show_bug.cgi?id=38204 and
https://crbug.com/864832
llvm-svn: 337344
Dean Michael Berris [Wed, 18 Jul 2018 02:08:39 +0000 (02:08 +0000)]
[XRay][compiler-rt] Segmented Array: Simplify and Optimise
Summary:
This is a follow-on to D49217 which simplifies and optimises the
implementation of the segmented array. In this patch we co-locate the
book-keeping for segments in the `__xray::Array<T>` with the data it's
managing. We take the chance in this patch to actually rename `Chunk` to
`Segment` to better align with the high-level description of the
segmented array.
With measurements using benchmarks landed in D48879, we've identified
that calls to `pthread_getspecific` started dominating the cycles, which
led us to revert the change made in D49217 to use C++ thread_local
initialisation instead (it reduces the cost by a huge margin, since we
save one PLT-based call to pthread functions in the hot path). In
particular, this is in `__xray::getThreadLocalData()`.
We also took the opportunity to remove the least-common-multiple based
calculation and instead pack as much data into segments of the array.
This greatly simplifies the API of the container which hides as much of
the implementation details as possible. For instance, we calculate the
number of elements we need for the each segment internally in the Array
instead of making it part of the type.
With the changes here, we're able to get a measurable improvement on the
performance of profiling mode on top of what D48879 already provides.
Depends on D48879.
Reviewers: kpw, eizan
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49363
llvm-svn: 337343
Dean Michael Berris [Wed, 18 Jul 2018 01:53:39 +0000 (01:53 +0000)]
[XRay][compiler-rt] Simplify Allocator Implementation
Summary:
This change simplifies the XRay Allocator implementation to self-manage
an mmap'ed memory segment instead of using the internal allocator
implementation in sanitizer_common.
We've found through benchmarks and profiling these benchmarks in D48879
that using the internal allocator in sanitizer_common introduces a
bottleneck on allocating memory through a central spinlock. This change
allows thread-local allocators to eliminate contention on the
centralized allocator.
To get the most benefit from this approach, we also use a managed
allocator for the chunk elements used by the segmented array
implementation. This gives us the chance to amortize the cost of
allocating memory when creating these internal segmented array data
structures.
We also took the opportunity to remove the preallocation argument from
the allocator API, simplifying the usage of the allocator throughout the
profiling implementation.
In this change we also tweak some of the flag values to reduce the
amount of maximum memory we use/need for each thread, when requesting
memory through mmap.
Depends on D48956.
Reviewers: kpw, eizan
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49217
llvm-svn: 337342
Dean Michael Berris [Wed, 18 Jul 2018 01:31:30 +0000 (01:31 +0000)]
[XRay][compiler-rt] FDR Mode: Allow multiple runs
Summary:
Fix a bug in FDR mode which didn't allow for re-initialising the logging
in the same process. This change ensures that:
- When we flush the FDR mode logging, that the state of the logging
implementation is `XRAY_LOG_UNINITIALIZED`.
- Fix up the thread-local initialisation to use aligned storage and
`pthread_getspecific` as well as `pthread_setspecific` for the
thread-specific data.
- Actually use the pointer provided to the thread-exit cleanup handling,
instead of assuming that the thread has thread-local data associated
with it, and reaching at thread-exit time.
In this change we also have an explicit test for two consecutive
sessions for FDR mode tracing, and ensuring both sessions succeed.
Reviewers: kpw, eizan
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49359
llvm-svn: 337341
Sterling Augustine [Wed, 18 Jul 2018 00:33:25 +0000 (00:33 +0000)]
Workaround warning bug in old versions of gcc.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=56480
llvm-svn: 337340
Peter Collingbourne [Wed, 18 Jul 2018 00:27:07 +0000 (00:27 +0000)]
Re-land r337333, "Teach Clang to emit address-significance tables.",
which was reverted in r337336.
The problem that required a revert was fixed in r337338.
Also added a missing "REQUIRES: x86-registered-target" to one of
the tests.
Original commit message:
> Teach Clang to emit address-significance tables.
>
> By default, we emit an address-significance table on all ELF
> targets when the integrated assembler is enabled. The emission of an
> address-significance table can be controlled with the -faddrsig and
> -fno-addrsig flags.
>
> Differential Revision: https://reviews.llvm.org/D48155
llvm-svn: 337339
Peter Collingbourne [Wed, 18 Jul 2018 00:21:40 +0000 (00:21 +0000)]
CodeGen: Don't create address significance table entries for thread-local variables.
The presence of these symbols in the symbol table can cause symbol type
mismatch errors (or undefined symbol errors on emulated TLS targets)
and they can't be ICF'd anyway.
llvm-svn: 337338
Puyan Lotfi [Wed, 18 Jul 2018 00:10:51 +0000 (00:10 +0000)]
[NFC][llvm-objcopy] Cleanup namespace usage in llvm-objcopy.
Nest any classes not used outside of a file into anon. Nest any classes used
across files in llvm-objcopy into namespace llvm::objcopy.
Differential Revision: https://reviews.llvm.org/D49449
llvm-svn: 337337
Peter Collingbourne [Tue, 17 Jul 2018 23:56:30 +0000 (23:56 +0000)]
Revert r337333, "Teach Clang to emit address-significance tables."
Causing multiple failures on sanitizer bots due to TLS symbol errors,
e.g.
/usr/bin/ld: __msan_origin_tls: TLS definition in /home/buildbots/ppc64be-clang-test/clang-ppc64be/stage1/lib/clang/7.0.0/lib/linux/libclang_rt.msan-powerpc64.a(msan.cc.o) section .tbss.__msan_origin_tls mismatches non-TLS reference in /tmp/lit_tmp_0a71tA/mallinfo-3ca75e.o
llvm-svn: 337336
Jason Molenda [Tue, 17 Jul 2018 23:44:09 +0000 (23:44 +0000)]
Link the lldb driver ("lldb") against the llvm static
libraries because of the new prettystackprinter dependency.
llvm-svn: 337335
Craig Topper [Tue, 17 Jul 2018 23:26:20 +0000 (23:26 +0000)]
[X86] Remove the vector alignment requirement from the patterns added in r337320.
The resulting instruction will only load 64 bits so alignment isn't required.
llvm-svn: 337334
Peter Collingbourne [Tue, 17 Jul 2018 23:17:16 +0000 (23:17 +0000)]
Teach Clang to emit address-significance tables.
By default, we emit an address-significance table on all ELF
targets when the integrated assembler is enabled. The emission of an
address-significance table can be controlled with the -faddrsig and
-fno-addrsig flags.
Differential Revision: https://reviews.llvm.org/D48155
llvm-svn: 337333
Sterling Augustine [Tue, 17 Jul 2018 23:16:02 +0000 (23:16 +0000)]
Implement framework for linking split-stack object files, and x86_64 support.
llvm-svn: 337332
Peter Collingbourne [Tue, 17 Jul 2018 22:40:08 +0000 (22:40 +0000)]
CodeGen: Add a target option for emitting .addrsig directives for all address-significant symbols.
Differential Revision: https://reviews.llvm.org/D48143
llvm-svn: 337331
Richard Smith [Tue, 17 Jul 2018 22:24:11 +0000 (22:24 +0000)]
Replace LLVM_ALIGNAS with just alignas.
Various places in Clang and LLVM are already using alignas; it seems
our minimum host configuration now requires it.
llvm-svn: 337330
Richard Smith [Tue, 17 Jul 2018 22:24:09 +0000 (22:24 +0000)]
Restructure checking for, and warning on, lifetime extension.
This change implements C++ DR1696, which makes initialization of a
reference member of a class from a temporary object ill-formed. The
standard wording here is imprecise, but we interpret it as meaning that
any time a mem-initializer would result in lifetime extension, the
program is ill-formed.
This reinstates r337226, reverted in r337255, with a fix for the
InitializedEntity alignment problem that was breaking ARM buildbots.
llvm-svn: 337329
Peter Collingbourne [Tue, 17 Jul 2018 22:17:18 +0000 (22:17 +0000)]
MC: Implement support for new .addrsig and .addrsig_sym directives.
Part of the address-significance tables proposal:
http://lists.llvm.org/pipermail/llvm-dev/2018-May/123514.html
Differential Revision: https://reviews.llvm.org/D47744
llvm-svn: 337328
Mandeep Singh Grang [Tue, 17 Jul 2018 22:03:24 +0000 (22:03 +0000)]
[COFF] Add more missing MSVC ARM64 intrinsics
Summary:
Added the following intrinsics:
_BitScanForward, _BitScanReverse, _BitScanForward64, _BitScanReverse64
_InterlockedAnd64, _InterlockedDecrement64, _InterlockedExchange64,
_InterlockedExchangeAdd64, _InterlockedExchangeSub64,
_InterlockedIncrement64, _InterlockedOr64, _InterlockedXor64.
Reviewers: compnerd, mstorsjo, rnk, javed.absar
Reviewed By: mstorsjo
Subscribers: kristof.beyls, chrib, llvm-commits
Differential Revision: https://reviews.llvm.org/D49445
llvm-svn: 337327
Eli Friedman [Tue, 17 Jul 2018 20:38:11 +0000 (20:38 +0000)]
[LangRef] Clarify semantics of load metadata.
We need to explicitly state what happens when an invariant promised by
load metadata is violated at runtime, since it's come up repeatedly.
It's possible we want to specify that the result of the load is poison
in some cases, rather than undefined behavior, if the constraint is
violated. That would allow preserving the metadata when the load is
hoisted, but doesn't allow propagating metadata based on control flow.
We currently do transforms based on control flow for nonnull metadata
(in PromoteMemToReg).
Differential Revision: https://reviews.llvm.org/D47854
llvm-svn: 337325
Max Moroz [Tue, 17 Jul 2018 20:37:40 +0000 (20:37 +0000)]
[libFuzzer] Mutation tracking and logging implemented.
Summary:
Code now exists to track number of mutations that are used in fuzzing in total
and ones that produce new coverage. The stats are currently being dumped to the
command line.
Patch by Kodé Williams (@kodewilliams).
Reviewers: metzman, Dor1s, morehouse, kcc
Reviewed By: Dor1s, morehouse, kcc
Subscribers: delcypher, kubamracek, kcc, morehouse, llvm-commits, #sanitizers, mgorny
Differential Revision: https://reviews.llvm.org/D48054
llvm-svn: 337324
Eli Friedman [Tue, 17 Jul 2018 20:31:42 +0000 (20:31 +0000)]
[LangRef] nnan and ninf produce poison.
Clarify that violating nnan and ninf can lead to undefined behavior.
This allows more aggressive optimizations based on those assumptions.
Differential Revision: https://reviews.llvm.org/D47963
llvm-svn: 337323
Eli Friedman [Tue, 17 Jul 2018 20:28:31 +0000 (20:28 +0000)]
[LangRef] Clarify which fast-math flags affect fcmp.
nsz has no effect due to the way fcmp is defined; +0 and -0 compare
equal anyway. reassoc could have the obvious effect.
llvm-svn: 337322
Eric Christopher [Tue, 17 Jul 2018 20:22:17 +0000 (20:22 +0000)]
Remove unnecessary trailing ; in macro intrinsic definition.
llvm-svn: 337321
Craig Topper [Tue, 17 Jul 2018 20:16:18 +0000 (20:16 +0000)]
[X86] Add patterns for folding full vector load into MOVHPS and MOVLPS with SSE1 only.
llvm-svn: 337320
Craig Topper [Tue, 17 Jul 2018 20:16:15 +0000 (20:16 +0000)]
[X86] Add test case for missed opportunity to use MOVLPS on the SSE1 only targets.
llvm-svn: 337319
Fangrui Song [Tue, 17 Jul 2018 19:50:41 +0000 (19:50 +0000)]
[Demangle] Add missing header files
llvm-svn: 337318
Zachary Turner [Tue, 17 Jul 2018 19:48:46 +0000 (19:48 +0000)]
Add missing include.
llvm-svn: 337317
Zachary Turner [Tue, 17 Jul 2018 19:42:29 +0000 (19:42 +0000)]
Add some helper functions to the demangle utility classes.
These are all methods that, while not currently used in the
Itanium demangler, are generally useful enough that it's
likely the itanium demangler could find a use for them. More
importantly, they are all necessary for the Microsoft demangler
which is up and coming in a subsequent patch. Rather than
combine these into a single monolithic patch, I think it makes
sense to commit this utility code first since it is very simple,
this way it won't detract from the substance of the MS demangler
patch.
llvm-svn: 337316
Sam Clegg [Tue, 17 Jul 2018 19:15:02 +0000 (19:15 +0000)]
[WebAssemlby] Set IsUsedInRegularObj correctly for undefined data symbols
Differential Revision: https://reviews.llvm.org/D49113
llvm-svn: 337314
Martin Storsjo [Tue, 17 Jul 2018 19:14:47 +0000 (19:14 +0000)]
[builtins] Implement the __chkstk function for ARM for MinGW
This function is available for linking in from kernel32.dll, but
it's not allowed to link that function from there in Windows Store
apps.
Differential Revision: https://reviews.llvm.org/D49055
llvm-svn: 337313
Joerg Sonnenberger [Tue, 17 Jul 2018 19:00:51 +0000 (19:00 +0000)]
The semantics of DW_CFA_GNU_args_size have changed subtile over the
years. Adopt the new convention that it is call-site specific and that
it should be applied before moving the IP by personality routines, but
not during normal unwinding.
Differential Revision: https://reviews.llvm.org/D38680
llvm-svn: 337312
Alex Langford [Tue, 17 Jul 2018 18:28:51 +0000 (18:28 +0000)]
Invert dependency between lldb-framework and lldb-suite
Summary:
Currently, if you build lldb-framework the entire framework doesn't
actually build. In order to build the entire framework, you need to actually
build lldb-suite. This abstraction doesn't feel quite right because
lldb-framework truly does depend on lldb-suite (liblldb + related tools).
In this change I want to invert their dependency. This will mean that lldb and
finish_swig will depend on lldb-framework in a framework build, and lldb-suite
otherwise. Instead of adding conditional logic everywhere to handle this, I
introduce LLDB_SUITE_TARGET to handle it.
Differential Revision: https://reviews.llvm.org/D49406
llvm-svn: 337311
Vedant Kumar [Tue, 17 Jul 2018 18:08:36 +0000 (18:08 +0000)]
[InstCombine] Preserve debug value when simplifying cast-of-select
InstCombine has a cast transform that matches a cast-of-select:
Orig = cast (Src = select Cond TV FV)
And tries to replace it with a select which has the cast folded in:
NewSel = select Cond (cast TV) (cast FV)
The combiner does RAUW(Orig, NewSel), so any debug values for Orig would
survive the transform. But debug values for Src would be lost.
This patch teaches InstCombine to replace all debug uses of Src with
NewSel (taking care of doing any necessary DIExpression rewriting).
Differential Revision: https://reviews.llvm.org/D49270
llvm-svn: 337310
Vedant Kumar [Tue, 17 Jul 2018 18:08:34 +0000 (18:08 +0000)]
Remove an errant piece of !dbg metadata from a test, NFC
llvm-svn: 337309
Chandler Carruth [Tue, 17 Jul 2018 18:07:59 +0000 (18:07 +0000)]
[x86/SLH] Flesh out the data-invariant instruction table a bit based on feedback from Craig.
Summary:
The only thing he suggested that I've skipped here is the double-wide
multiply instructions. Multiply is an area I'm nervous about there being
some hidden data-dependent behavior, and it doesn't seem important for
any benchmarks I have, so skipping it and sticking with the minimal
multiply support that matches what I know is widely used in existing
crypto libraries. We can always add double-wide multiply when we have
clarity from vendors about its behavior and guarantees.
I've tried to at least cover the fundamentals here with tests, although
I've not tried to cover every width or permutation. I can add more tests
where folks think it would be helpful.
Reviewers: craig.topper
Subscribers: sanjoy, mcrosier, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D49413
llvm-svn: 337308
Simon Pilgrim [Tue, 17 Jul 2018 17:47:35 +0000 (17:47 +0000)]
[llvm-mca][x86] Add extend, carry-flag and CMP instructions to general x86_64 resource tests
llvm-svn: 337306
Simon Pilgrim [Tue, 17 Jul 2018 17:41:45 +0000 (17:41 +0000)]
[llvm-mca][x86] Add MOVBE resource tests to all supporting targets
SNB doesn't support MOVBE but the numbers in Generic (which use the SNB model) look sane.
llvm-svn: 337305
Mikhail R. Gadelha [Tue, 17 Jul 2018 17:40:34 +0000 (17:40 +0000)]
[analyzer] Fix Z3 backend after D48205
Summary:
An assertion was added in D48205 to catch places where a `nonloc::SymbolVal` was wrapping a `loc` object.
This patch fixes that in the Z3 backend by making the `SValBuilder` object accessible from inherited instances of `SimpleConstraintManager` and calling `SVB.makeSymbolVal(foo)` instead of `nonloc::SymbolVal(foo)`.
Reviewers: NoQ, george.karpenkov
Reviewed By: NoQ
Subscribers: xazax.hun, szepet, a.sidorin
Differential Revision: https://reviews.llvm.org/D49430
llvm-svn: 337304
Florian Hahn [Tue, 17 Jul 2018 17:12:50 +0000 (17:12 +0000)]
Revert rL337292 due to another MSVC STL problem.
llvm-svn: 337303
Simon Pilgrim [Tue, 17 Jul 2018 17:10:47 +0000 (17:10 +0000)]
[llvm-mca][x86] Add BSWAP resource tests
llvm-svn: 337302
Sam Clegg [Tue, 17 Jul 2018 16:40:03 +0000 (16:40 +0000)]
[WebAssembly] Update WebAssemblyLowerEmscriptenEHSjLj to handle separate compilation
Previously we were assuming whole program compilation. Now that
separate compilation is a thing we need to update this pass.
Firstly, it can no longer assert on the existence of malloc and free.
This functions might not be in the current translation unit. If we
need them then we will generate not imports for them.
Secondly the global helper function we create should be marked as
weak since we will be generating a separate copy in each translation
unit.
Finally the names of the symbols used must be unique and fixed since
they need to agree across translation units.
Differential Revision: https://reviews.llvm.org/D49263
llvm-svn: 337301
Sam Clegg [Tue, 17 Jul 2018 16:34:48 +0000 (16:34 +0000)]
Add wasm-ld to help text Improve error text
Differential Revision: https://reviews.llvm.org/D48838
llvm-svn: 337300