Simon Glass [Sun, 28 Aug 2022 18:32:48 +0000 (12:32 -0600)]
image: Drop #ifdefs for LEGACY_IMAGE_FORMAT
Use if() instead of the #ifdef in select_ramdisk().
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 28 Aug 2022 18:32:47 +0000 (12:32 -0600)]
image: Track when ramdisk processing is completed
The current switch default is tricky since it relies on #ifdefs to work.
Use a bool instead.
Also fix the comment on @select, since it has a dual purpose.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 28 Aug 2022 18:32:46 +0000 (12:32 -0600)]
image: Fix up ANDROID_BOOT_IMAGE ramdisk code
Convert this to an if(), fix the cast from an address to a pointer and
make sure that any error is returned correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 14 Sep 2022 12:57:39 +0000 (08:57 -0400)]
Merge branch '2022-09-13-add-support-for-cyclic-function-execution' into next
To quote the author:
This patchset adds the basic infrastructure to periodically execute
code, e.g. all 100ms. Examples for such functions might be LED blinking
etc. The functions that are hooked into this cyclic list should be
small timewise as otherwise the execution of the other code that relies
on a high frequent polling (e.g. UART rx char ready check) might be
delayed too much. This patch also adds the Kconfig option
CONFIG_CYCLIC_MAX_CPU_TIME_US, which configures the max allowed time
for such a cyclic function. If it's execution time exceeds this time,
this cyclic function will get removed from the cyclic list.
How is this cyclic functionality executed?
This patchset integrates the main function responsible for calling all
registered cyclic functions cyclic_run() into the common WATCHDOG_RESET
macro. This guarantees that cyclic_run() is executed very often, which
is necessary for the cyclic functions to get scheduled and executed at
their configured periods.
This cyclic infrastructure will be used by a board specific function on
the NIC23 MIPS Octeon board, which needs to check periodically, if a
PCIe FLR has occurred.
Ideas how to continue:
One idea is to rename WATCHDOG_RESET to something like SCHEDULE and
move the watchdog_reset call into this cyclic infrastructure as well.
Or to perhaps move the shell UART RX ready polling to a cyclic
function.
It's also possible to extend the "cyclic" command, to support the
creation of periodically executed shell commands (for testing etc).
Stefan Roese [Fri, 2 Sep 2022 11:57:54 +0000 (13:57 +0200)]
cyclic: Add a simple test
Add a test for cyclic function registration and activation.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Fri, 2 Sep 2022 11:57:53 +0000 (13:57 +0200)]
cyclic: Add documentation
Add documentation for the cyclic function infrastructure, including the
cyclic command.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Aaron Williams [Fri, 2 Sep 2022 11:57:52 +0000 (13:57 +0200)]
mips: octeon_nic23: Add PCIe FLR fixup via cyclic infrastructure
This patch adds a fixup function related to a PCIe FLR (Function Level
Reset) problem on the NIC23 PCIe board. This function is imported from
the Marvell Octeon 2013 U-Boot version as a (nearly) verbatim copy. It
uses the newly introduced cyclic infrastructure, so that this function
gets called every 100us, which is needed to detect this FLR issue.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Fri, 2 Sep 2022 11:57:51 +0000 (13:57 +0200)]
cyclic: Add 'cyclic list' and 'cyclic demo' commands
This patch adds the cyclic command, which currently only supports the
'list' subcommand, to list all currently registered cyclic functions.
Here an example:
=> cyclic list
function: cyclic_demo, cpu-time: 7010 us, frequency: 99.80 times/s
function: cyclic_demo2, cpu-time: 1 us, frequency: 1.13 times/s
As you can see, the cpu-time is accounted, so that cyclic functions
that take too long might be discovered. Additionally the frequency is
logged.
The 'cyclic demo' commands registers the cyclic_demo() function to
be executed all 'cycletime_ms' milliseconds. The only thing this
function does is delaying by 'delay_us' microseconds.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Fri, 2 Sep 2022 11:57:50 +0000 (13:57 +0200)]
cyclic: Integrate cyclic functionality at bootup in board_r/f
This patch adds a call to cyclic_init() to board_f/r.c, enabling the
common cyclic infrastructure. After this it's possible to add cyclic
functions via cyclic_register().
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Fri, 2 Sep 2022 11:57:49 +0000 (13:57 +0200)]
cyclic: Integrate cyclic infrastructure into WATCHDOG_RESET
This patch integrates the main function responsible for calling all
registered cyclic functions cyclic_run() into the common WATCHDOG_RESET
macro. This guarantees that cyclic_run() is executed very often, which
is necessary for the cyclic functions to get scheduled and executed at
their configured periods.
If CONFIG_WATCHDOG is not enabled, only cyclic_run() without calling
watchdog_reset(). This guarantees that the cyclic functionality does not
rely on CONFIG_WATCHDOG being enabled.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Fri, 2 Sep 2022 11:57:48 +0000 (13:57 +0200)]
cyclic: Add basic support for cyclic function execution infrastruture
Add the basic infrastructure to periodically execute code, e.g. all
100ms. Examples for such functions might be LED blinking etc. The
functions that are hooked into this cyclic list should be small timewise
as otherwise the execution of the other code that relies on a high
frequent polling (e.g. UART rx char ready check) might be delayed too
much. This patch also adds the Kconfig option
CONFIG_CYCLIC_MAX_CPU_TIME_US, which configures the max allowed time
for such a cyclic function. If it's execution time exceeds this time,
this cyclic function will get removed from the cyclic list.
How is this cyclic functionality executed?
The following patch integrates the main function responsible for
calling all registered cyclic functions cyclic_run() into the
common WATCHDOG_RESET macro. This guarantees that cyclic_run() is
executed very often, which is necessary for the cyclic functions to
get scheduled and executed at their configured periods.
This cyclic infrastructure will be used by a board specific function on
the NIC23 MIPS Octeon board, which needs to check periodically, if a
PCIe FLR has occurred.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Fri, 2 Sep 2022 11:57:47 +0000 (13:57 +0200)]
time: Import time_after64() and friends from Linux
When using us times it makes sense to use 64bit variables for storage.
The currently implemented time_after() and friends functions only handle
32bit variables. This patch now includes the 64bit variants as well
from Linux. This will be used by the upcoming generic cyclic function
infrastructure.
These macros were copied from include/linux/jiffies.h of Linux 5.18.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 13 Sep 2022 19:55:33 +0000 (15:55 -0400)]
Merge branch '2022-09-13-add-aspeed-spi-controller' into next
To quote the author:
This patch series aims to porting ASPEED FMC/SPI memory controller
driver with spi-mem interface. spi-mem dirmap framework is also
synchronized from Linux. These patches have been verified on
AST2600, AST2500 and AST2400 EVBs.
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:15 +0000 (17:01 +0800)]
mtd: spi-nor-ids: Add Winbond W25Q512JVQ ID
Add ID for Winbond W25Q512JVQ device which is supported
on AST2600 EVB by default.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:14 +0000 (17:01 +0800)]
spi: aspeed: Clock frequency adjustment support
Driver can configure the SPI clock frequnecy to the
target value of "spi-max-frequency" property in
the device tree. The frequency is divided from HCLK,
200MHz. Usually, the ASPEED SPI clock frequency range
is between 12.5MHz and 100MHz. On AST2600, the lowest
SPI clock frequency can be about 780kHz.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:13 +0000 (17:01 +0800)]
spi: aspeed: Support customized decoded address ranges
If "decoded-ranges" is defined in the device tree, the
driver will apply the decoded address ranges from this
property to the controller during probe stage.
This patch refers to the following OpenBMC u-boot patch.
https://patchwork.ozlabs.org/project/openbmc/list/?series=306969
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:12 +0000 (17:01 +0800)]
spi: aspeed: Adjust decoded range size support
There are some known HW problems about decoded
range register configurations on existing AST2500 and
AST2600 platforms. Additional callback function,
adjust_decoded_sz, is added to solve these problems
on each platform. Besides, aspeed_spi_trim_decoded_size
function is added to modify overall decoded address
size for fitting the maximum AHB decoded size.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:11 +0000 (17:01 +0800)]
configs: aspeed: Enable CONFIG_SPI_DIRMAP
Enable CONFIG_SPI_DIRMAP on ASPEED platforms.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:10 +0000 (17:01 +0800)]
spi: aspeed: SPI dirmap read support
From the HW point of view, the performance of
command read mode is greater than user mode slightly.
Thus, dirmap read framework is introduced to achieve
this goal. In dirmap_create, command read mode is
configured. Usually, the decoded address area with flash
size is assigned to each CS. CPU can thus access the
SPI flash as normal memory in dirmap_read function.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:09 +0000 (17:01 +0800)]
mtd: spi-nor: Use spi-mem dirmap API
This adds support for the dirmap API to the spi-nor subsystem, as
introduced in Linux commit
df5c21002cf4 ("mtd: spi-nor: use
spi-mem dirmap API").
This patch is synchronize from the following patch
https://patchwork.ozlabs.org/project/uboot/patch/
20210205043924.149504-4-seanga2@gmail.com/
The corresponding Linux kernel SHA1 is
df5c21002cf4.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:08 +0000 (17:01 +0800)]
spi-mem: Add dirmap API from Linux
This adds the dirmap API originally introduced in
Linux commit
aa167f3fed0c
("spi: spi-mem: Add a new API to support direct mapping").
This also includes several follow-up patches and fixes.
Changes from Linux include:
* Added Kconfig option
* Changed struct device to struct udevice
* Changed struct spi_mem to struct spi_slave
This patch is obtained from the following patch
https://patchwork.ozlabs.org/project/uboot/patch/
20210205043924.149504-3-seanga2@gmail.com/
The corresponding Linux kernel SHA1 is
aa167f3fed0c.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:07 +0000 (17:01 +0800)]
arm: dts: aspeed: Update SPI flash node settings
For both AST2500 and AST2600, there are three
SPI controllers, FMC(Firmware Memory Controller),
SPI1 and SPI2. The clock source is HCLK. Following
is the basic information for ASPEED SPI controller.
AST2500:
- FMC:
CS number: 3
controller reg: 0x1e620000 - 0x1e62ffff
decoded address: 0x20000000 - 0x2fffffff
- SPI1:
CS number: 2
controller reg: 0x1e630000 - 0x1e630fff
decoded address: 0x30000000 - 0x37ffffff
- SPI2:
CS number: 2
controller reg: 0x1e631000 - 0x1e631fff
decoded address: 0x38000000 - 0x3fffffff
AST2600:
- FMC:
CS number: 3
controller reg: 0x1e620000 - 0x1e62ffff
decoded address: 0x20000000 - 0x2fffffff
- SPI1:
CS number: 2
controller reg: 0x1e630000 - 0x1e630fff
decoded address: 0x30000000 - 0x3fffffff
- SPI2:
CS number: 3
controller reg: 0x1e631000 - 0x1e631fff
decoded address: 0x50000000 - 0x5fffffff
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:06 +0000 (17:01 +0800)]
spi: aspeed: Support AST2400 platform
Although AST2400 is EOL officially, in order to achieve
sustainability and completeness, AST2400 part is added.
For AST2400,
- Five CSs are supported by FMC controller.
- SPI1 controller only supports single CS and there is
no address segment address register. The CE control
register of SPI1 is located at the offset 0x04 and
the 4-byte address mode control bit is bit 13 of
this register.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:05 +0000 (17:01 +0800)]
configs: aspeed: Enable SPI flash features
- Enable ASPEED SPI controller driver.
- Enable SPI flash memory configurations.
- Enable configurations for SPI flash manufacturers
supported on both ASPEED AST2500 and AST2600 AVL.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:04 +0000 (17:01 +0800)]
spi: aspeed: Add ASPEED SPI controller driver
Add ASPEED BMC FMC/SPI memory controller driver with
spi-mem interface for AST2500 and AST2600 platform.
There are three SPI memory controllers embedded in an ASPEED SoC.
- FMC: Named as Firmware Memory Controller. After AC on, MCU ROM
fetches initial device boot image from FMC chip select(CS) 0.
- SPI1: Play the role of a SPI Master controller. Or, there is a
dedicated path for HOST(X86) to access its BIOS flash mounted
under BMC. spi-aspeed-smc.c implements the control sequence when
SPI1 is a SPI master.
- SPI2: It is a pure SPI flash controller. For most scenarios, flashes
mounted under it are for pure storage purpose.
ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode.
Three types of command mode are supported, normal mode, command
read/write mode and user mode.
- Normal mode: Default mode. After power on, normal read command 03h or
13h is used to fetch boot image from SPI flash.
- AST2500: Only 03h command can be used after power on
or reset.
- AST2600: If FMC04[6:4] is set, 13h command is used,
otherwise, 03h command.
The address length is decided by FMC04[2:0].
- Command mode: SPI controller can send command and address
automatically when CPU read/write the related remapped
or decoded address area. The command used by this mode
can be configured by FMC10/14/18[23:16]. Also, the
address length is decided by FMC04[2:0]. This mode will
be implemented in the following patch series.
- User mode: It is a traditional and pure SPI operation, where
SPI transmission is controlled by CPU. It is the main
mode in this patch.
Each SPI controller in ASPEED SoC has its own decoded address mapping.
Within each SPI controller decoded address, driver can assign a specific
address region for each CS of a SPI controller. The decoded address
cannot overlap to each other. With normal mode and command mode, the
decoded address accessed by the CPU determines which CS is active.
When user mode is adopted, the CS decoded address is a FIFO, CPU can
send/receive any SPI transmission by accessing the related decoded
address for the target CS.
This patch only implements user mode initially. Command read/write
mode will be implemented in the following patches.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:03 +0000 (17:01 +0800)]
pinctrl: aspeed: FWSPICS1 and SPI1CS1 pin support
Add FWSPICS1 and SPI1CS1 in AST2500 pinctrl group.
On AST2500 EVB, FWSPICS1 can be supported by default.
An extra jumper, J45, should be configured before
enabling SPI1CS1.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:02 +0000 (17:01 +0800)]
clk: aspeed: Get HCLK frequency support
User can get correct HCLK frequency during driver probe stage
by adding the following configuration in the device tree.
"clocks = <&scu ASPEED_CLK_AHB>".
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tom Rini [Tue, 13 Sep 2022 13:34:12 +0000 (09:34 -0400)]
Merge tag 'xilinx-for-v2023.01-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2023.01-rc1
cmd:
- bdinfo - guard LMB code to run only when LMB is enabled
timer:
- convert arm twd timer to DM
power-domain:
- Skip loading config object for Versal
xilinx:
- Fix logic when dfu_alt_info is generated
- Define only mmc devnum not partition
- Add xlnx prefix to GEM compatible string
- Add missing tca6416 to zynqmp SC - vck190
- Add env redund offset
- Enable CMD_GREPENV/SETEXPR by default
- Move board_get_usable_ram_top() to common location
- Add support for SOC detection
net/gem:
- Check rate before setting it up
microblaze:
- drop CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE
- Show cache size in bdinfo
spi:
- cadence_qspi: driver updates
- zynqmp_gqspi: driver updates
- zynqmp_gqspi: Add tap delays for Versal
zynq:
- Enable mkeficapsule compilation
- Use CONFIG_SPL_FS_LOAD_PAYLOAD_NAME for dfu_alt_info
- Align bss and end of u-boot image to 64bits
- Align qspi node name with Linux kernel
- DT: List OCM memory
zynqmp:
- Fix AES cache handling with a user provided key
- SOM: Add mtd partition for secure OS storage area
- Add ref_clk property for REFCLKPER calculation
- Fix mdio bus description for vck190-sc
xilinx-mini:
- Remove unneeded configs
- Disable LMB
versal:
- Enable i2c mux pca954x by default
- Define CONFIG_CQSPI_REF_CLK
- Enable power domain driver
- Enable zynqmp_gqspi driver
Tom Rini [Tue, 13 Sep 2022 12:59:11 +0000 (08:59 -0400)]
Merge branch '2022-09-12-update-pytests-for-more-parellel-support' into next
To quote the author:
This series makes a further attempt to get closer to having all tests
run in parallel. It introduces a new 'make pcheck' option which runs
tests in parallel, skipping those that are not compatible.
A number of fixes are included for existing tests. The vboot test is
updated to only run a single scenario in 'quick' mode.
This makes use of pytest's parallel-testing features. The resulting
times (including incremental building with LTO) on a 16-core machine are
as follows:
make pcheck - 1 minute 6 seconds
make qcheck - 3 minutes
make check - 5 minutes 15 seconds
Note that this is not a fair comparison, since 'make pcheck' omits a
number of tests, even more than 'make qcheck'.
Michal Simek [Tue, 6 Sep 2022 10:40:41 +0000 (12:40 +0200)]
xilinx: common: Add support for SOC detection
Code supports board detection based on information available in EEPROM in
legacy or FRU format. But this is not enough for emulation and simulation
systems which are lacking these identification EEPROMs. But SOC itself has
normally registers for SOC identification. Based on them it is possible to
compose detected name. That's why prepare infrastructure in common location
for SOC platform detection which is called before board platform detection.
SOC platform detection shouldn't detect real silicon and should fallback to
current existing mechanism to identify boards based on EEPROMs.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/329a8da338927b082e26a958bf69bb18af072420.1662460837.git.michal.simek@amd.com
Michal Simek [Tue, 6 Sep 2022 10:39:11 +0000 (12:39 +0200)]
xilinx: Fix mdio bus description for vck190-sc
Current behavior is that eth_phy_get_mdio_bus
Net: FEC: can't find phy-handle
ZYNQ GEM:
ff0b0000, mdio bus
ff0b0000, phyaddr 0, interface sgmii
eth0: ethernet@
ff0b0000
Net:
ZYNQ GEM:
ff0b0000, mdio bus
ff0b0000, phyaddr 0, interface sgmii
eth0: ethernet@
ff0b0000
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5b7da5808136b3f579c0cf7a3431b56c758655e9.1662460749.git.michal.simek@amd.com
Michal Simek [Tue, 6 Sep 2022 10:38:34 +0000 (12:38 +0200)]
ARM: zynq: DT: List OCM memory
Description OCM with mmio-sram driver. In 99% use cases OCM is mapped high
that's why it is placed on fixed location.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a951dbe885640197efe3e91bb9fa5caedb54b387.1662460712.git.michal.simek@amd.com
Michal Simek [Tue, 6 Sep 2022 10:35:42 +0000 (12:35 +0200)]
ARM: zynq: Align qspi node name with Linux kernel
Nodes should follow generic rules where compatible and reg properties
should be listed on the top of node. That's why sync it up.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/922dca6227cb0aa4f79e6d3595c5f280ba020684.1662460540.git.michal.simek@amd.com
Ashok Reddy Soma [Thu, 25 Aug 2022 12:59:06 +0000 (06:59 -0600)]
arm64: versal: Enable zynqmp_gqspi driver
Versal supports gqspi ip, so enable zynqmp_gqspi driver for Versal
platforms.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-7-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ashok Reddy Soma [Thu, 25 Aug 2022 12:59:05 +0000 (06:59 -0600)]
spi: zynqmp_qspi: Code alignment
Few lines are extented to next line though they can fit in 80 character
limit, align them to single line. No functional change.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-6-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ashok Reddy Soma [Thu, 25 Aug 2022 12:59:04 +0000 (06:59 -0600)]
spi: zynqmp_gqspi: Fix issue of reading more than 32bits length
As the flash sizes are increasing day by day, QSPI can have devices of
size > 512MB. In qspi driver we are trying to read all the data at once
using DMA.
The DMA descriptor destination size is only 29bits long.
QSPIDMA_DST_SIZE 0xFF0F0804
BITS: 1:0 Reserved to keep word alignment
BITS: 28:2 Number of 4-byte words the DMA will transfer
BITS: 31:29 Reserved: Returns 0 when read, writes ignored
So we can only transfer data of 0x1FFFFFF0(512MB minus 4bytes) bytes.
Anything above will overflow this register and will ignore higher bits
above 29 bits.
Change the DMA functionality if the requested size is greater than or
equal to 512MB to read 256MB chunks.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-5-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ashok Reddy Soma [Thu, 25 Aug 2022 12:59:03 +0000 (06:59 -0600)]
spi: zynqmp_gqspi: Add support for IO mode
Add support for io-mode transfers. This is necessary for UBIFS to work
properly with spi-nor devices. The driver will work in IO mode when
"has-io-mode" is passed from device tree instead of DMA.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-4-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Michal Simek [Thu, 25 Aug 2022 12:59:02 +0000 (06:59 -0600)]
arm64: versal: Define zynqmp_mmio_write() for versal
GQSPI driver is using it but this function is never called for Versal
because it is removed by linker. But function should be declared to avoid
this build warning:
drivers/spi/zynqmp_gqspi.c: In function 'zynqmp_qspi_set_tapdelay':
drivers/spi/zynqmp_gqspi.c:378:3: warning: implicit declaration of function
'zynqmp_mmio_write' [-Wimplicit-function-declaration]
378 | zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST,
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ashok Reddy Soma [Thu, 25 Aug 2022 12:59:01 +0000 (06:59 -0600)]
spi: zynqmp_gqspi: Add tap delays for Versal
Add tap delays for Versal platform and re-align the tapdelays code.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ashok Reddy Soma [Wed, 24 Aug 2022 11:38:47 +0000 (05:38 -0600)]
spi: cadence-qspi: Use priv instead of plat across the driver
As per driver model we should enumerate plat structure only in
of_to_plat() and should be used only in probe(). Copy required
plat structure info into priv structure in probe() and use priv
structure across the driver. So replace plat with priv structure across
the driver.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220824113847.7482-4-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ashok Reddy Soma [Wed, 24 Aug 2022 11:38:46 +0000 (05:38 -0600)]
spi: cadence_qspi: Call read_setup for STIG_READ
In cadence_spi_read_id we are using STIG mode to read flash id's.
Call cadence_qspi_apb_command_read_setup() to setup cmd, addr and data
bus width properly before cadence_qspi_apb_command_read().
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220824113847.7482-3-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ashok Reddy Soma [Wed, 24 Aug 2022 11:38:45 +0000 (05:38 -0600)]
spi: cadence-qspi: Correct flash reset function name
In cadence_spi_probe, cadence_qspi_versal_flash_reset() is called to reset
the flash device. Looks like there is a mistake in previous series of
patches where it is defined as cadence_spi_versal_flash_reset() but
called as cadence_qspi_versal_flash_reset. Since there is a weak function
defined with the same name this issue was not caught.
Fix the issue by renaming cadence_spi_versal_flash_reset as
cadence_qspi_versal_flash_reset().
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220824113847.7482-2-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ovidiu Panait [Mon, 29 Aug 2022 17:02:05 +0000 (20:02 +0300)]
microblaze: add arch_print_bdinfo() implementation
Allow bdinfo command to print icache/dcache information:
U-Boot-mONStR> bdinfo
boot_params = 0x00000000
DRAM bank = 0x00000000
-> start = 0x04000000
-> size = 0x04000000
flashstart = 0x00000000
flashsize = 0x00000000
flashoffset = 0x00000000
baudrate = 9600 bps
relocaddr = 0x07f76000
reloc off = 0x02f76000
Build = 32-bit
current eth = unknown
ethaddr = (not set)
IP addr = <NULL>
fdt_blob = 0x07fec7e0
new_fdt = 0x00000000
fdt_size = 0x00000000
lmb_dump_all:
memory.cnt = 0x1
memory[0] [0x4000000-0x7ffffff], 0x04000000 bytes flags: 0
reserved.cnt = 0x1
reserved[0] [0x7e94b8c-0x7ffffff], 0x0016b474 bytes flags: 0
devicetree = embed
icache = 32 KiB
icache line = 4 Bytes
dcache = 32 KiB
dcache line = 4 Bytes
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220829170205.1274484-4-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ovidiu Panait [Mon, 29 Aug 2022 17:02:04 +0000 (20:02 +0300)]
cmd: bdinfo: introduce bdinfo_print_size() helper
Add bdinfo_print_size() helper to display size variables (such as cache
sizes) in bdinfo format. The size is printed as "xxx Bytes", "xxx KiB",
"xxx MiB", "xxx GiB", etc as needed;
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Jason Liu <jason.hui.liu@nxp.com>
Link: https://lore.kernel.org/r/20220829170205.1274484-3-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ovidiu Panait [Mon, 29 Aug 2022 17:02:03 +0000 (20:02 +0300)]
cpu: microblaze: add error handling in microblaze_cpu_get_desc()
Check snprintf() return value for errors.
Make microblaze_cpu_get_desc() directly return snprintf() error code if
ret < 0. Otherwise, if the return value is greater than or equal to size,
the resulting string is truncated, so return -ENOSPC.
Fixes:
816226d27e ("cpu: add CPU driver for microblaze")
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220829170205.1274484-2-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Ovidiu Panait [Mon, 29 Aug 2022 17:02:02 +0000 (20:02 +0300)]
microblaze: drop CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE
These macros are not used anymore in microblaze code since commit
f113d7d303467 ("Convert CONFIG_SPL_STACK to Kconfig"), so remove them.
Fixes:
f113d7d303467 ("Convert CONFIG_SPL_STACK to Kconfig")
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220829170205.1274484-1-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Michal Simek [Fri, 26 Aug 2022 08:30:47 +0000 (10:30 +0200)]
net: gem: Check rate before setting it up
On QEMU setting rate for fixed clock is failing. That's why check a rate
first if the rate is the same there is no need to ask for the change.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/bc465ffd4904bfd65208b782daa06732b915db54.1661502645.git.michal.simek@amd.com
Michal Simek [Tue, 6 Sep 2022 10:41:34 +0000 (12:41 +0200)]
xilinx: versal: Disable LMB for mini configurations
There shouldn't be a reason to have LMB on for these configurations.
LMB was already disabled for ZynqMP by commit
0063487a5b60 ("configs:
zynqmp: Disable LMB for mini u-boot").
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/17d1e9b50b2fd032352911f94f4f213828e0a3f7.1662460892.git.michal.simek@amd.com
Michal Simek [Thu, 25 Aug 2022 12:23:10 +0000 (14:23 +0200)]
arm64: xilinx: Move board_get_usable_ram_top() to common location
The commit
ce39ee28ec31 ("zynqmp: Do not place u-boot to reserved memory
location") adds functionality for ZynqMP to read reserved memory node and
do not place U-Boot to reserved location. This functionality is generic
across all Xilinx SOCs that's why move it to common location to be used by
all Xilinx SOCs.
On zynq platform this is also fixing issue where U-Boot was placed to
locating which was reserved already which ends up with error message
"ERROR: reserving fdt memory region failed (addr=
30000000 size=
10000000
flags=4)" which is shown when bdinfo is called.
Tested on vck190, zcu102, zc706 and kc705 to cover all platforms.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b0817807912f7c7af6a8e1cf9ee04e5ab5de5f6a.1661430188.git.michal.simek@amd.com
Michal Simek [Wed, 31 Aug 2022 09:28:59 +0000 (11:28 +0200)]
ARM: zynq: Align bss and end of u-boot image to 64bits
The main reason is that DT memory reserved code is expecting DT to be 64bit
aligned. For more information take a look at commit
5bd5ee02b23b ("xilinx:
zynqmp: Check that DT is 64bit aligned").
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9f3688cda188d8ea0b462df2aa08a10ddcc9c149.1661938136.git.michal.simek@amd.com
Michal Simek [Wed, 24 Aug 2022 11:28:35 +0000 (13:28 +0200)]
xilinx: Enable CMD_GREPENV/SETEXPR by default
Enable both of these commands in Xilinx SoCs to be able to use them in boot
scripts.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1a612be7e09e9bc502f30e1f025441ccf8accba5.1661340513.git.michal.simek@amd.com
T Karthik Reddy [Wed, 24 Aug 2022 11:23:26 +0000 (13:23 +0200)]
xilinx: Add env redund offset
ENV_OFFSET_REDUND config is by default set to 0 for flashes. Saving the env
variables is overwriting data at 0 offset, which is wrong. So add default
redund env offset for Zynq, ZynqMP, Versal and microblaze platforms.
Configured ENV_OFFSET_REDUND offsets by ENV_OFFSET + (2 * ENV_SIZE).
In case of versal, we configured ENV_OFFSET_REDUND at 0x7F00000 instead
of 0x7F80000. As BOOT_SCRIPT_OFFSET is already configured at 0x7F80000.
Added ENV_OFFSET_REDUND in Kconfig for microblaze due to dependency of
ENV_IS_IN_SPI_FLASH config.
Below table specifies platform specific env and env redund offsets.
PLAT ENV_OFFSET ENV_OFFSET_REDUND
---- ---------- -----------------
ZYNQ 0xE0000 0xE40000
ZYNQMP 0x1E00000 0x1E80000
VERSAL 0x7F40000 0x7F00000
MICROBLAZE 0x1080000 0x10C0000
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/92656dc08f0f5a749d62b71ca6e77fe1be72e9e0.1661340204.git.michal.simek@amd.com
Piyush Mehta [Tue, 23 Aug 2022 13:03:31 +0000 (15:03 +0200)]
arm64: zynqmp: add ref_clk property for REFCLKPER calculation
Added ref_clk 'ref' property for GUCTL_REFCLKPER and GFLADJ_REFCLK_FLADJ
calculation. This property configure correct value for SOF/ITP counter
and period of ref_clk.
This patch adds 'ref' property for both dwc3_0 and dwc3_1 cores.
Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/417545b948ea12a9301a5e80851f98523be2b443.1661259809.git.michal.simek@amd.com
Michal Simek [Tue, 23 Aug 2022 13:00:25 +0000 (15:00 +0200)]
arm64: zynqmp: Add missing tca6416 to zynqmp SC
Add missing tca6416 i2c gpio controller to SC dts file.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a19c191d0dffb213d9dc8809d22728d79cf73a22.1661259623.git.michal.simek@amd.com
Harini Katakam [Tue, 23 Aug 2022 12:59:20 +0000 (14:59 +0200)]
arm: dts: Add xlnx prefix to GEM compatible string
cdns,zynq/zynqmp were recentle deprecated in Linux in favour of xlnx
prefix. Add this new compatible string and retain the existing string for
compatibility with uboot drivers.
Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a38b1b55132fc026cc09224dba61e42fd03b1a36.1661259558.git.michal.simek@amd.com
Amit Kumar Mahapatra [Tue, 23 Aug 2022 08:18:03 +0000 (10:18 +0200)]
arm64: zynqmp: Add mtd partition for secure OS storage area
Update MTD partitions of Kria device trees to allocate 128KB of QSPI
memory for secure OS. Increased "SHA256" partition size & changed
starting address of "User" partition to accommodate the new partition
"Secure OS Storage"
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9cc64b8c731d11439de73d0af54c65080068f00b.1661242681.git.michal.simek@amd.com
Michal Simek [Tue, 9 Aug 2022 14:32:54 +0000 (16:32 +0200)]
xilinx: Define only mmc devnum not partition
The commit
53b406369e9d ("DFU: Check the number of arguments and argument
string strictly") added strict control over string that 0:1 partition
definition is not valid anymore that's why use only device number without
partition ID. Device is specified by 2nd parameter and partition by 3rd.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/840eca944f4f2abeeb63b5d724f9ba5fe9a9213b.1660055571.git.michal.simek@amd.com
Michal Simek [Tue, 9 Aug 2022 14:32:53 +0000 (16:32 +0200)]
xilinx: zynq: Use CONFIG_SPL_FS_LOAD_PAYLOAD_NAME for dfu_alt_info
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME stores the name of firmware file to be
loaded by SPL. Name can be selected via Kconfig that's why use the macro.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/601fbc2dfd16b4708fc6b5f86954e10add43334e.1660055571.git.michal.simek@amd.com
Michal Simek [Tue, 9 Aug 2022 14:32:52 +0000 (16:32 +0200)]
xilinx: Fix logic when dfu_alt_info is generated
Generate dfu_alt_info only when it is not defined.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/464e4b325c644e52a660df9cf44eeb4d80427f6a.1660055571.git.michal.simek@amd.com
Michal Simek [Tue, 9 Aug 2022 14:32:51 +0000 (16:32 +0200)]
xilinx: zynq: Enable mkeficapsule tools compilation
Zynq can use efi capsule infrastructure that's why enable it by default.
For capsule generation for zynq you can use:
pushd spl
../tools/mkeficapsule -g "
1ba29a15-9969-40aa-b424-
e86121618664" boot.bin \
--index 1 ../capsule1.bin
popd
./tools/mkeficapsule -g "
1a5178f0-87d3-4f36-ac63-
3b31a23be305" u-boot.img \
--index 2 capsule2.bin
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a8194ecfa7932f2d8ada5ee508b2a026c782f15e.1660055571.git.michal.simek@amd.com
Ashok Reddy Soma [Fri, 5 Aug 2022 09:19:58 +0000 (11:19 +0200)]
xilinx: versal: Define CONFIG_CQSPI_REF_CLK
With commit
55b3ba4c2ba4 ("spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK
to Kconfig") CONFIG_CQSPI_REF_CLK is moved to Kconfig.
The static value via Kconfig is a fallback option in case of clock
framework is not enabled or fails for some reason.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fe7c38a19e878c307d5b75311bbfd8cf6c1f601e.1659691195.git.michal.simek@amd.com
Ashok Reddy Soma [Fri, 5 Aug 2022 09:19:57 +0000 (11:19 +0200)]
xilinx: versal: Enable power domain driver
Enable power domain driver to request node for all the IP's that are
enabled in DT.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/dbed54df622d647b8d520d8ce5289cd69ba66e0b.1659691195.git.michal.simek@amd.com
Ashok Reddy Soma [Fri, 5 Aug 2022 09:19:56 +0000 (11:19 +0200)]
firmware: zynqmp: Skip loading config object for Versal
SET_CONFIGURATION is not yet implemented for Versal platforms. Skip
loading config object for Versal until support is added.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/eb7ef6c6de36a1f7d056de43042f96fe3639f18e.1659691195.git.michal.simek@amd.com
Simon Glass [Sat, 6 Aug 2022 23:51:59 +0000 (17:51 -0600)]
Makefile: Add a pcheck option to run tests in parallel
Running tests in parallel is much faster, e.g. 15 seconds to run the tests
on sandbox (only), instead of 100 seconds (on a 16-core machine). Add a
'make pcheck' option to access this feature.
Note that the tools/ tests still run each tool's tests once after the
other, although within that, they do run in parallel. So for example,
the buildman tests run in parallel, then the binman tests run in
parallel. There would be a signiificant advantage to running them all
in parallel together, but that would require a large amount of
refactoring, e.g. with more use of pytest fixtures.
Update the documentation to represent the current state.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 6 Aug 2022 23:51:58 +0000 (17:51 -0600)]
dtoc: Drop sys.exit() in test_fdt
This breaks using pytest to run the tests. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 6 Aug 2022 23:51:57 +0000 (17:51 -0600)]
test/py: Support --build when running tests in parallel
At present when -n is used, all workers try to build U-Boot at once.
Add a lock to ensure that only one of them builds, with the others using
the build that is produced.
The lock file is removed on startup.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 6 Aug 2022 23:51:56 +0000 (17:51 -0600)]
test/py: Move U-Boot building into a function
This is a lot of code in a function that is too long. Split out the
building code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 6 Aug 2022 23:51:55 +0000 (17:51 -0600)]
test: Refactor arg parsing for the run script
Tidy up this code a little. Also use '-k' consistently, since -m is more
limited in what it can accept.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 6 Aug 2022 23:51:54 +0000 (17:51 -0600)]
test: Make test_gpio_read() independent
This assumes that the GPIO starts as 0 but it does not if
test_gpio_input() ran first and test_gpio_exit_statuses() was skipped.
This can happen when running tests in parallel.
Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 6 Aug 2022 23:51:53 +0000 (17:51 -0600)]
test: Mark test_gpt tests as slow
Mark all the tests in this file as slow, since they take a while.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 6 Aug 2022 23:51:52 +0000 (17:51 -0600)]
test: Mark all but the first vboot test as slow
When doing a quick check we don't need to run all the vboot tests. Just
run the first one, which is enough to catch most problems.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 6 Aug 2022 23:51:51 +0000 (17:51 -0600)]
test: Make test_efi_bootmgr() single-threaded
This test seems to fail when run in parallel. Mark it single-threaded to
avoid any problems.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 6 Aug 2022 23:51:50 +0000 (17:51 -0600)]
test: Make test_sqfs_ls() single-threaded
This test seems to interfere with the other test in this file. Mark it
single-threaded to avoid any problems.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 6 Aug 2022 23:51:49 +0000 (17:51 -0600)]
test: Update FIT tests to run in parallel
Use a different temporary dir for each test, to allow them to run in
parallel.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 6 Aug 2022 23:51:48 +0000 (17:51 -0600)]
test: Make test_bind_unbind_with_uclass() single-threaded
This test seems to rely on the other test in this file. Mark it
single-threaded to avoid any problems.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 6 Aug 2022 23:51:47 +0000 (17:51 -0600)]
test/py: Allow tests to be marked single-threaded only
Add a new 'singlethread' marker to allow tests to be skipped when running
in parallel.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 6 Aug 2022 23:51:46 +0000 (17:51 -0600)]
test: Fix bootm_test_subst_var() running independently
This test relies on the silent_linux env variable being set. Add this
to the code so it can run without relying on other bootm tests having been
run first.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 6 Aug 2022 23:51:45 +0000 (17:51 -0600)]
test: Fix test_pinmux to run in parallel
At present test_pinmux_status() assumes that test_pinmux_dev() has run
beforehand. Drop this assumption so we can run the tests in parallel.
Signed-off-by: Simon Glass <sjg@chromium.org>
Michal Simek [Tue, 6 Sep 2022 10:41:10 +0000 (12:41 +0200)]
xilinx: zynq: Disable LMB for mini configurations
There shouldn't be a reason to have LMB on for these configurations.
LMB was already disabled for ZynqMP by commit
0063487a5b60 ("configs:
zynqmp: Disable LMB for mini u-boot").
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/07d95f619a15672d1a234eddcfbb54c0ab382eaa.1662460867.git.michal.simek@amd.com
Ashok Reddy Soma [Fri, 5 Aug 2022 09:19:55 +0000 (11:19 +0200)]
xilinx: zynqmp: Disable LMB for mini u-boot
LMB is not required for mini u-boot which runs out of on chip memory.
Disable CONFIG_LMB from mini u-boot defconfig's.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/45fad28825f0f236ad45e700aca1f39afbb22236.1659691195.git.michal.simek@amd.com
Michal Simek [Wed, 7 Sep 2022 07:52:09 +0000 (09:52 +0200)]
cmd: bdinfo: Enable dumping lmb data when LMB is enabled
The commit
9996cea75f5a ("lmb/bdinfo: dump lmb info via bdinfo") added
support for dumping LMB information as the part of bdinfo. But code itself
should be called only when LMB is enabled.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/3e40c8bb77550dfca9f7eb48fe644a018d971411.1662537127.git.michal.simek@amd.com
Ashok Reddy Soma [Fri, 5 Aug 2022 09:19:54 +0000 (11:19 +0200)]
xilinx: zynqmp: Disable various configs for mini U-Boot
With 2022.01-rc3 upgrade, the size of the mini U-Boot increased and is
not able to fit in OCM. Hence disable unnecessary configs and make room.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/306b57818601fa3571bc75c4182f25aaa3f2a793.1659691195.git.michal.simek@amd.com
Michal Simek [Fri, 5 Aug 2022 09:19:53 +0000 (11:19 +0200)]
xilinx: versal: Enable i2c mux uclass with pca954x driver
Xilinx is using pca954x i2c muxes on a lot of boards that's why enable this
driver by default.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c090aea3436c7a4ebe698da6cbc70e70a14baae3.1659691195.git.michal.simek@amd.com
Janne Ylalehto [Tue, 16 Aug 2022 12:45:25 +0000 (15:45 +0300)]
xilinx: zynqmp: Fix AES with a user provided key
The user provided key address was not flushed in struct aes because of
the flushing location in the function.
Signed-off-by: Janne Ylalehto <ylalehto@gmail.com>
Link: https://lore.kernel.org/r/20220816124525.19671-1-ylalehto@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Stefan Herbrechtsmeier [Mon, 8 Aug 2022 14:53:31 +0000 (16:53 +0200)]
fpga: zynq: Remove post config info message for SPL
The drivers informs the user that a post config was not run after FPGA
configuration. This message is unnecessary in SPL because the
ps7_post_config function is called via spl_board_prepare_for_boot
function before jump_to_image_no_args function from board_init_r
function.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220808145331.24723-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Stefan Herbrechtsmeier [Fri, 5 Aug 2022 06:16:28 +0000 (08:16 +0200)]
zynq: Convert arm twd timer to DM driver
Move arm twd timer driver from zynq to generic location.
DM timer drivers are designed differently to original driver. Timer is
counting up and not down.
Information about clock rates are find out in timer_pre_probe() that's
why there is no need to get any additional information from DT in the
driver itself (only register offset).
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Tom Rini [Sat, 3 Sep 2022 01:51:21 +0000 (21:51 -0400)]
Merge branch '2022-09-02-assorted-improvements' into next
- DM RTC improvements that should help in CI, allow disabling LTO from
the make line, add extension (cape, etc) support to distro bootcmd,
add a pause command and re-enable ARM v4T support.
Simon Glass [Mon, 1 Aug 2022 13:58:48 +0000 (07:58 -0600)]
dm: rtc: Try to handle the localtime() race
At present the sandbox timer uses localtime() which can jump around twice
a year when daylight-saving time changes.
It would be tricky to make use of gmtime() since we still need to present
the time in local time, as seems to be required by U-Boot's RTC interface.
The problem can only happen once, so use a loop to detect it and try
again. This should be sufficient to detect either a change in the 'second'
value, or a daylight-saving change. We can assume that the latter also
incorporates a 'second' change, so there is no need to loop more than
twice.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 1 Aug 2022 13:58:47 +0000 (07:58 -0600)]
dm: rtc: Try to avoid a race in rtc_set_get test
It seems that the time can change in between getting it and reading the
offset. Check for this and try again if this happens.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 1 Aug 2022 13:58:46 +0000 (07:58 -0600)]
dm: rtc: Avoid a race in the rtc_reset test
Since resetting the RTC on sandbox causes it to read the base time from
the system, we cannot rely on this being unchanged since it was last read.
Allow for a one-second delay.
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Fixes: https://source.denx.de/u-boot/u-boot/-/issues/4
Reported-by: Bin Meng <bmeng.cn@gmail.com>
Reported-by: Tom Rini <trini@konsulko.com>
Suggested-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 1 Aug 2022 13:58:45 +0000 (07:58 -0600)]
test: Allow running tests multiple times
Some tests can have race conditions which are hard to detect on a single
one. Add a way to run tests more than once, to help with this.
Each individual test is run the requested number of times before moving
to the next test. If any runs failed, a message is shown.
This is most useful when running a single test, since running all tests
multiple times can take a while.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 1 Aug 2022 13:58:44 +0000 (07:58 -0600)]
dm: rtc: Make use of ut_assertnonnull()
Use this (newish) macro since it is designed for the purpose of making
sure things are non-NULL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 3 Aug 2022 18:13:09 +0000 (12:13 -0600)]
ci: Add a test for a non-LTO build
Check that sandbox builds and runs tests OK with LTO disabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 3 Aug 2022 18:13:08 +0000 (12:13 -0600)]
Makefile: Allow LTO to be disabled for a build
LTO (Link-Time Optimisation) is an very useful feature which can
significantly reduce the size of U-Boot binaries. So far it has been
made available for selected ARM boards and sandbox.
However, incremental builds are much slower when LTO is used. For example,
an incremental build of sandbox takes 2.1 seconds on my machine, but 6.7
seconds with LTO enabled.
Add a NO_LTO parameter to the build, similar to NO_SDL, so it can be
disabled during development if needed, for faster builds.
Add some documentation about LTO while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Sergei Antonov [Sun, 21 Aug 2022 13:34:20 +0000 (16:34 +0300)]
arm: ARMv4 assembly compatibility
There is currently a problem that U-Boot can not work on ARMv4
because assembly imlementations of memcpy() and some other functions
use "bx lr" instruction that is not available on ARMv4 ("mov pc, lr"
should be used instead).
A working preprocessor-based solution to this problem is found in
arch/arm/lib/relocate.S. Move it to the "ret" macro in
arch/arm/include/asm/assembler.h and change all "bx lr" code
to "ret lr" in functions that may run on ARMv4. Linux source code
deals with this problem in the same manner.
v1 -> v2:
Comment update. Pointed out by Andre Przywara.
Signed-off-by: Sergei Antonov <saproj@gmail.com>
CC: Samuel Holland <samuel@sholland.org>
CC: Ye Li <ye.li@nxp.com>
CC: Simon Glass <sjg@chromium.org>
CC: Andre Przywara <andre.przywara@arm.com>
CC: Marek Vasut <marex@denx.de>
CC: Sean Anderson <sean.anderson@seco.com>
CC: Tom Rini <trini@konsulko.com>
Samuel Dionne-Riel [Thu, 18 Aug 2022 19:44:04 +0000 (15:44 -0400)]
cmd: Add pause command
This command is being introduced with the goal of allowing user-friendly
"generic use case" U-Boot builds to pause until user input under some
situations.
The main use case would be when a boot failure happens, to pause until
the user has had time to acknowledge the current state.
Tested using:
make && ./u-boot -v -T -c 'ut lib lib_test_hush_pause'
Signed-off-by: Samuel Dionne-Riel <samuel@dionne-riel.com>
Cc: Simon Glass <sjg@chromium.org>
Matwey V. Kornilov [Tue, 9 Aug 2022 15:54:07 +0000 (18:54 +0300)]
distro_bootcmd: Introduce support for extension command
Try to load required DTB overlays if the board supports extensions and
CONFIG_CMD_EXTENSION is enabled.
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Tom Rini [Fri, 2 Sep 2022 12:59:15 +0000 (08:59 -0400)]
Merge branch '2022-09-01-assorted-Kconfig-migrations' into next
- Assorted Kconfig migrations
Marek Vasut [Wed, 17 Aug 2022 13:07:14 +0000 (15:07 +0200)]
ARM: imx6: dh-imx6: Enable d-cache early in SPL
Enable d-cache early in SPL right after DRAM is started up.
This reduces U-Boot proper load time by 650ms when loaded
from SPI NOR.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Philip Oberfichtner <pro@denx.de>
Philip Oberfichtner [Wed, 17 Aug 2022 13:07:13 +0000 (15:07 +0200)]
ARM: cache: Allow SPL to build cache-pl310.c
Introduce the new Kconfig symbol CONFIG_SPL_SYS_L2_PL310 to allow the
SPL to build cache-pl310.c.
Before this commit, the SPL could enable the PL310 L2 cache [1], but the
cache maintenance functions from cache-pl310.c were only useable for
non-SPL builds.
After enabling the cache one must be able to flush it, too. Thus this
commit allows cache-pl310.c to be included in the SPL build.
[1] See for example arch/arm/mach-imx/cache.c: v7_outer_cache_enable()
Signed-off-by: Philip Oberfichtner <pro@denx.de>