Aart Bik [Thu, 20 Oct 2022 23:01:37 +0000 (16:01 -0700)]
[mlir][sparse] lower number of entries op to actual code
works both along runtime path and pure codegen path
Reviewed By: Peiming
Differential Revision: https://reviews.llvm.org/D136389
Chris Bieneman [Fri, 21 Oct 2022 17:08:35 +0000 (12:08 -0500)]
[HLSL] Remove unused frontend-generated ID
As @python3kgae pointed out we're going to want to assign these IDs
after optimization so that we can remove unused resrouces. This patch
just removes the unused ID value from the frontend metadata, clang code
generation, and updates associated test cases.
Reviewed By: python3kgae
Differential Revision: https://reviews.llvm.org/D136271
Zequan Wu [Sat, 15 Oct 2022 00:15:02 +0000 (17:15 -0700)]
[LLDB][NativePDB] Improve ParseDeclsForContext time.
1. When we evaluating an expression multiple times and the searching scope is translation unit, ParseDeclsForContext iterates the type info and symbol info multiple times, though only the debug info is parsed once. Using llvm::call_once to make it only iterating and parsing once.
2. When evaluating an expression with identifier whose parent scope is a namespace, ParseDeclsForContext needs to search the entire type info to complete those records whose name is prefixed with the namespace's name and the entire symbol info to to parse functions and non-local variables. Caching parsed namespaces to avoid unnecessary searching.
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D136006
Sanjay Patel [Fri, 21 Oct 2022 16:22:40 +0000 (12:22 -0400)]
[InstCombine] allow more commutative matches for logical-and to select fold
When the common value is part of either select condition,
this is safe to reduce. Otherwise, it is not poison-safe
(with the select form of the pattern):
https://alive2.llvm.org/ce/z/FxQTzB
This is another patch motivated by issue #58313.
Zhixun Tan [Fri, 21 Oct 2022 17:09:52 +0000 (10:09 -0700)]
Let MLIR ODS also support generating build() functions without result type parameters when the op contains regions.
Regions were intentionally left unsupported: https://github.com/llvm/llvm-project/commit/
398f04aa49109fd5d1eff2c1946a2956dc6b29c6
Reviewed By: jpienaar
Differential Revision: https://reviews.llvm.org/D136232
Jeff Niu [Fri, 21 Oct 2022 17:04:07 +0000 (10:04 -0700)]
[mlir][index] Fix NoSideEffect->Pure
Jeff Niu [Tue, 11 Oct 2022 17:10:57 +0000 (10:10 -0700)]
[mlir][index] Add `convert-index-to-llvm` pass
This patch adds a lowering pass to convert `index` dialect ops to LLVM.
Depends on D135694
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D135697
Jeff Niu [Tue, 11 Oct 2022 16:47:00 +0000 (09:47 -0700)]
[mlir][index] Add folders for `index` ops
This patch adds folders for `index` dialect ops. Ths folders are
careful to ensure that fold results are valid on both 32-bit and 64-bit
targets.
Depends on D135689
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D135694
Jeff Niu [Tue, 11 Oct 2022 16:29:35 +0000 (09:29 -0700)]
[mlir][index] Add `index` dialect ops and attributes
This patch adds the definitions for the operations and attributes (just
one enum attribute) for the `index` dialect.
Depends on D135688
Reviewed By: rriddle, jpienaar
Differential Revision: https://reviews.llvm.org/D135689
Jeff Niu [Tue, 11 Oct 2022 00:02:44 +0000 (17:02 -0700)]
[mlir][index] Add boilerplate for the `index` dialect
This patch introduces the `index` dialect and associated boilerplate for
adding ops and enums (comparison predicates).
Reviewed By: rriddle, jpienaar, nicolasvasilache
Differential Revision: https://reviews.llvm.org/D135688
Fangrui Song [Fri, 21 Oct 2022 16:43:25 +0000 (09:43 -0700)]
[ELF] Suppress "duplicate symbol" when resolving STB_WEAK and STB_GNU_UNIQUE in different COMDATs
```
template <typename T> struct A {
A() {}
int value = 0;
};
template <typename Value> struct B {
static A<int> a;
};
template <typename Value> A<int> B<Value>::a;
inline int foo() {
return B<int>::a.value;
}
```
```
clang++ -c -fno-pic a.cc -o weak.o
g++ -c -fno-pic a.cc -o unique.o # --enable-gnu-unique-object
# Duplicate symbol error. In postParse, we do not check `sym.binding`
ld.lld -e 0 weak.o unique.o
```
Mixing GCC and Clang object files in this case is not ideal. .bss._ZGVN1BIiE1aE
has different COMDAT groups. It appears to work in practice because the guard
variable prevents harm due to double initialization.
For the linker, we just stick with the rule that a weak binding does not cause
"duplicate symbol" errors.
Close https://github.com/llvm/llvm-project/issues/58232
Differential Revision: https://reviews.llvm.org/D136381
Wael Yehia [Thu, 20 Oct 2022 16:07:35 +0000 (16:07 +0000)]
[PGO][AIX] Improve dummy var retention and allow -bcdtors:csect linking.
1) Use a static array of pointer to retain the dummy vars.
2) Associate liveness of the array with that of the runtime hook variable
__llvm_profile_runtime.
3) Perform the runtime initialization through the runtime hook variable.
4) Preserve the runtime hook variable using the -u linker flag.
Reviewed By: hubert.reinterpretcast
Differential Revision: https://reviews.llvm.org/D136192
David Sherwood [Wed, 19 Oct 2022 11:43:14 +0000 (11:43 +0000)]
[AArch64][SVE2] Add the SVE2.1 fdot instructions
This patch adds the assembly/disassembly for the following instructions:
FDOT : Half-precision floating-point dot product
FDOT : Half-precision floating-point indexed dot product
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D136427
Louis Dionne [Fri, 21 Oct 2022 16:25:29 +0000 (12:25 -0400)]
[libc++][NFC] Add documentation for _Or and _And
Jeff Niu [Sun, 16 Oct 2022 18:30:08 +0000 (11:30 -0700)]
[mlir][scf] Add an IndexSwitchOp
The `scf.index_switch` is a control-flow operation that branches to one of the
given regions based on the values of the argument and the cases. The
argument is always of type `index`.
Example:
```mlir
%0 = scf.index_switch %arg0 -> i32
case 2 {
%1 = arith.constant 10 : i32
scf.yield %1 : i32
}
case 5 {
%2 = arith.constant 20 : i32
scf.yield %2 : i32
}
default {
%3 = arith.constant 30 : i32
scf.yield %3 : i32
}
```
Reviewed By: jpienaar
Differential Revision: https://reviews.llvm.org/D136003
Arthur Eubanks [Tue, 18 Oct 2022 22:42:14 +0000 (15:42 -0700)]
[llvm-reduce] Attempt to strip debug info
I often run llvm-reduce on IR that contains debug info, this prevents an
extra step of `opt -passes=strip` I do every time and will result in a
lot less invalid reductions around debug metadata.
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D136208
Craig Topper [Fri, 21 Oct 2022 15:56:00 +0000 (08:56 -0700)]
[RISCV] Add missing vscale x 1 cost model entries and tests.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D136411
Jay Foad [Fri, 21 Oct 2022 15:42:43 +0000 (16:42 +0100)]
[AMDGPU] Use VGPR classes in divergent build_vector patterns
This does not appear to affect codegen, but using SGPR classes for
operands of VALU instructions looked weird.
Differential Revision: https://reviews.llvm.org/D136459
bixia1 [Fri, 21 Oct 2022 15:25:45 +0000 (08:25 -0700)]
[mlir][sparse] Refactor the convert operator conversion to support codegen for the operator.
Outline the code that generates the loop structure to iterate over a dense
tensor or a sparse constant to genDenseTensorOrSparseConstantIterLoop.
Move a few routines to CodegenUtils for sharing.
Reviewed By: wrengr
Differential Revision: https://reviews.llvm.org/D136210
Jay Foad [Wed, 6 Jul 2022 13:00:32 +0000 (14:00 +0100)]
[MachineVerifier] Try harder to verify LiveVariables
Verify the LiveVariables analysis after a pass that claims to preserve
it, even if there are no further passes (apart from the verifier itself)
that would use the analysis.
Differential Revision: https://reviews.llvm.org/D129213
Sanjay Patel [Fri, 21 Oct 2022 15:15:11 +0000 (11:15 -0400)]
[InstCombine] allow some commutative matches for logical-and to select fold
This is obviously correct for real logic instructions,
and it also works for the poison-safe variants that use
selects:
https://alive2.llvm.org/ce/z/wyHiwX
This is motivated by the lack of 'xor' folding seen in issue #58313.
This more general fold should help reduce some of those patterns,
but I'm not sure if this specific case does anything for that
particular example.
Sanjay Patel [Fri, 21 Oct 2022 14:43:54 +0000 (10:43 -0400)]
[InstCombine] refactor matching code for logical ands; NFCI
Separating the matches makes it easier
to enhance for commutative patterns.
Jean Perier [Fri, 21 Oct 2022 15:21:58 +0000 (08:21 -0700)]
[flang] Fix FIRSupport build race condition with HLFIRDialect
FIRSupports includes headers from HLFIRDialect that are generated at
compile time. Therefore it must wait until these headers have been
generated.
Fix flang bot failures:
https://lab.llvm.org/buildbot/#/builders/173/builds/10304
Bjorn Pettersson [Thu, 20 Oct 2022 22:04:16 +0000 (00:04 +0200)]
[test] Use -passes in more Transforms tests
Another step towards getting rid of dependencies to the legacy
pass manager.
Primary change here is to just do -passes=foo instead of -foo in
simple situations (when running a single transform pass). But also
updated a few test running multiple passes.
Also removed some "duplicated" RUN lines in a few tests that where
using both -foo and -passes=foo syntax. No need to do the same kind
of testing twice.
Philip Reames [Fri, 21 Oct 2022 14:50:01 +0000 (07:50 -0700)]
[instcombine] Add basic test coverage for demanded bits of scalable vectors
Caroline Concatto [Thu, 20 Oct 2022 16:32:39 +0000 (17:32 +0100)]
[AArch64]SME2 Multi-vector-Multiple Vectors SQDMULH instructions
This patch adds the assembly/disassembly for the following instruction:
SQDMULH (multiple vectors): Multi-vector signed saturating doubling multiply high.
For 2 and 4 ZA registers
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09/SME-Instructions/SQDMULH--multiple-vectors---Multi-vector-signed-saturating-doubling-multiply-high-?lang=en
Depends on: D135563
Differential Revision: https://reviews.llvm.org/D135575
David Sherwood [Wed, 19 Oct 2022 10:47:24 +0000 (10:47 +0000)]
[AArch64][SVE2] Add the SVE2.1 fclamp instructions
This patch adds the assembly/disassembly for the following instructions:
FCLAMP : Floating-point clamp to minimum/maximum number
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D136358
Erich Keane [Fri, 21 Oct 2022 14:31:26 +0000 (07:31 -0700)]
[NFC] Make sure we check an optional when checking function constraints
For some reason the initial deferred concepts patch didn't add this
check, which someone noticed could cause a problem with other patches
applied. This makes sure we check these, so that an error condition
cannot cause us to crash.
Nikita Popov [Fri, 21 Oct 2022 14:22:26 +0000 (16:22 +0200)]
[LLVMIR] Use helper methods to set/check readnone attribute (NFC)
This makes the code forward-compatible to the memory attribute.
chenglin.bi [Fri, 21 Oct 2022 14:11:22 +0000 (22:11 +0800)]
[AAArch64][Windows] Fix the crash when running ninja check-asan
The crash comes from mismatch between load count in epilogue and seh instruction count.
Still because of the pass AArch64LoadStoreOpt. It remove some load in the epilogue but haven't remove the corresponding seh instruction.
This patch don't optimize the load in the epilogue to fix the issue.
Fix: #58516
Reviewed By: mstorsjo
Differential Revision: https://reviews.llvm.org/D136430
David Sherwood [Tue, 18 Oct 2022 16:43:44 +0000 (16:43 +0000)]
[AArch64] Add SVE2.1 target feature for Armv9-A 2022 Architecture Extension
First patch in a series adding MC layer support for SVE2.1.
This patch adds the following feature:
sve2p1
Some of the existing SVE instructions added for SME are now
also available under the sve2p1 feature, which are now guarded
by the HasSVE2p1orSME predicate.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D136352
Jay Foad [Fri, 21 Oct 2022 13:08:58 +0000 (14:08 +0100)]
[TwoAddressInstruction] Fix stale LiveVariables info in processStatepoint
D129213 improves verification of LiveVariables, and caused
CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll to fail with:
*** Bad machine code: LiveVariables: Block should not be in AliveBlocks ***
after Two-Address instruction pass.
Fix it by clearing AliveBlocks for a register which is no longer used.
Differential Revision: https://reviews.llvm.org/D136445
Caroline Concatto [Fri, 21 Oct 2022 13:38:46 +0000 (14:38 +0100)]
[AArch64] SME2 Multiple vectors int/float binary accumulator and two/four ZA single-vector
This patch adds the assembly/disassembly for the following instructions:
INT :
ADD (array accumulators): Add multi-vector to ZA array vector accumulators.
SUB (array accumulators): Subtract multi-vector from ZA array vector accumulators.
FP:
FADD : Floating-point add multi-vector to ZA array vector accumulators.
FSUB : Floating-point subtract multi-vector from ZA array vector accumulators.
For Two and Four ZA single-vectors
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Depends on: D135563
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D135567
Oleg Shyshkov [Fri, 21 Oct 2022 13:19:52 +0000 (15:19 +0200)]
[mlir][linalg] Add one-shot-bufferize tests for Linalg ops: reduce, map and transpose.
Differential Revision: https://reviews.llvm.org/D136431
Caroline Concatto [Thu, 20 Oct 2022 18:11:04 +0000 (19:11 +0100)]
[AArch64]SME2 multi-vec FP/INT down convert 2/4 registers
This patch implements
Int:
SQCVT: Multi-vector signed saturating extract narrow for 2 and 4 registers.
UQCVT: Multi-vector unsigned saturating extract narrow for 2 and 4 registers.
SQCVTU: Multi-vector signed saturating unsigned extract narrow for 2 and 4 registers
SQCVTN: Multi-vector signed saturating extract narrow and interleave.
SQCVTUN: Multi-vector signed saturating unsigned extract narrow and interleave.
UQCVTN: Multi-vector unsigned saturating extract narrow and interleave.
FP:
FCVT(narrowing): Multi-vector floating-point convert from single-precision to
packed half-precision.
FCVTN: Multi-vector floating-point convert from single-precision to
interleaved half-precision.
BFCVT: Multi-vector floating-point convert from single-precision to packed
BFloat16 format.
BFCVTN: : Multi-vector floating-point convert from single-precision to
interleaved BFloat16 format.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Depends on: D135563
Reviewed By: sdesmalen
Differential Revision: https://reviews.llvm.org/D135588
Caroline Concatto [Thu, 20 Oct 2022 17:57:33 +0000 (18:57 +0100)]
[AArch64]SME2 Multi-vector - Index/Single/Multi Array Vectors FMA sources
This patch adds the assembly/disassembly for the following instructions:
INT:
SMLAL
SMLSL
UMLAL
UMLSL
FP:
BFMLAL
BFMLSL
FMLAL
FMLSL
For multiple and indexed vector, Multiple and Single vector and
Multi vectors, for 1, 2 and 4 ZA registers.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
It also adds a new immediate:
uimm3s2range for off3
uimm2s2range for off2
to represent the vector select offset.
The new operands have the range between the first and the last vector position.
Depends on: D135563
Reviewed By: aemerson, sdesmalen
Re-landing the patch as the problem with https://reviews.llvm.org/D135563
is fixed in this commit:
1e4f82c2578cf5045ffe
Differential Revision: https://reviews.llvm.org/D135785
Luo, Yuanke [Fri, 21 Oct 2022 13:11:27 +0000 (21:11 +0800)]
[X86] Fix typo of mtamx_int8
Christian Kandeler [Thu, 4 Aug 2022 11:33:33 +0000 (13:33 +0200)]
[clangd] Add highlighting modifier "constructorOrDestructor"
This is useful for clients that want to highlight constructors and
destructors different from classes, e.g. like functions.
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D134728
Simon Pilgrim [Fri, 21 Oct 2022 13:06:54 +0000 (14:06 +0100)]
[CostModel][X86] Remove duplicate RUN line from cttz cost tests
Sanjay Patel [Fri, 21 Oct 2022 12:00:23 +0000 (08:00 -0400)]
[InstCombine] match logical and/or more generally in fold to select
This allows the regular bitwise logic opcodes in addition to the
poison-safe select variants:
https://alive2.llvm.org/ce/z/8xB9gy
Handling commuted variants safely is likely trickier, so that's
left to another patch.
Sanjay Patel [Thu, 20 Oct 2022 19:48:57 +0000 (15:48 -0400)]
[InstCombine] add tests for logical selects; NFC
Caroline Concatto [Mon, 17 Oct 2022 10:46:32 +0000 (11:46 +0100)]
[AArch64]SME2 Multi-single vector SVE Destructive 2 and 4 Registers
This patch adds the assembly/disassembly for the following instructions:
ADD (to vector): Add replicated single vector to multi-vector with multi-vector result.
SQDMULH (multiple and single vector): Multi-vector signed saturating doubling multiply high by vector.
for 2 and 4 ZA SVE registers.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
It also adds more size for the multiple register tuple:
ZZ_b_mul_r, ZZ_h_mul_r,
ZZZZ_b_mul_r, ZZZZ_h_mul_r,
for 8 bits and 16 bits with 2 and 4 ZA registers.
Depends on: D135468
With a fix for Mips for this test:
llvm/test/MC/Mips/mips64r6/valid.s
Differential Revision: https://reviews.llvm.org/D135563
Michael Buch [Wed, 19 Oct 2022 14:08:00 +0000 (15:08 +0100)]
[lldb][CPlusPlus] Add abi_tag support to the CPlusPlusNameParser
This patch teaches the `CPlusPlusNameParser` to parse the
demangled/prettified [[gnu::abi_tag(...)]] attribute. The demangled format
isn't standardized and the additions to the parser were mainly driven
using Clang (and the limited information on this from the official
Clang docs).
This change is motivated by multiple failures around step-in
behaviour for libcxx APIs (many of which have ABI tags as of recently).
LLDB determines whether the `step-avoid-regexp` matches the current
frame by parsing the scope-qualified name out of the demangled
function symbol. On failure, the `CPlusPlusNameParser` will simply
return the fully demangled name (which can include the return type)
to the caller, which in `FrameMatchesAvoidCriteria` means we will
not correctly decide whether we should stop at a frame or not if
the function has an abi_tag.
Ideally we wouldn't want to rely on the non-standard format
of demangled attributes. Alternatives would be:
1. Use the mangle tree API to do the parsing for us
2. Reconstruct the scope-qualified name from DWARF instead of parsing
the demangled name
(1) isn't feasible without a significant refactor of `lldb_private::Mangled`,
if we want to do this efficiently.
(2) could be feasible in cases where debug-info for a frame is
available. But it does mean we certain operations (such as step-in regexp,
and frame function names) won't work with/won't show ABI tags.
**Testing**
* Un-XFAILed step-in API test
* Added parser unit-tests
Differential Revision: https://reviews.llvm.org/D136306
Valentin Clement [Fri, 21 Oct 2022 12:34:37 +0000 (14:34 +0200)]
[flang] Handle fir.class pointer and allocatable in fir.dispatch code gen
fir.dispatch code generation was not handling fir.class pointer and
allocatable types. Update the code generation part to rertieve correctly the
the type info from those types.
Depends on D136426
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D136429
Valentin Clement [Fri, 21 Oct 2022 12:33:36 +0000 (14:33 +0200)]
[flang] Lower and code gen for allocate on polymorphic entities
When allocating a polymorphic entity, its type descriptor can come
from the declared type or can be provided in the allocate statement.
This patch adds lowering for allocate on polymorphic by calling
the `AllocatableInitDerived` runtime function with the correct
type descriptor. Some adaptation are made in the code generation
to accept fir.class where it is appropriate.
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D136426
Sylvestre Ledru [Fri, 21 Oct 2022 11:55:44 +0000 (13:55 +0200)]
Update links to googletest documentation
Update links to googletest documentation
No automatic tests, but local manual test: i click it, it opens the googletest documentation.
Reviewed By: sylvestre.ledru
Differential Revision: https://reviews.llvm.org/D136424
Jean Perier [Fri, 21 Oct 2022 11:43:03 +0000 (04:43 -0700)]
[flang] fix shared library builds after D136428
https://reviews.llvm.org/D136428 introduced the need for FIRBuilder
library to link against HLFIRDialect to satisfy shared builds.
The PrintFlangFunctionNames failure is unrelated, it is a build
race because many of the headers included in FrontendAction are
tablegen generated. So PrintFlangFunctionNames must wait until its
headers can be safely used. See
https://lab.llvm.org/buildbot/#/builders/191/builds/10340
Evgeny Shulgin [Fri, 21 Oct 2022 11:22:50 +0000 (11:22 +0000)]
[Clang] Add __has_constexpr_builtin support
The `__has_constexpr_builtin` macro can be used to check
whether the builtin in constant-evaluated by Clang frontend.
Reviewed By: aaron.ballman, shafik
Differential Revision: https://reviews.llvm.org/D136036
Jean Perier [Fri, 21 Oct 2022 11:14:17 +0000 (13:14 +0200)]
[flang] add hlfir::FortranEntity class
Add hlfir::FortranEntity class and a first helper to convert it to
fir::ExtendedValue.
The hlfir::FortranEntity will be the core class of the new expression
lowering. It is conceptually very similar to what fir::ExtendedValue
is today, except that it is wrapping single mlir::Value: it holds the
SSA value for a lowered Fortran variable or expression value.
Differential Revision: https://reviews.llvm.org/D136428
Tres Popp [Fri, 21 Oct 2022 11:08:51 +0000 (13:08 +0200)]
Delete dead code in Inliner
This code, on all platforms was a use-after-move violation that resulted
in the if-statement always returning false. As several core tests specifically
tested that this code did not execute, we assume that is the intent and
match behavior to existing behavior without relying on use-after-move
results.
Jean Perier [Fri, 21 Oct 2022 11:10:52 +0000 (13:10 +0200)]
[flang] Add High level Fortran IR dialect
This patch adds the basic dialect definition of the HLFIR dialect that
was described in https://reviews.llvm.org/D134285.
It adds the definition of the hlfir.expr type and related tests so that
it can be verified that the dialect is properly hooked up by the tools.
Operations will be added as progress is made in the expression
lowering update.
Differential Revision: https://reviews.llvm.org/D136328
Aaron Jacobs [Fri, 21 Oct 2022 11:08:30 +0000 (13:08 +0200)]
[libc++] type_traits: fix short-circuiting in std::conjunction.
Replace the two-level implementation with a simpler one that directly subclasses
the predicates, avoiding the instantiation of the template to get the `type`
member in a situation where we should short-circuit. This prevents incorrect
diagnostics when the instantiated predicate contains a static assertion.
Add a test case that reproduced the previous problem. The existing test case
involving `HasNoValue` didn't catch the problem because `HasNoValue` was in the
final position. The bug comes up when the predicate that shouldn't be
instantiated is after the short-circuit position but there is more to follow,
because then `__conjunction_impl<False, BadPredicate, ...>` instantiates
`__conjunction_impl<BadPredicate, ...>` (in order to obtain its `type` member),
which in turn instantiates `BadPredicate` in order to obtain its `value` member.
In contrast the new implementation doesn't recurse in instantiation any further
than it needs to, because it doesn't require particular members of the recursive
case.
I've also updated the test cases for `std::disjunction` to match,
although it doesn't have the same particular bug (its implementation is
quite different).
Fixes #58490.
Reviewed By: #libc, ldionne, philnik
Spies: philnik, ldionne, libcxx-commits
Differential Revision: https://reviews.llvm.org/D136318
Anton Sidorenko [Wed, 19 Oct 2022 13:30:41 +0000 (16:30 +0300)]
[MachineCombiner][RISCV] Relax optimization level requirement
Enable Machine Combiner for O1/O2/O3 optimization levels. It makes RISCV
consistent with other targets running Machine Combiner.
Originally it was enabled only for -O3, however I looked through time reports
and usually it takes 0.1%-0.4% of total time, and never takes more than 1.0%.
Differential Revision: https://reviews.llvm.org/D136339
Nikita Popov [Fri, 21 Oct 2022 10:16:57 +0000 (12:16 +0200)]
[ModuleSummaryAnalysis] Use helper methods to check readnone/readonly (NFC)
This makes sure that this code continue working when switching to
the memory attribute.
A caveat here is that onlyReadsMemory() will also true for readnone.
To be conservative, I'm explicitly excluding that case here.
Florian Hahn [Fri, 21 Oct 2022 10:18:01 +0000 (11:18 +0100)]
[IndVars] Forget SCEV for value after simplifying condition.
Additional SCEV verification highlighted a case where the cached loop
dispositions where incorrect after simplifying a condition in IndVars
and moving the user in LoopDeletion. Fix it by invalidating ICmp and all
its users.
Fixes #58515.
Nikita Popov [Mon, 10 Oct 2022 12:33:13 +0000 (14:33 +0200)]
[IR] Add support for memory attribute
This implements IR and bitcode support for the memory attribute,
as specified in https://reviews.llvm.org/D135597.
The new attribute is not used for anything yet (and as such, the
old memory attributes are unaffected).
Differential Revision: https://reviews.llvm.org/D135592
Nikita Popov [Mon, 10 Oct 2022 15:58:16 +0000 (17:58 +0200)]
[LangRef] Add memory attribute
This adds the LangRef wording for the memory attribute proposed at
https://discourse.llvm.org/t/rfc-unify-memory-effect-attributes/65579.
The old attributes are not removed from LangRef until the migration
is finished.
Differential Revision: https://reviews.llvm.org/D135597
Paulo Matos [Fri, 21 Oct 2022 10:06:28 +0000 (12:06 +0200)]
[clang] Fix typo in error message
Nikita Popov [Fri, 21 Oct 2022 09:49:42 +0000 (11:49 +0200)]
[Bitcode] Remove redundant intrinsic remangling (NFCI)
UpgradeIntrinsicFunction() is supposed to handle this already.
Simon Pilgrim [Fri, 21 Oct 2022 09:39:57 +0000 (10:39 +0100)]
[X86] Fold scalar_to_vector(i64 zext(x)) -> bitcast(vzext_movl(scalar_to_vector(i32 x)))
Extends existing anyextend fold to make use of the implicit zero-extension of the movd instruction
This also helps replace some nasty xmm->gpr->xmm traffic with a shuffle pattern instead
Noticed while looking at D130953
wanglei [Fri, 21 Oct 2022 09:03:37 +0000 (17:03 +0800)]
[LoongArch] Stack realignment support
This patch adds support for stack realignment while adding support for
variable sized objects.
Differential Revision: https://reviews.llvm.org/D136074
Simon Pilgrim [Fri, 21 Oct 2022 09:16:27 +0000 (10:16 +0100)]
[DebugInfo] Fix MSVC warning: "truncation from 'double' to 'float'"
David Green [Fri, 21 Oct 2022 09:10:35 +0000 (10:10 +0100)]
[ARM] Fix the type for v4f16 duplane
This was previously using the 32bit variant of the instruction, instead
of the 16bit as intended.
Fixes #58512
Differential Revision: https://reviews.llvm.org/D136422
Diana Picus [Tue, 11 Oct 2022 12:38:08 +0000 (12:38 +0000)]
[flang] Rename hypotf on MSVC platforms
The single precision `hypot` intrinsic is lowered to a call to the libm
`hypotf` function. However, the MSVC runtime lacks a hypotf function
and instead uses `_hypotf` (*). This patch tries to find and rewrite
calls to `hypotf` if we're on a MSVC platform.
Calls to libm functions can be introduced even after lowering (**).
Therefore, we try to do the rewriting at the very end of FIR to LLVM
lowering.
Fixes https://github.com/llvm/llvm-project/issues/57563
(*) More specifically, MSVC's headers define hypotf as an inline
function that just calls _hypotf. This works fine for clang, since it
will include those headers, but flang only links with the CRT so we
don't get a free ride.
(**) https://github.com/llvm/llvm-project/blob/
56f94ede2af9a327e59fe84dbf8cbbb7bb1dfa79/flang/lib/Optimizer/CodeGen/CodeGen.cpp#L3391
Differential Revision: https://reviews.llvm.org/D135853
Nikita Popov [Fri, 21 Oct 2022 09:05:53 +0000 (11:05 +0200)]
[AutoUpgrade] Fix remangling when upgrading struct return type
This was remangling the old function rather than the new one, and
could result in failures when we were performing both a struct
return upgrade and an opaque pointer upgrade.
Luo, Yuanke [Thu, 20 Oct 2022 09:49:47 +0000 (17:49 +0800)]
[Verifier] Relieve intrinsics parameter alignment size constrain
In D121898 we restrict parameter alignment size in IR since DAGISel
only have 4 bits to hold the alignment value. However intrinsics
won't be lowered to call instruction, so we can remove the constrain
for intrinsics.
Differential Revision: https://reviews.llvm.org/D136330
wanglei [Fri, 21 Oct 2022 08:35:23 +0000 (16:35 +0800)]
[LoongArch] Modify ParserMethod for the simm26_b operand type
Modify the ParserMethod of `simm26_b` operand type to `parseImmediate`.
Before that, for the `simm26_b` operand type, the same ParserMethod
was used as `simm26_bl`. When using the internal assembler to process
the blockaddress with `asm` instruction, the wrong blockaddress symbol
would be generated due to the call to the `getOrCreateSymbol()`
interface.
Differential Revision: https://reviews.llvm.org/D136073
Nikita Popov [Fri, 21 Oct 2022 08:53:24 +0000 (10:53 +0200)]
[LLParser] Remove redundant remangling (NFCI)
UpgradeCallsToIntrinsic() is already intended to perform remangling
in case no other upgrades are necessary. The additional
remangleIntrinsicFunction() calls are not needed and can hide bugs
in the UpgradeCallsToIntrinsic() implementation.
Nikita Popov [Fri, 21 Oct 2022 08:49:45 +0000 (10:49 +0200)]
[AutoUpgrade] Fix length check for intrinsic upgrade
The shortest intrinsics that can be upgraded via remangling have
8 characters (like "llvm.abs"). Make sure these go through the
upgrade code.
I think that currently this change is not observable from in-tree
callers of UpgradeIntrinsicFunction(), because callers do
redundant remangling checks. However, this issue shows up in
existing tests if those checks are removed (which I will do in
followup changes).
Timm Bäder [Fri, 14 Oct 2022 06:19:53 +0000 (08:19 +0200)]
[clang][Interp] Support base class constructors
Differential Revision: https://reviews.llvm.org/D135025
Timm Bäder [Fri, 14 Oct 2022 06:19:30 +0000 (08:19 +0200)]
[clang][Interp] Array initialization via ImplicitValueInitExpr
Differential Revision: https://reviews.llvm.org/D135013
Timm Bäder [Thu, 20 Oct 2022 13:44:09 +0000 (15:44 +0200)]
[clang][Interp][NFC] Remove some unused aliases.
David Green [Fri, 21 Oct 2022 08:35:39 +0000 (09:35 +0100)]
[ARM] Regnereate armv8.2a-fp16-vector-intrinsics.ll test. NFC
Florian Hahn [Fri, 21 Oct 2022 07:54:10 +0000 (08:54 +0100)]
[VPlan] Print predicates for widened cmp instructions (NFC).
Danil Sidoruk [Thu, 29 Sep 2022 07:24:55 +0000 (10:24 +0300)]
[clang-format] Add option for aligning requires clause body
Adds an option whether requires clause body should be aligned with
the `requires` keyword.
This option is now the default, both without configuration and in LLVM
style.
Fixes https://github.com/llvm/llvm-project/issues/56283
Differential Revision: https://reviews.llvm.org/D129443
Co-authored-by: Emilia Dreamer <emilia@rymiel.space>
Pierre van Houtryve [Wed, 19 Oct 2022 09:01:19 +0000 (09:01 +0000)]
[AMDGPU][GISel] Constrain selected operands in selectG_BUILD_VECTOR
Small bugfix. Currently harmless but a case in D134354 triggers it.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D136235
Adrian Kuegel [Fri, 21 Oct 2022 06:46:14 +0000 (08:46 +0200)]
Pierre van Houtryve [Thu, 20 Oct 2022 12:14:30 +0000 (12:14 +0000)]
[AMDGPU][GISel] Re-enable some working tests
These tests had been commented out but seem to not be crashing.
Not sure if codegen is perfect in each of them, but even if it's not I think it's better to put a TODO to fix codegen than remove the test outright, unless codegen is plain wrong (then I'd still rather XFAIL rather than hide it)
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D136341
Pierre van Houtryve [Mon, 17 Oct 2022 07:56:20 +0000 (07:56 +0000)]
[AMDGPU][DAG] Fix trunc/shift combine condition
The condition needs to be different for right-shifts, else we may lose information in some cases.
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D136059
Michael Wyman [Wed, 19 Oct 2022 20:11:41 +0000 (13:11 -0700)]
Don't emit `-Wnullability-completeness` warnings on `weak` Objective-C properties.
Zeroing weak references are by definition `nullable`, and adding
`nonnull` or `_Nullable` yields a mutual-exclusivity error. When
`-Wnullability-completeness` is enabled, however, non-audited header
regions require adding the `nullable` property keyword to avoid a
warning. This should be unnecessary, since it restates known nullability
of the `weak` property.
Additionally, the fix-it hints are both non-idiomatic Objective-C
(adding `_Nullable` to the property's pointer type rather than in the
`@property` attributes) and suggest the option of adding `_Nonnull`,
which would be an error.
Differential Revision: https://reviews.llvm.org/D128031
LLVM GN Syncbot [Fri, 21 Oct 2022 04:55:54 +0000 (04:55 +0000)]
[gn build] Port
0332a8e7d6da
Carlos Alberto Enciso [Thu, 20 Oct 2022 07:49:21 +0000 (08:49 +0100)]
[llvm-debuginfo-analyzer] (05/09) - Select elements
llvm-debuginfo-analyzer is a command line tool that processes debug
info contained in a binary file and produces a debug information
format agnostic “Logical View”, which is a high-level semantic
representation of the debug info, independent of the low-level
format.
The code has been divided into the following patches:
1) Interval tree
2) Driver and documentation
3) Logical elements
4) Locations and ranges
5) Select elements
6) Warning and internal options
7) Compare elements
8) ELF Reader
9) CodeView Reader
Full details:
https://discourse.llvm.org/t/llvm-dev-rfc-llvm-dva-debug-information-visual-analyzer/62570
This patch:
Select elements
- Support for logical elements selection:
LVPatterns
Reviewed By: psamolysov, probinson
Differential Revision: https://reviews.llvm.org/D125780
Craig Topper [Fri, 21 Oct 2022 04:35:47 +0000 (21:35 -0700)]
[RISCV] Add vscale x 1 cost model tests for compares. NFC
Weining Lu [Fri, 21 Oct 2022 01:56:27 +0000 (09:56 +0800)]
[LoongArch] Report error in AsmParser when rd == rk or rd == rj for AM* instructions
Do this check because the ISA manual says (edited from the original translation):
> If the AM* instruction has its rd == rj, an Instruction Non-defined Exception will be triggered when the instruction is executed.
>
> If the AM* instruction has its rd == rk, the execution result is unpredictable. It is software's responsibility to avoid this situation.
Note that binutils does the same check except when rd == r0 but this
is undocumented.
Differential Revision: https://reviews.llvm.org/D136076
Peiming Liu [Fri, 21 Oct 2022 00:28:02 +0000 (00:28 +0000)]
[mlir][sparse] update doc for sparse_tensor.foreach operator.
Clarify that sparse_tensor.foreach iterates sparse_tensor in stored dim order.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D136401
Peiming Liu [Thu, 20 Oct 2022 22:05:28 +0000 (22:05 +0000)]
[mlir][sparse] support foreach on dense tensor.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D136384
Siva Chandra Reddy [Fri, 21 Oct 2022 00:01:16 +0000 (00:01 +0000)]
[libc][Obvious] Add few missing license headers.
bixia1 [Thu, 20 Oct 2022 22:43:03 +0000 (15:43 -0700)]
[mlir][sparse] Fix getUnorderedCOOFromType for rank 1 tensor.
Previously, it used DimLevelType::SingletonNo to represent an unorder COO
tensor of rank 1 while it should use DimLevelType::CompressedNuNo.
Reviewed By: Peiming, wrengr
Differential Revision: https://reviews.llvm.org/D136387
Michael Jones [Thu, 20 Oct 2022 22:39:55 +0000 (15:39 -0700)]
[libc][obvious] fix comparison test cmake
The name of the libc target changed, this patch updates the cmake for
the string to float comparison test to use the correct name.
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D136388
rkayaith [Tue, 11 Oct 2022 21:39:34 +0000 (17:39 -0400)]
[mlir-opt] Add a '-dump-pass-pipeline' option
Add an option to dump the pipeline that will be run to stderr. A
dedicated option is needed since the existing `test-dump-pipeline`
pipeline won't be usable with `-pass-pipeline` after D135745.
Reviewed By: rriddle, mehdi_amini
Differential Revision: https://reviews.llvm.org/D135747
Luo, Yuanke [Wed, 19 Oct 2022 00:32:13 +0000 (08:32 +0800)]
[X86][AVX] Eliminate redundant movzbl instruction.
The movzbl instruction can be combined to vpinsrb or vmovd, when it is
actual lowered from anyext.
Differential Revision: https://reviews.llvm.org/D130953
rkayaith [Sun, 25 Sep 2022 20:47:39 +0000 (16:47 -0400)]
[mlir] Include anchor op when printing pass managers
Previously a pipeline nested on `anchor-op` would print as just
`'pipeline'`, now it will print as `'anchor-op(pipeline)'`. This ensures
the text form includes all information needed to reconstruct the pass
manager.
Reviewed By: rriddle, mehdi_amini
Differential Revision: https://reviews.llvm.org/D134622
Jan Svoboda [Sat, 15 Oct 2022 15:42:27 +0000 (08:42 -0700)]
[clang][lex] Avoid `DirectoryLookup` copies
This patch fixes a performance regression introduced in D121685 that was caused by copying `DirectoryLookup`.
rdar://
101206790
Reviewed By: ributzka
Differential Revision: https://reviews.llvm.org/D136019
Bill Wendling [Thu, 20 Oct 2022 23:08:01 +0000 (16:08 -0700)]
[clang] Correct sanitizer behavior in union FAMs
Clang doesn't have the same behavior as GCC does with union flexible
array members. (Technically, union FAMs are probably not acceptable in
C99 and are an extension of GCC and Clang.)
Both Clang and GCC treat *all* arrays at the end of a structure as FAMs.
GCC does the same with unions. Clang does it for some arrays in unions
(incomplete, '0', and '1'), but not for all. Instead of having this
half-supported feature, sync Clang's behavior with GCC's.
Reviewed By: kees
Differential Revision: https://reviews.llvm.org/D135727
Xiang Li [Tue, 18 Oct 2022 16:22:46 +0000 (09:22 -0700)]
[HLSL] Disable integer promotion to avoid int16_t being promoted to int for HLSL.
short will be promoted to int in UsualUnaryConversions.
Disable it for HLSL to keep int16_t as 16bit.
Reviewed By: aaron.ballman, rjmccall
Differential Revision: https://reviews.llvm.org/D133668
Rob Suderman [Thu, 20 Oct 2022 21:16:10 +0000 (14:16 -0700)]
[mlir][tosa] Add broadcasting case for tosa.resize degenerate case
When the resize is ?x1x1x?, the tosa.resize operation broadcasts the
input and (when quantized) applies a scaling factor. Updated the resize
operation to not use a tensor.extract operation, instead broadcasting
the only positional value as necessary.
Moved the tosa.resize tests to their own mlir test due to increased
complexity. Also corrected a bug where tosa.resize for bilinear-floating
point was not applying the correct scaling.
Reviewed By: jpienaar
Differential Revision: https://reviews.llvm.org/D136299
Jonas Devlieghere [Thu, 20 Oct 2022 22:20:50 +0000 (15:20 -0700)]
Revert "[lldb] Fix member access in GetExpressionPath"
This reverts commit
0205aa4a02570dfeda5807f66756ebdbb102744b because it
breaks TestArray.py:
a->c = <parent failed to evaluate: parent is NULL>
I decided to revert instead of disable the test because it looks like a
legitimate issue with the patch.
Eli Friedman [Thu, 20 Oct 2022 22:06:20 +0000 (15:06 -0700)]
[Arm64EC] Refer to dllimport'ed functions correctly.
Arm64EC has two different ways to refer to dllimport'ed functions in an
object file. One is using the usual __imp_ prefix, the other is using an
Arm64EC-specific prefix __imp_aux_. As far as I can tell, if a function
is in an x64 DLL, __imp_aux_ refers to the actual x64 address, while
__imp_ points to some linker-generated code that calls the exit thunk.
So __imp_aux_ is used to refer to the address in non-call contexts,
while __imp_ is used for calls to avoid the indirect call checker.
There's one twist to this, though: if an object refers to a symbol using
the __imp_aux_ prefix, the object file's symbol table must also contain
the symbol with the usual __imp_ prefix. The symbol doesn't actually
have to be used anywhere, it just has to exist; otherwise, the linker's
symbol lookup in x64 import libraries doesn't work correctly. Currently,
this is handled by emitting a .globl __imp_foo directive; we could try
to design some better way to handle this.
One minor quirk I haven't figured out: apparently, in Arm64EC mode, MSVC
prefers to use a linker-synthesized stub to call dllimport'ed functions,
instead of branching directly. The linker stub appears to do the same
thing that inline code would do, so not sure if it's just a code-size
optimization, or if the synthesized stub can actually do something other
than just load from the import table in some circumstances.
Differential Revision: https://reviews.llvm.org/D136202
Aart Bik [Thu, 20 Oct 2022 21:39:34 +0000 (14:39 -0700)]
[mlir][sparse] introduce new op for querying number of stored entries
Reviewed By: bixia
Differential Revision: https://reviews.llvm.org/D136382
Alexander Shaposhnikov [Thu, 20 Oct 2022 21:45:22 +0000 (21:45 +0000)]
[clang-tidy] Skip private default ctors in modernize-use-equals-default
For c++17 (i.e. before c++20) making a private default ctor explicitly defaulted
might expose the previously intentionally disallowed initializations, e.g.
class Tag { Tag() {} friend class Widget; }; is not equivalent to
class Tag { Tag() = default; friend class Widget; };
since in the latter case Tag is treated as an aggregate despite having a declaration
of the default constructor. This diff makes modernize-use-equals-default skip
in-class empty nonpublic default ctors to avoid code breakages.
Test plan: ninja check-all
Differential revision: https://reviews.llvm.org/D136224