Philipp Tomsich [Mon, 17 Apr 2017 15:48:00 +0000 (17:48 +0200)]
rockchip: mkimage: rkspi: include the header sector in the SPI size calculation
Our earlier change broke the generation of SPI images, by excluding the
2K used for header0 from the size-calculation.
This commit makes sure that these are included before calculating the
required total size (including the padding from the 2K-from-every-4K
conversion).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Thu, 20 Apr 2017 20:05:55 +0000 (22:05 +0200)]
rockchip: spl: rk3399: spi: enable SPL_SPI_LOAD if SPI is enabled for SPL
To include the ability to load from an SPI flash in SPL, it's not
sufficient to define SPL_SPI_SUPPORT and SPL_SPI_FLASH_SUPPORT via
Kconfig... so we conditionally define SPL_SPI_LOAD if SPI support
is already enabled for SPL via Kconfig.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Jakob Unterwurzacher [Thu, 20 Apr 2017 20:05:54 +0000 (22:05 +0200)]
rockchip: spi: enable support for the rk_spi driver for the RK3399
The existing Rockchip SPI (rk_spi.c) driver also matches the hardware
block found in the RK3399. This has been confirmed both with SPI NOR
flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5.
This change adds the 'rockchip,rk3399-spi' string to its compatible
list to allow reuse of the existing driver.
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Thu, 20 Apr 2017 20:05:53 +0000 (22:05 +0200)]
rockchip: pinctrl: rk3399: add support for the SPI5 controller
This commit adds support for the pin-configuration of the SPI5
controller of the RK3399 through the following changes:
* grf_rk3399.h: adds definition for configuring the SPI5 pins
in the GPIO2C group
* periph.h: defines PERIPH_ID_SPI3 through PERIPH_ID_SPI5
* pinctrl_rk3399.c: adds the reverse-mapping from the IRQ# to
PERIPH_ID_SPI5; dispatches PERIPH_ID_SPI3
through SPI5 to the appropriate pin-config
function; implements the pin-configuration
for PERIPH_ID_SPI5 using the GPIO2C group
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Thu, 20 Apr 2017 20:05:52 +0000 (22:05 +0200)]
rockchip: spi: rewrite rkspi_set_clk for a more conservative baudrate setting
The baudrate in rkspi was calculated by using an integer division
(which implicitly discarded any fractional result), then rounding to
an even number and finally clamping to 0xfffe using a bitwise AND
operator. This introduced two issues:
1) for very small baudrates (overflowing the 0xfffe range), the
bitwise-AND generates rather random-looking (wildly varying)
actual output bitrates
2) for higher baudrates, the calculation tends to 'err towards a
higher baudrate' with the actual error increasing as the dividers
become very small. E.g., with a 99MHz input clock, a request
for a 20MBit baudrate (99/20 = 4.95), a 24.75 MBit would be use
(which amounts to a 23.75% error)... for a 34 MBit request this
would be an actual outbout of 49.5 Mbit (i.e. a 45% error).
This change rewrites the divider selection (i.e. baudrate calculation)
by making sure that
a) for the normal case: the largest representable baudrate below the
requested rate will be chosen;
b) for the denormal case (i.e. when the divider can no longer be
represented), the lowest representable baudrate is chosen.
Even though the denormal case (b) may be of little concern in real
world applications (even with a 198MHz input clock, this will only
happen at below approx. 3kHz/3kBit), our board-verification team kept
complaining.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Philipp Tomsich [Thu, 20 Apr 2017 20:05:51 +0000 (22:05 +0200)]
rockchip: spi: rk_spi: dynamically select an module input rate
The original clock/bitrate selection code for the rk_spi driver was a
bit limited, as it always selected a 99MHz input clock rate (which
would allow for a maximum bitrate of 49.5MBit/s), but returned -EINVAL
if a bitrate higher than 48MHz was requested.
To give us better control over the bitrate (i.e. add more operating
points, especially at "higher" bitrate---such as above 9MBit/s), we
try to choose 4x the maximum frequency (clamped to 50MBit) from the
DTS instead of 99MHz... for most use-cases this will yield a frequency
of 198MHz, but is flexible to go beyond this in future configurations.
This also rewrites the check to allow frequencies of up to half the
SPI module rate as bitrates and then clamps to whatever the DTS allows
as a maximum (board-specific) frequency and does away with the -EINVAL
when trying to select a bitrate (for cases that exceeded the hard
limit) and instead consistently clamps to the lower of the hard limit,
the soft limit for the SPI bus (from the DTS) or the soft limit for
the SPI slave device.
This replaces
"rockchip: spi: rk_spi: select 198MHz input to the SPI module for the RK3399"
"rockchip: spi: rk_spi: improve clocking code for the RK3399"
from earlier versions of this series.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Thu, 20 Apr 2017 20:05:50 +0000 (22:05 +0200)]
rockchip: clk: rk3399: fix off-by one during rate calculation in i2c/spi_set_rate
For the RK3399, i2c_set_rate (and by extension: our spi_set_rate,
which had been mindlessly following the template of the i2c_set_rate
implementation) miscalculates the rate returned due to a off-by-one
error resulting from the following sequence of events:
1. calculates 'src_div := src_freq / target_freq'
2. stores 'src_div - 1' into the register (the actual divider applied
in hardware is biased by adding 1)
3. returns the result of the DIV_RATE(src_freq, src_div) macro, which
expects the (decremented) divider from the hardware-register and
implictly adds 1 (i.e. 'DIV_RATE(freq, div) := freq / (div + 1)')
This can be observed with the SPI driver, which sets a rate of 99MHz
based on the GPLL frequency of 594MHz: the hardware generates a clock
of 99MHz (src_div is 6, the bitfield in the register correctly reads 5),
but reports a frequency of 84MHz (594 / 7) on return.
To fix, we have two options:
* either we bias (i.e. "DIV_RATE(GPLL, src_div - 1)"), which doesn't
make for a particularily nice read
* we simply call the i2c/spi_get_rate function (introducing additional
overhead for the additional register-read), which reads the divider
from the register and then passes it through the DIV_RATE macro
Given that this code is not time-critical, the more readable solution
(i.e. calling the appropriate get_rate function) is implemented in this
change.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Thu, 20 Apr 2017 20:05:49 +0000 (22:05 +0200)]
rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5
This change adds support for configuring the module clocks for SPI1 and
SPI5 from the 594MHz GPLL.
Note that the driver (rk_spi.c) always sets this to 99MHz, but the
implemented functionality is more general and will also support
different clock configurations.
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
eric.gao@rock-chips.com [Mon, 17 Apr 2017 14:24:24 +0000 (22:24 +0800)]
rockchip: video: Makefile: Modify Makefile for rockchip video driver
Modify Makefile for rockchip video driver according to Kconfig, so that
source code will not be compiled if not needed.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
eric.gao@rock-chips.com [Mon, 17 Apr 2017 14:24:23 +0000 (22:24 +0800)]
rockchip: video: Kconfig: Add Kconfig for rockchip video driver
1. add Kconfig for rockchip video driver, so that video port can be
selected as needed.
2. move VIDEO_ROCKCHIP option to new Kconfig for concision.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Drop indenting in Kconfig:
Signed-off-by: Simon Glass <sjg@chromium.org>
Kever Yang [Mon, 17 Apr 2017 08:42:44 +0000 (16:42 +0800)]
rockchip: rk3399: correct memory region
RK3399 device memory region is 0xf8000000~0xffffffff.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Xu Ziyuan [Sun, 16 Apr 2017 09:44:46 +0000 (17:44 +0800)]
rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMC
The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Xu Ziyuan [Sun, 16 Apr 2017 09:44:45 +0000 (17:44 +0800)]
rockchip: clk: rk3288: add ciu_clk entry for eMMC/SDMMC/SDIO
The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Xu Ziyuan [Sun, 16 Apr 2017 09:44:44 +0000 (17:44 +0800)]
rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO
The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Xu Ziyuan [Sun, 16 Apr 2017 09:44:43 +0000 (17:44 +0800)]
rockchip: clk: rk3036: add ciu_clk entry for eMMC/SDIO
The genunie bus clock is sclk_x for eMMC/SDIO, add support for it.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Xu Ziyuan [Sun, 16 Apr 2017 09:44:42 +0000 (17:44 +0800)]
mmc: dw_mmc: rockchip: select proper card clock
As you know, biu_clk is used for AMBA AHB/APB interface, ciu_clk is
used for communication between host and card devices. The real bus clock
is ciu, so let's rectify it.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 14 Apr 2017 06:55:05 +0000 (14:55 +0800)]
mkimage: rockchip: add support for rk3328
Add support for rk3328 package header in mkimage tool.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Kever Yang [Wed, 12 Apr 2017 04:00:06 +0000 (12:00 +0800)]
rockchip: rk3399: use regulators_enable_boot_on() to init regulator
Use regulators_enable_boot_on() instead of init regulators one by one,
the interface can init all the regulators with regulator-boot-on property.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:28:39 +0000 (20:28 +0200)]
mips: bmips: enable bcm6328-power-domain driver for BCM6328 and BCM63268 boards
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:28:38 +0000 (20:28 +0200)]
mips: bmips: add bcm6328-power-domain driver support for BCM63268
This driver can control up to 32 power domains.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:28:37 +0000 (20:28 +0200)]
mips: bmips: add bcm6328-power-domain driver support for BCM6328
This driver can control up to 32 power domains.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:28:36 +0000 (20:28 +0200)]
dm: power: domain: add BCM6328 power domain driver
This allows controlling MISC IDDQ register on BCM6328 SoCs.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Álvaro Fernández Rojas [Wed, 3 May 2017 13:10:25 +0000 (15:10 +0200)]
mips: bmips: enable bcm6345-reset driver for all BMIPS boards
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Wed, 3 May 2017 13:10:24 +0000 (15:10 +0200)]
mips: bmips: add bcm6345-rst driver support for BCM63268
This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Wed, 3 May 2017 13:10:23 +0000 (15:10 +0200)]
mips: bmips: add bcm6345-rst driver support for BCM6328
This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Wed, 3 May 2017 13:10:22 +0000 (15:10 +0200)]
mips: bmips: add bcm6345-rst driver support for BCM6358
This driver can control up to 32 resets.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Wed, 3 May 2017 13:10:21 +0000 (15:10 +0200)]
dm: reset: add BCM6345 reset driver
This is a simplified version of linux/arch/mips/bcm63xx/reset.c
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:13:05 +0000 (20:13 +0200)]
mips: bmips: enable bcm6345-clk driver for all BMIPS boards
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:13:04 +0000 (20:13 +0200)]
mips: bmips: add bcm6345-clk driver support for BCM63268
This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:13:03 +0000 (20:13 +0200)]
mips: bmips: add bcm6345-clk driver support for BCM6328
This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:13:02 +0000 (20:13 +0200)]
mips: bmips: add bcm6345-clk driver support for BCM6358
This driver can control up to 32 clocks.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:13:01 +0000 (20:13 +0200)]
dm: clk: add BCM6345 clock driver
This is a simplified version of linux/arch/mips/bcm63xx/clk.c
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:11:32 +0000 (20:11 +0200)]
mips: bmips: add NeufBox 4 (Sercomm) board
This serves as an example for bcm6358-leds.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:11:31 +0000 (20:11 +0200)]
mips: bmips: add bcm6358-led driver support for BCM6358
This driver can control up to 32 serial leds.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:11:30 +0000 (20:11 +0200)]
dm: led: add BCM6358 led driver
This driver is a simplified version of linux/drivers/leds/leds-bcm6358.c
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:10:28 +0000 (20:10 +0200)]
mips: bmips: add Comtrend VR-3032u bcm6328-leds
This board has several LEDs attached to its BCM6328 led controller.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:10:27 +0000 (20:10 +0200)]
mips: bmips: add Comtrend AR-5387un bcm6328-leds
This board has several LEDs attached to its BCM6328 led controller.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:10:26 +0000 (20:10 +0200)]
mips: bmips: add bcm6328-led driver support for BCM63268
This driver can control up to 24 LEDs and supports HW blinking and serial leds.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:10:25 +0000 (20:10 +0200)]
mips: bmips: add bcm6328-led driver support for BCM6328
This driver can control up to 24 LEDs and supports HW blinking and serial leds.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:10:24 +0000 (20:10 +0200)]
dm: led: add BCM6328 led driver
This driver is a simplified version of linux/drivers/leds/leds-bcm6328.c,
simplified to remove HW leds and blink fallbacks.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:09:34 +0000 (20:09 +0200)]
mips: bmips: add Huawei HG556a gpio-leds
This board has several LEDs attached to gpio0.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:09:33 +0000 (20:09 +0200)]
mips: bmips: add bcm6345-gpio driver support for BCM63268
This SoC has one gpio bank divided into two 32 bit registers, with a total of
52 GPIOs.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:09:32 +0000 (20:09 +0200)]
mips: bmips: add bcm6345-gpio driver support for BCM6328
This SoC has one gpio bank with a total of 32 GPIOs.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:09:31 +0000 (20:09 +0200)]
mips: bmips: add bcm6345-gpio driver support for BCM6358
This SoC has one gpio bank divided into two 32 bit registers, with a total of
40 GPIOs.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Sun, 7 May 2017 18:09:30 +0000 (20:09 +0200)]
dm: gpio: add BCM6345 gpio driver
This driver is based on linux/arch/mips/bcm63xx/gpio.c, simplified to allow
defining one or two independent banks for each Broadcom SoC.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Mon, 24 Apr 2017 22:39:26 +0000 (00:39 +0200)]
MIPS: add BMIPS Comtrend VR-3032u board
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Mon, 24 Apr 2017 22:39:25 +0000 (00:39 +0200)]
MIPS: add support for Broadcom MIPS BCM63268 SoC family
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Mon, 24 Apr 2017 22:39:24 +0000 (00:39 +0200)]
MIPS: add BMIPS Comtrend AR-5387un board
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Mon, 24 Apr 2017 22:39:23 +0000 (00:39 +0200)]
MIPS: add support for Broadcom MIPS BCM6328 SoC family
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Mon, 24 Apr 2017 22:39:22 +0000 (00:39 +0200)]
MIPS: add BMIPS Huawei HG556a board
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Mon, 24 Apr 2017 22:39:21 +0000 (00:39 +0200)]
MIPS: add support for Broadcom MIPS BCM6358 SoC family
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Mon, 24 Apr 2017 22:39:20 +0000 (00:39 +0200)]
MIPS: add initial infrastructure for Broadcom MIPS SoCs
CFE checks CPU Thread in a different way (using register $22):
mfc0 t1, C0_BCM_CONFIG, 3 # $22
li t2, CP0_CMT_TPID # (1 << 31)
and t1, t2
bnez t1, 2f # if we are running on thread 1, skip init
nop
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Mon, 24 Apr 2017 22:39:19 +0000 (00:39 +0200)]
ram: add RAM driver for Broadcom MIPS SoCs
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Mon, 24 Apr 2017 22:39:18 +0000 (00:39 +0200)]
cpu: add CPU driver for Broadcom MIPS SoCs
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Mon, 24 Apr 2017 22:39:17 +0000 (00:39 +0200)]
cmd: cpu: refactor to ensure devices are probed and improve code style
Use uclass_first_device and uclass_next_device in order to avoid exceptions
for drivers that aren't probed when cpu ops are requested.
Improve code style and fix indentations.
Fix incorrect line break when cpu info is not available.
Remove unneeded brackets.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Mon, 24 Apr 2017 22:39:16 +0000 (00:39 +0200)]
serial: add serial driver for BCM6345
It is based on linux/drivers/tty/serial/bcm63xx_uart.c
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Mon, 24 Apr 2017 22:39:15 +0000 (00:39 +0200)]
MIPS: allow using generic sysreset drivers
Avoid duplicating do_reset definition if SYSRESET is enabled for MIPS
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Mon, 24 Apr 2017 22:39:14 +0000 (00:39 +0200)]
sysreset: add syscon-reboot driver
Add a new sysreset driver based on linux/drivers/power/reset/syscon-reboot.c,
which provides a generic driver for platforms that only require writing a mask
to a regmap offset.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas [Mon, 24 Apr 2017 22:39:13 +0000 (00:39 +0200)]
cmd: cpu: fix NULL cpu feature prints
Commit 740d5d3 added two new features but only one feature name,
which results in NULL prints when device_id feature is selected.
Before:
HG556a # cpu detail
-1: cpu@0 BCM6358A1
ID = 0, freq = 300 MHz: L1 cache, MMU, NULL
Device ID 0x2a010
-1: cpu@1 BCM6358A1
ID = 1, freq = 300 MHz: L1 cache, MMU, NULL
Device ID 0x2a010
After:
HG556a # cpu detail
-1: cpu@0 BCM6358A1
ID = 0, freq = 300 MHz: L1 cache, MMU, Device ID
Device ID 0x2a010
-1: cpu@1 BCM6358A1
ID = 1, freq = 300 MHz: L1 cache, MMU, Device ID
Device ID 0x2a010
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Daniel Schwierzeck [Mon, 24 Apr 2017 17:03:34 +0000 (19:03 +0200)]
MIPS: call debug_uart_init right before board_init_f
All MIPS boards that support debug uart are calling debug_uart_init right at
the beginning of board_early_init_f.
Instead of doing that, let's provide a generic call to debug_uart_init right
before the call to board_init_f if debug uart is enabled for boards without
stack in SRAM.
On the other hand, boards with stack in SRAM can call earlier (right before
low level init).
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Álvaro Fernández Rojas [Mon, 24 Apr 2017 17:03:33 +0000 (19:03 +0200)]
MIPS: tl-wdr4300: remove debug_uart_init call
In order to add a generic MIPS debug_uart_init call right before the call to
board_early_init_f, we need to remove all calls to debug_uart_init from every
MIPS boards.
WDR4300 doesn't provide a board_debug_uart_init and configures pinmux in
board_early_init_f instead. Since I have no idead of what's the needed uart
pinmux config, I copied the whole pinmux config to a new function that is
called from board_early_init_f if CONFIG_DEBUG_UART_BOARD_INIT is not enabled.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Álvaro Fernández Rojas [Mon, 24 Apr 2017 17:03:32 +0000 (19:03 +0200)]
MIPS: QCA AP143: remove debug_uart_init call
In order to add a generic MIPS debug_uart_init call right before the call to
board_early_init_f, we need to remove all calls to debug_uart_init from every
MIPS boards.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Álvaro Fernández Rojas [Mon, 24 Apr 2017 17:03:31 +0000 (19:03 +0200)]
MIPS: QCA AP121: remove debug_uart_init call
In order to add a generic MIPS debug_uart_init call right before the call to
board_early_init_f, we need to remove all calls to debug_uart_init from every
MIPS boards.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Álvaro Fernández Rojas [Thu, 20 Apr 2017 18:36:28 +0000 (20:36 +0200)]
u-boot.elf: add quiet_cmd_u-boot-elf and cmd_u-boot-elf
This way we can see output about u-boot.elf being built or not.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Álvaro Fernández Rojas [Thu, 20 Apr 2017 18:36:27 +0000 (20:36 +0200)]
MIPS: add support for generating u-boot.elf
Define PLATFORM_ELFFLAGS for MIPS in order to be able to generate u-boot.elf
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Álvaro Fernández Rojas [Thu, 20 Apr 2017 18:36:26 +0000 (20:36 +0200)]
u-boot.elf: allow overriding entry symbol
LD gives the following warning when trying to process u-boot-elf.o
warning: cannot find entry symbol __start; defaulting to
0000000080010000
According to gnu-libc the entry symbol for mips is __start and not _start:
https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/mips/dl-machine.h;h=
ed47513ccc1d23d23d32ee640053d2f351f3990b;hb=HEAD#l258
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Álvaro Fernández Rojas [Thu, 20 Apr 2017 18:36:25 +0000 (20:36 +0200)]
u-boot.elf: remove hard-coded arm64 flags
This is needed in order to allow building it for other archs.
Move relocation comment to a better place.
Remove no longer needed dts FIXME.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adam Ford [Wed, 26 Apr 2017 18:41:32 +0000 (13:41 -0500)]
power: twl4030: Remove CONFIG_TWL4030_POWER from include/configs
With the addition of Kconfig now having CONFIG_TWL4030_POWER and
with that being the default when OMAP34XX is selected, this
is no longer needed in include/configs and can be removed from the
whitelist.
This has only been tested on logic PD DM3730 using ti_omap3_common.h
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Adam Ford [Wed, 26 Apr 2017 18:41:31 +0000 (13:41 -0500)]
power: twl4030: Move CONFIG_TWL4030_POWER to Kconfig
As requested, I added the CONFIG_TWL4030_POWER to Kconfig and made it
the implied default when selecting OMAP34XX as a platform.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Adam Ford [Mon, 24 Apr 2017 18:34:43 +0000 (13:34 -0500)]
power: twl4030: Add CONFIG_CMD_POWEROFF support
With the addition of twl4030_power_off(), let's allow the 'poweroff' command
to run this function when CONFIG_CMD_POWEROFF is enabled.
Tested on a DM3730 with twl4030 PMIC.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Adam Ford [Mon, 17 Apr 2017 13:09:45 +0000 (08:09 -0500)]
omap3_logic: Add Device Tree Support and more DM drivers
This patch also removes all the excessive code for NS16550 intiailization
as the device tree can do that now. This also adds DM_I2C and DM_MMC
since the overlying drivers have the built-in support already. The
corresponding include/config/omap3_logic.h also reduced in size
due to the new device tree support.
Signed-off-by: Adam Ford <aford173@gmail.com>
Changes in V2:
Retain Auto-detect ability between SOM-LV and Torpedo
Split this off from the device sub submissions
Adam Ford [Mon, 17 Apr 2017 13:09:44 +0000 (08:09 -0500)]
ARM: DTS: Add Logic PD DM3730 Torpedo Device Tree
Previous commit has this combined with SOM-LV. This commit has only
the Torpedo Device Tree.
The device trees were sync'd with 4.9.y stable with two changes:
disable mmc2 and stdout-path = &uart1. Both of those two changes
will be submitted to the linux-omap list
Signed-off-by: Adam Ford <aford173@gmail.com>
Changes in V2:
Split device tree from other board
Adam Ford [Mon, 17 Apr 2017 13:09:43 +0000 (08:09 -0500)]
ARM: DTS: Add Logic PD DM3730 SOM-LV initial support
This adds the device tree. Previous commit added both boards at the
same time.
Signed-off-by: Adam Ford <aford173@gmail.com>
Changes in V2:
Split the SOM-LV from Torpedo
Adam Ford [Mon, 17 Apr 2017 13:09:42 +0000 (08:09 -0500)]
OMAP3: Add SMSC9221 device tree for omap devices connected on GPMC.
Some OMAP3 devices support an SMSC ethernet PHY connected to the GPMC bus.
This copies this device tree from Linux 4.9.y stable
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Adam Ford [Mon, 17 Apr 2017 13:09:41 +0000 (08:09 -0500)]
omap3: Copy twl4030 device tree from Linux 4.9.y stable
Many OMAP3 boards use a TWL4030 PMIC. This brings in the related
device tree information for common TWL4030 and TWL4030 with OMAP3.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Adam Ford [Mon, 17 Apr 2017 13:09:40 +0000 (08:09 -0500)]
ARM: OMAP: I2C: Support New read, write and probe functions for OMAP3
New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
(4430/60/70), OMAP5 (5430) and AM335X (3359) were added in
960187ffa125(
"ARM: OMAP: I2C: New read, write and probe functions") but not tested
on OMAP3. This patch will allow the updated drivers using device tree and
DM_I2C to operate on OMAP3.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Adam Ford [Mon, 17 Apr 2017 13:09:39 +0000 (08:09 -0500)]
omap3630: Copy Device tree from Linux 4.9.y stable
Add device tree support to allow for CONFIG_OF_CONTROL in OMAP3630 boards.
DM3730 can use this same device tree.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Adam Ford [Mon, 17 Apr 2017 13:09:38 +0000 (08:09 -0500)]
omap3: Copy Device tree from Linux 4.9.y stable
Add device tree support to allow for CONFIG_OF_CONTROL in OMAP3 boards.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Adam Ford [Mon, 17 Apr 2017 13:09:37 +0000 (08:09 -0500)]
omap_hsmmc: update struct hsmmc to accommodate omap3 from DT
This patch changes the way DM_MMC calculates offset to the base register of
MMC. Previously this was through an #ifdef but that wasn't necessary for OMAP3.
This patch will now add in the offset to the base address based on the
.compatible flags.
Signed-off-by: Adam Ford <aford173@gmail.com>
V2: Remove ifdef completely and reference offset from the omap_hsmmc_ids table.
V1: Change ifdef to ignore OMAP3
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Alex Deymo [Sun, 2 Apr 2017 08:25:20 +0000 (01:25 -0700)]
Allow boards to initialize the DT at runtime.
In some boards like the Raspberry Pi the initial bootloader will pass
a DT to the kernel. When using U-Boot as such kernel, the board code in
U-Boot should be able to provide U-Boot with this, already assembled
device tree blob.
This patch introduces a new config option CONFIG_OF_BOARD to use instead
of CONFIG_OF_EMBED or CONFIG_OF_SEPARATE which will initialize the DT
from a board-specific funtion instead of bundling one with U-Boot or as
a separated file. This allows boards like the Raspberry Pi to reuse the
device tree passed from the bootcode.bin and start.elf firmware
files, including the run-time selected device tree overlays.
Signed-off-by: Alex Deymo <deymo@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Paolo Pisati [Fri, 10 Feb 2017 16:28:05 +0000 (17:28 +0100)]
bcm2835_wdt: support for the BCM2835/2836 watchdog
Signed-off-by: Paolo Pisati <p.pisati@gmail.com>
Simon Glass [Wed, 5 Apr 2017 22:23:45 +0000 (16:23 -0600)]
arm: rpi: Add a TODO to move all messages into the msg handler
The board code should all move into msg.c for consistency. Add a TODO for
this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 5 Apr 2017 22:23:44 +0000 (16:23 -0600)]
dm: video: arm: rpi: Convert to use driver model for video
Adjust the video driver to work with driver model and move over existing
baords. There is no need to keep the old code.
We can also drop setting of CONFIG_FB_ADDR since driver model doesn't have
this problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Simon Glass [Wed, 5 Apr 2017 22:23:43 +0000 (16:23 -0600)]
dm: video: Add driver-model support to lcd_simplefb
Allow this to work with CONFIG_DM_VIDEO enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Simon Glass [Wed, 5 Apr 2017 22:23:42 +0000 (16:23 -0600)]
dm: video: Refactor lcd_simplefb to prepare for driver model
Adjust this function so that we can convert it to support CONFIG_DM_VIDEO
without a lot of code duplication.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Simon Glass [Wed, 5 Apr 2017 22:23:41 +0000 (16:23 -0600)]
video: arm: rpi: Move the video settings out of the driver
Add a function to set the video parameters to the msg handler and remove
it from the video driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Simon Glass [Wed, 5 Apr 2017 22:23:40 +0000 (16:23 -0600)]
video: arm: rpi: Move the video query out of the driver
Add a function to get the video size to the msg handler and remove it from
the video driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Simon Glass [Wed, 5 Apr 2017 22:23:39 +0000 (16:23 -0600)]
dm: arm: rpi: Drop CONFIG_OF_EMBED
We should not use an embedded device tree on a production board. There
does not seem to be any reason for it in commit 7670909. So drop this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 5 Apr 2017 22:23:38 +0000 (16:23 -0600)]
dm: mmc: rpi: Convert Raspberry Pi to driver model for MMC
Convert the bcm2835 SDHCI driver over to support CONFIG_DM_MMC and move
all boards over. There is no need to keep the old code since there are no
other users.
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 5 Apr 2017 22:23:37 +0000 (16:23 -0600)]
arm: rpi: Add a function to obtain the MMC clock
Move this code into the new message handler file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 5 Apr 2017 22:23:36 +0000 (16:23 -0600)]
arm: rpi: Add a file to handle messages
The bcm283x chips provide a way for the ARM core to communicate with the
graphics processor, which is in charge of many things. This is handled by
way of a message prototcol.
At present the code for sending message (and receiving a reply) is spread
around U-Boot, primarily in the board file. This means that sending a
message from a driver requires duplicating the code.
Create a new message implementation with a function to support powering on
a subsystem as a starting point.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 5 Apr 2017 22:23:35 +0000 (16:23 -0600)]
dm: arm: rpi: Use driver model for Ethernet
Enable CONFIG_DM_ETH so that driver model is used for the USB Ethernet
device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 5 Apr 2017 22:23:34 +0000 (16:23 -0600)]
dm: arm: rpi: Move to driver model for USB
Start using driver model for USB on the Raspberry Pi. The dwc2 supports
this now so this is just a config change.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 5 Apr 2017 22:23:33 +0000 (16:23 -0600)]
arm: rpi: Drop CONFIG_CONS_INDEX
This is not needed now that serial uses driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 5 Apr 2017 22:23:32 +0000 (16:23 -0600)]
arm: rpi: Drop the GPIO device addresses
We can rely on the device tree to provide this information.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 5 Apr 2017 22:23:31 +0000 (16:23 -0600)]
string: Use memcpy() within memmove() when we can
A common use of memmove() can be handled by memcpy(). Also memcpy()
includes an optimisation for large sizes: it copies a word at a time. So
we can get a speed-up by calling memcpy() to handle our move in this case.
Update memmove() to call memcpy() if the destination is before the source.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Wed, 5 Apr 2017 22:23:28 +0000 (16:23 -0600)]
net: smsc95xx: Correct free_pkt() implementation
On further review this returns the wrong packet length from the driver.
It may not be noticed since protocols will take care of it. Fix it by
subtracting the header length from the packet length returned.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 9 May 2017 20:11:36 +0000 (16:11 -0400)]
Merge git://git.denx.de/u-boot-dm
Tom Rini [Tue, 9 May 2017 19:48:09 +0000 (15:48 -0400)]
Merge git://www.denx.de/git/u-boot-marvell
Jean-Jacques Hiblot [Mon, 24 Apr 2017 09:51:32 +0000 (11:51 +0200)]
defconfig: dra7xx_evm: enable CONFIG_BLK and disk driver model for SCSI
Enable disk driver model for dra7xx_evm as dwc_ahci supports
driver model. As a consequence we must also enable CONFIG_BLK and
CONFIG_DM_USB.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Dropped CONFIG_SPL_PHY=y in sandbox_spl to fix build error:
Signed-off-by: Simon Glass <sjg@chromium.org>