review.tizen.org Git - external/binutils.git/log

Automatic date update in version.in

PR 20627: Use resume_stop to stop lwp

Commit 049a8570 (Use target_continue{,_no_signal} instead of target_resume)
replaces the code stopping lwp with target_continue_no_signal in
target_stop_and_wait, like this,

-  resume_info.thread = ptid;
-  resume_info.kind = resume_stop;
-  resume_info.sig = GDB_SIGNAL_0;
-  (*the_target->resume) (&resume_info, 1);
+  target_continue_no_signal (ptid);

the replacement is not equivalent, and it causes PR 20627.  This patch
is just to revert that change.

Regression testing it on x86_64-linux.

gdb/gdbserver:

2016-09-30  Yao Qi  <yao.qi@linaro.org>

PR gdbserver/20627
* target.c (target_stop_and_wait): Don't call
target_continue_no_signal, use resume_stop instead.

Don't assign alt twice

PR binutils/20657
* i386-dis.c (putop): Don't assign alt twice.

Add missing dependencies to BFD_H_FILES

* Makefile.am (BFD_H_FILES): Add linker.c and simple.c. Sort
as per comment at head of bfd-in2.h.
* Makefile.in: Regenerate.

[AArch64] PR target/20553, fix opcode mask for SIMD multiply by element

opcode/
PR target/20553
        * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.

gas/
        * testsuite/gas/aarch64/advsimd-fp16.s (indexed_elem): New high index
        testcases for H and S variants.  New low index testcases for D variant.
        * testsuite/gas/aarch64/advsimd-fp16.d: Update expected results.

v850 linker scripts

This should mean the 2010-10-28 change for ld -r --gc-sections can
be reverted.

* scripttempl/v850.sc: Don't reference __ctbp, __ep, __gp when
not relocating.
* scripttempl/v850_rh850.sc: Likewise.

Fix pr20528 testsuite

PR ld/20528
* testsuite/ld-elf/pr20528a.d: xfail generic elf targets. Allow
multiple .text sections for hppa-linux.
* testsuite/ld-elf/pr20528b.d: Likewise.

Remove syntactic sugar

Now that _bfd_error_handler is not a function pointer.

* aout-adobe.c: Replace (*_bfd_error_handler) (...) with
_bfd_error_handler (...) throughout.
* aout-cris.c, * aoutx.h, * archive.c, * bfd.c, * binary.c,
* cache.c, * coff-alpha.c, * coff-arm.c, * coff-h8300.c,
* coff-i860.c, * coff-mcore.c, * coff-ppc.c, * coff-rs6000.c,
* coff-sh.c, * coff-tic4x.c, * coff-tic54x.c, * coff-tic80.c,
* coff64-rs6000.c, * coffcode.h, * coffgen.c, * cofflink.c,
* coffswap.h, * cpu-arm.c, * cpu-m68k.c, * cpu-sh.c, * dwarf2.c,
* ecoff.c, * elf-eh-frame.c, * elf-m10300.c, * elf.c, * elf32-arc.c,
* elf32-arm.c, * elf32-avr.c, * elf32-bfin.c, * elf32-cr16.c,
* elf32-cris.c, * elf32-crx.c, * elf32-dlx.c, * elf32-frv.c,
* elf32-hppa.c, * elf32-i370.c, * elf32-i386.c, * elf32-lm32.c,
* elf32-m32c.c, * elf32-m32r.c, * elf32-m68hc1x.c, * elf32-m68k.c,
* elf32-mcore.c, * elf32-mep.c, * elf32-metag.c, * elf32-microblaze.c,
* elf32-mips.c, * elf32-nds32.c, * elf32-nios2.c, * elf32-or1k.c,
* elf32-pj.c, * elf32-ppc.c, * elf32-rl78.c, * elf32-s390.c,
* elf32-score.c, * elf32-score7.c, * elf32-sh.c, * elf32-sh64.c,
* elf32-sparc.c, * elf32-spu.c, * elf32-tic6x.c, * elf32-tilepro.c,
* elf32-v850.c, * elf32-vax.c, * elf32-xtensa.c, * elf64-alpha.c,
* elf64-hppa.c, * elf64-ia64-vms.c, * elf64-mips.c, * elf64-mmix.c,
* elf64-ppc.c, * elf64-s390.c, * elf64-sh64.c, * elf64-sparc.c,
* elf64-x86-64.c, * elfcode.h, * elfcore.h, * elflink.c,
* elfn32-mips.c, * elfnn-aarch64.c, * elfnn-ia64.c, * elfxx-mips.c,
* elfxx-sparc.c, * elfxx-tilegx.c, * hpux-core.c, * i386linux.c,
* ieee.c, * ihex.c, * libbfd.c, * linker.c, * m68klinux.c,
* mach-o.c, * merge.c, * mmo.c, * oasys.c, * osf-core.c, * pdp11.c,
* pe-mips.c, * peXXigen.c, * pef.c, * plugin.c, * reloc.c,
* rs6000-core.c, * sco5-core.c, * som.c, * sparclinux.c, * srec.c,
* stabs.c, * syms.c, * vms-alpha.c, * vms-lib.c, * vms-misc.c,
* xcofflink.c: Likewise.

Better ld --fatal-warnings support

* ldmain.c (default_bfd_error_handler): New function pointer.
(ld_bfd_error_handler): New function.
(main): Arrange to call it on bfd errors/warnings.
(ld_bfd_assert_handler): Enable tail call.

Make bfd_error_handler_type like vprintf

It was like printf, which means you can't use bfd_set_error_handler to
hook in a function to do something and then call the original handler.

The patch also deletes some unused functions and makes pointers local.

bfd/
* bfd-in.h: Include stdarg.h.
* bfd.c (bfd_error_handler_type): Make like vprintf.
(_bfd_error_internal): Rename from _bfd_error_handler. Make static.
(error_handler_internal): New function, split out from..
(_bfd_default_error_handler): ..here. Rename to _bfd_error_handler.
(bfd_set_error_handler): Update.
(bfd_get_error_handler, bfd_get_assert_handler): Delete.
(_bfd_assert_handler): Make static.
* coffgen.c (null_error_handler): Update params.
* elf-bfd.h (struct elf_backend_data <link_order_error_handler>):
Don't use bfd_error_handler_type.
* elf64-mmix.c (mmix_dump_bpo_gregs): Likewise.
* elfxx-target.h (elf_backend_link_order_error_handler): Default
to _bfd_error_handler.
* libbfd-in.h (_bfd_default_error_handler): Don't declare.
(bfd_assert_handler_type): Likewise.
(_bfd_error_handler): Update.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
ld/
* ldlang.c (ignore_bfd_errors): Update params.

Automatic date update in version.in

Update tests to account for the L operand being compulsory.

* gdb.arch/powerpc-power.exp <cmprb>: Update tests to account for
the compulsory L operand changes.
* gdb.arch/powerpc-power.s: Likewise.

Don't merge 2 sections with different SHF_EXCLUDE

SEC_EXCLUDE is ignored when doing a relocatable link. But we can't
merge 2 input sections with the same name when only one of them has
SHF_EXCLUDE.

PR ld/20528
* emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Don't
merge 2 sections with different SHF_EXCLUDE.
* testsuite/ld-elf/pr20528a.d: New file.
* testsuite/ld-elf/pr20528a.s: Likewise.
* testsuite/ld-elf/pr20528b.d: Likewise.
* testsuite/ld-elf/pr20528b.s: Likewise.

PR gdb/20609 - attach of JIT-debug-enabled inf 7.11.1 regression

Regression: gdb --pid $(pidof qemu-system-x86_64) stopped working with gdb 7.11.1
https://sourceware.org/bugzilla/show_bug.cgi?id=20609

It was reported for qemu-system-x86_64 but it happens for any multithreaded
inferior with a JIT debugging hook.

136613ef0c6850427317e57be1b644080ff6decb is the first bad commit
Author: Pedro Alves <palves@redhat.com>
    Fix PR gdb/19828: gdb -p <process from a container>: internal error
Message-ID: <cbdf2e04-4fa8-872a-2a23-08c9c1b26e00@redhat.com>
https://sourceware.org/ml/gdb-patches/2016-05/msg00450.html

jit_breakpoint_re_set() is specific by trying to insert a breakpoint into the
main executable, not into a shared library.  During attachment GDB thinks it
needs to use 'breakpoint always-inserted' from
breakpoints_should_be_inserted_now() as a newly attached thread is
'thread_info->executing' due to 'lwp_info->must_set_ptrace_flags' enabled and
the task not yet stopped.  This did not happen before the 'bad commit' above
which adds tracking of such thread.

GDB then fails to insert the breakpoints to invalid address as PIE executable
gets properly relocated during later phase of attachment.  One can see in the
backtraces below:
-> jit_breakpoint_re_set_internal()
later:
-> svr4_exec_displacement()

One can suppress the initial breakpoint_re_set() call as there will be another
breakpoint_re_set() done from the final post_create_inferior() call in
setup_inferior().

BTW additionally 'threads_executing' cache bool is somehow stale (somewhere is
missing update_threads_executing()).  I was trying to deal with that in my
first/second attempt below but in my final third attempt (attached) I have
left it as it is.

First attempt trying not to falsely require 'breakpoint always-inserted':
  https://people.redhat.com/jkratoch/rhbz1375553-fix1.patch
Reduced first attempt:
  https://people.redhat.com/jkratoch/rhbz1375553-fix2.patch

The third attempt suppresses breakpoint insertion until PIE executable gets
relocated by svr4_exec_displacement().  Applied.

gdb/ChangeLog
2016-09-29  Jan Kratochvil  <jan.kratochvil@redhat.com>

PR gdb/20609 - attach of JIT-debug-enabled inf 7.11.1 regression
* exec.c (exec_file_locate_attach): Add parameter defer_bp_reset.
Use it.
* gdbcore.h (exec_file_locate_attach): Add parameter defer_bp_reset.
* infcmd.c (setup_inferior): Update caller.
* remote.c (remote_add_inferior): Likewise.

gdb/testsuite/ChangeLog
2016-09-29  Jan Kratochvil  <jan.kratochvil@redhat.com>

PR gdb/20609 - attach of JIT-debug-enabled inf 7.11.1 regression
* gdb.base/jit-attach-pie.c: New file.
* gdb.base/jit-attach-pie.exp: New file.

Frame info dump: Fix bad register marks.

On S/390 we see quite often registers marked as "bad register" in the
readelf --debug-dump=frames or objdump -Wf output.

00000000 0000000000000014 00000000 CIE
      Version:               1
      Augmentation:          "zR"
      Code alignment factor: 1
      Data alignment factor: -8
      Return address column: 14
      Augmentation data:     1b

      DW_CFA_def_cfa: r15 ofs 160
      DW_CFA_nop
      DW_CFA_nop
      DW_CFA_nop

    ...

    00000050 000000000000001c 00000054 FDE cie=00000000 pc=0000000080000e58..0000000080000e84
      DW_CFA_advance_loc: 6 to 0000000080000e5e
      DW_CFA_offset: r14 at cfa-48
      DW_CFA_offset: r15 at cfa-40
      DW_CFA_advance_loc: 6 to 0000000080000e64
      DW_CFA_def_cfa_offset: 320
      DW_CFA_advance_loc: 18 to 0000000080000e76
      DW_CFA_restore: bad register: r15              <------
      DW_CFA_restore: r14
      DW_CFA_def_cfa_offset: 160

    This is triggered by this check in display_debug_frames (dwarf.c):

case DW_CFA_restore:
  if (opa >= (unsigned int) cie->ncols
      || opa >= (unsigned int) fc->ncols)
    reg_prefix = bad_reg;

cie->ncols is number of registers referenced in the CIE which is 15 due
to r14 being given as return address column.  So for the CFA_restore of
r15 a "bad register" is being printed while the same rule on r14 is ok.

The reason for this check is to prevent wild memory accesses when
reading input with corrupted register values while accessing the
col_type/col_offset arrays. However in that case r15 is a perfectly
valid register. It just happens not to be mentioned in the CIE.  Hence
restoring the CIE rule for r15 should end up with the default rule which
is DW_CFA_undefined.

This probably wasn't observed on other platforms because they either do
not use CFA_restore (x86-64) or do not issue CFA_restore on registers
with a higher number than the return address column.

binutils/ChangeLog:

2016-09-29  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

* dwarf.c (frame_display_row): Fix formatting of return address
register column.
(display_debug_frames): Ignore invalid indices into
cie->col_type/cie->col_offset arrays and default to
DW_CF_undefined instead.

Add .cfi_val_offset GAS command.

This patch adds support for .cfi_val_offset GAS pseudo command which
maps to DW_CFA_val_offset and DW_CFA_val_offset_sf.

gas/ChangeLog:

2016-09-29 Andreas Krebbel <krebbel@linux.vnet.ibm.com>

* doc/as.texinfo: Add docu for .cfi_val_offset.
* dw2gencfi.c (cfi_add_CFA_val_offset): New function.
(dot_cfi): Add case for DW_CFA_val_offset.
(output_cfi_insn): Likewise.
(cfi_pseudo_table): Add entry for cfi_val_offset.
* dw2gencfi.h: Add prototype for cfi_add_CFA_val_offset.
* testsuite/gas/cfi/cfi-common-8.d: New test.
* testsuite/gas/cfi/cfi-common-8.s: New test.
* testsuite/gas/cfi/cfi.exp: Run cfi-common-8 testcase.

binutils/ChangeLog:

2016-09-29 Andreas Krebbel <krebbel@linux.vnet.ibm.com>

* dwarf.c (display_debug_frames): Adjust output line.

Disallow 3-operand cmp[l][i] for ppc64

cmp[l][o] get an optional L field only when generating 32-bit code.
dcbf, tlbie and tlbiel keep their optional L field, ditto for R field
of tbegin. cmprb, tsr., wlcr[all] and mtsle all change to a
compulsory L field.

L field of dcbf and wclr is 2 bits.

PR 20641
include/
* opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
opcodes/
* ppc-opc.c (L): Make compulsory.
(LOPT): New, optional form of L.
(HTM_R): Define as LOPT.
(L0, L1): Delete.
(L32OPT): New, optional for 32-bit L.
(L2OPT): New, 2-bit L for dcbf.
(SVC_LEC): Update.
(L2): Define.
(insert_l0, extract_l0, insert_l1, extract_l2): Delete.
(powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
<dcbf>: Use L2OPT.
<tlbiel, tlbie>: Use LOPT.
<wclr, wclrall>: Use L2.
gas/
* config/tc-ppc.c (md_assemble): Handle PPC_OPERAND_OPTIONAL32.
* testsuite/gas/ppc/power8.s: Provide tbegin. operand.
* testsuite/gas/ppc/power9.d: Update cmprb disassembly.

Display .gnu.attributes tags for powerpc64

* readelf.c (process_arch_specific): Call process_power_specific
for EM_PPC64.

Automatic date update in version.in

Fix PR 20345 - call_function_by_hand_dummy: Assertion `tp->thread_fsm == &sm->thread_fsm' failed

If you run an infcall from the command line, and immediately after run
some other command, GDB incorrectly processes the other command before
the infcall finishes.

The problem is that the fix for PR gdb/20418 (Problems with
synchronous commands and new-ui, git 3eb7562a983b) moved the
add_file_handler/delete_file_handler calls out of
target_terminal_$foo, and missed adjusting the infcall code.

gdb/ChangeLog:
2016-09-28 Pedro Alves <palves@redhat.com>

* infcall.c (run_inferior_call): Remove input from the event
loop while running the infcall.

gdb/testsuite/ChangeLog:
2016-09-28 Pedro Alves <palves@redhat.com>

* gdb.base/infcall-input.c: New file.
* gdb.base/infcall-input.exp: New file.

Small improvements to the remote protocol manual

I was reading the gdb RSP manual recently and I found a number of
small problems in the documentation.  This patch attempts to improve
these areas.  Specfically:

* The term "memory breakpoint" is used only in this section of the
  manual, and there inconsistently.  I found this term confusing --
  initially I thought it might be a watchpoint.  This patch changes it
  to use the term "software breakpoint", which is used in the rest of
  the manual.

* The z0 packet didn't document how "kind" was written.  And, it had a
  stray link to the architecture-specific protocol details node.  This
  patch moves this link to a better spot.

* The z1 patch didn't document that it accepts cmd_list.

* I couldn't find any text saying what response is given to a command
  like vCont in non-stop mode.  The answer is that OK is sent, and
  then a stop reply is sent as a notification.  This patch adds a note
  about this.

* The "create" stop reply did not document that the "R" argument is
  ignored.

* The "W", "X", and "w" packets did not document how the "AA" part is
  formatted.

* The %Stop notification example said "%%Stop", but I think this is
  incorrect.

2016-09-28  Tom Tromey  <tom@tromey.com>

* gdb.texinfo (Packets) <z0>: Use "software breakpoint" rather
than "memory breakpoint".  Further document "kind".  Move
protocol-details link earlier.
<z1>: Document the cmd_list argument.  Fix typo.
<g>: Remove incorrect sentence.
(Stop Reply Packets): Document "OK" response to requests when in
non-stop mode.
<swbreak>: Use "software breakpoint" rather than "memory
breakpoint".
<create>: Document that "R" is ignored.
<W, X, w>: Document formatting of "AA".
(Notification Packets): Use "%Stop", not "%%Stop".

Fix seg-fault in the linker introduced by the previous delta.

PR ld/20636
* elf-bfd.h (struct elf_backend_data): Delete
elf_backend_count_output_relocs callback and add
elf_backend_update_relocs.
* elf32-arm.c (elf32_arm_count_output_relocs): Deleted.
(emit_relocs): Deleted.
(elf32_arm_emit_relocs): Deleted.
(elf_backend_emit_relocs): Updated not to use the old functions.
(elf32_arm_update_relocs): New function.
(elf_backend_update_relocs): New define.
* elflink.c (bfd_elf_final_link): Add additional_reloc_count to the
relocation count. Call elf_backend_emit_relocs.
(_bfd_elf_size_reloc_section): Do not call
elf_backend_count_output_relocs.
* elfxx-target.h (elf_backend_count_output_relocs): Deleted.
(elf_backend_update_relocs): New define.

Automatic date update in version.in

[ARM] PR ld/20608 Relocation truncated to fit: R_ARM_THM_JUMP24 for relocation to PLT entry

2016-09-28 Christophe Lyon <christophe.lyon@linaro.org>

PR ld/20608
bfd/
* elf32-arm.c (arm_type_of_stub): Handle the case when the pre-PLT
Thumb-ARM stub is too far.

ld
* testsuite/ld-arm/arm-elf.exp: Handle new testcase.
* testsuite/ld-arm/farcall-mixed-app2.d: New file.
* testsuite/ld-arm/farcall-mixed-app2.r: Likewise.
* testsuite/ld-arm/farcall-mixed-app2.s: Likewise.
* testsuite/ld-arm/farcall-mixed-app2.sym: Likewise.

Don't treat as separate symbols if unversioned symbol is undefined.

When we see an unversioned symbol reference in a shared library, followed
by a default definition of the symbol in another shared library, we were
treating them as separate symbols. That should only happen when both are
definitions.

gold/
PR gold/20238
* symtab.cc (Symbol_table::define_default_version): Check that
unversioned symbol is defined.

Add archives and make stamps to the .gitignore file.

Ensure that the timestamp in PE/COFF headers is always initialised.

PR ld/20634
* peXXigen.c (_bfd_XXi_only_swap_filehdr_out): Put 0 in the
timestamp field if real time values are not being stored.

Detect the magic address of EXC_RETURN in ARM coretx-m profile

On ARMv6-M and ARMv7-M, the exception return address is sort of magic
address defined by the manual. This patch is to let GDB well handle
these magic addresses.

2016-09-27 Fredrik Hederstierna <fredrik.hederstierna@verisure.com>

* arm-tdep.c (arm_m_addr_is_magic): New function.
(arm_addr_bits_remove): Call arm_m_addr_is_magic.
(arm_m_exception_unwind_sniffer): Likewise.

Automatic date update in version.in

tc-xtensa.c: fixup xg_reverse_shift_count typo

gas/ChangeLog:

2016-09-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>

* config/tc-xtensa.c (xg_reverse_shift_count): Pass cnt_arg instead of
cnt_argp to concat.

When building target binaries, ensure that the warning flags selected for the command line match the target compiler.

bfd * warning.m4 (AC_EGREP_CPP_FOR_BUILD): Introduce macro
to verify CC_FOR_BUILD compiler.
(AM_BINUTILS_WARNINGS): Introduce ac_cpp_for_build variable
and add CC_FOR_BUILD compiler checks.
* Makefile.in: Regenerate.
* configure: Likewise.
* doc/Makefile.in: Likewise.

binutils * Makefile.am: Replace AM_CLFAGS with AM_CFLAGS_FOR_BUILD
when building with CC_FOR_BUILD compiler.
* Makefile.in: Regenerate.
* configure: Likewise.
* doc/Makefile.in: Likewise.

gas * Makefile.in: Regenerate.
* configure: Likewise.
* doc/Makefile.in: Likewise.

gold * Makefile.in: Regenerate.
* configure: Likewise.
* testsuite/Makefile.in: Likewise.

gprof * Makefile.in: Regenerate.
* configure: Likewise.

ld * Makefile.in: Regenerate.
* configure: Likewise.

opcodes * Makefile.in: Regenerate.
* configure: Likewise.

Fix the calculation of AMD64_PCRQUAD relocations.

PR ld/17955
* coff-x86_64.c (coff_amd64_rtype_to_howto): Use an 8 byte offset
for R_AMD64_PCRQUAD relocations.

[ARC] ISA alignment.

include/
2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>

* opcode/arc.h (insn_class_t): Add two new classes.

opcodes/
2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>

* arc-ext-tbl.h (EXTINSN2OPF): Define.
(EXTINSN2OP): Use EXTINSN2OPF.
(bspeekm, bspop, modapp): New extension instructions.
* arc-opc.c (F_DNZ_ND): Define.
(F_DNZ_D): Likewise.
(F_SIZEB1): Changed.
(C_DNZ_D): Define.
(C_HARD): Changed.
* arc-tbl.h (dbnz): New instruction.
(prealloc): Allow it for ARC EM.
(xbfu): Likewise.

PowerPC .gnu.attributes

This patch extends Tag_GNU_Power_ABI_FP to cover long double ABIs,
makes the assembler warn about undefined tag values, and removes
similar warnings from the linker.  I think it is better to not
warn in the linker about undefined tag values as future extensions to
the tags then won't result in likely bogus warnings.  This is
consistent with the fact that an older linker won't warn on an
entirely new tag.

include/
* elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment.
bfd/
* elf-bfd.h (_bfd_elf_ppc_merge_fp_attributes): Declare.
* elf32-ppc.c (_bfd_elf_ppc_merge_fp_attributes): New function.
(ppc_elf_merge_obj_attributes): Use it.  Don't copy first file
attributes, merge them.  Don't warn about undefined tag bits,
or copy unknown values to output.
* elf64-ppc.c (ppc64_elf_merge_private_bfd_data): Call
_bfd_elf_ppc_merge_fp_attributes.
binutils/
* readelf.c (display_power_gnu_attribute): Catch truncated section
for all powerpc attributes.  Display long double ABI.  Don't
capitalize words, except for names.  Show known bits of tag values
when some unknown bits are present.  Whitespace fixes.
gas/
* config/tc-ppc.c (ppc_elf_gnu_attribute): New function.
(md_pseudo_table <ELF>): Handle "gnu_attribute".
ld/
* testsuite/ld-powerpc/attr-gnu-4-4.s: Delete.
* testsuite/ld-powerpc/attr-gnu-4-14.d: Delete.
* testsuite/ld-powerpc/attr-gnu-4-24.d: Delete.
* testsuite/ld-powerpc/attr-gnu-4-34.d: Delete.
* testsuite/ld-powerpc/attr-gnu-4-41.d: Delete.
* testsuite/ld-powerpc/attr-gnu-4-32.d: Adjust expected warning.
* testsuite/ld-powerpc/attr-gnu-8-23.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-01.d: Adjust expected output.
* testsuite/ld-powerpc/attr-gnu-4-02.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-03.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-10.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-11.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-20.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-22.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-33.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-8-11.d: Likewise.
* testsuite/ld-powerpc/powerpc.exp: Don't run deleted tests.

[GOLD] regen testsuite/Makefile.in

[GOLD] warning fixes

* aarch64.cc (Target_aarch64::is_erratum_835769_sequence): Avoid
compiler warning.
* output.cc (Output_segment::set_section_addresses): Likewise.

Fix nm potential buffer overflow

get_coff_symbol_type had a potenial buffer overflow even with
untranslated messages.

* nm.c (get_elf_symbol_type): Don't use sprintf with translated
strings, use asprintf instead.
(get_coff_symbol_type): Likewise.

Call debug_exit in linux_wait_1

When I read the GDBserver debug message, I find the "entering" of
linux_wait_1 doesn't match the "existing" of linux_wait_1. Looks
we don't call debug_exit somewhere in linux_wait_1 on return.

gdb/gdbserver:

2016-09-26 Yao Qi <yao.qi@linaro.org>

* linux-low.c (linux_wait_1): Call debug_exit.

Automatic date update in version.in

Fix a use of target_mourn_inferior in windows-nat.c

One use of target_mourn_interior seems to have been missed in bc1e6c81

gdb/ChangeLog:

2016-09-23 Jon Turney <jon.turney@dronecode.org.uk>

* windows-nat.c (windows_delete_thread): Adjusting call to
target_mourn_inferior to include ptid_t argument.

Automatic date update in version.in

Use std::string rather than dyn-string

This patch changes some code in cli-cmds.c to use std::string rather
than dyn-string, removing some cleanups.  Since this was the last use
of dyn-string in gdb, this patch also removes
make_cleanup_dyn_string_delete.

2016-09-23  Tom Tromey  <tom@tromey.com>

* utils.h (make_cleanup_dyn_string_delete): Remove declaration.
* utils.c: Don't include dyn-string.h.
(do_dyn_string_delete, make_cleanup_dyn_string_delete): Remove.
* cli/cli-cmds.c: Include <string>.  Don't include dyn-string.h.
(argv_to_string): Rename.  Change return type to std::string.
(alias_command): Use std::string.

Use std::vector in objfiles.c

This patch changes a spot in objfiles.c to use a std::vector, removing
a cleanup.

2016-09-23 Tom Tromey <tom@tromey.com>

* objfiles.c: Include <vector>.
(objfile_relocate): Use std::vector.

Use std::string, std::vector in rust-lang.c

This patch changes some spots in rust-lang.c to use std::string or
std::vector, removing some cleanups.

2016-09-23 Tom Tromey <tom@tromey.com>

* rust-lang.c: Include <string> and <vector>.
(rust_evaluate_funcall): Use std::vector, std::string.
(rust_evaluate_subexp): Use std::string.
(rust_lookup_symbol_nonlocal): Use std::string.

Use std::string in cp-namespace.c

This changes a few spots in cp-namespace.c to use std::string,
removing some cleanups.

2016-09-23 Tom Tromey <tom@tromey.com>

* cp-namespace.c: Include <string>.
(cp_search_static_and_baseclasses)
(cp_lookup_symbol_imports_or_template, find_symbol_in_baseclass):
Use std::string.

Use std::string in break-catch-sig.c

This changes one spot in break-catch-sig.c to use std::string,
removing some cleanups.

2016-09-23 Tom Tromey <tom@tromey.com>

* break-catch-sig.c: Include <string>.
(signal_catchpoint_print_one): Use std::string.

Remove some unnecessary code

This patch removes some unnecessary code.  In particular,
terminate_minimal_symbol_table is declared in minsyms.h, so it doesn't
need to be declared in objfiles.h as well.  And,
restore_ui_out_closure was rendered unnecessary by an earlier patch,
so the structure definition can be removed now.

I'm checking this in as obvious.

Tested by rebuilding on x86-64 Fedora 24 with --enable-targets=all;
which would notice any missing includes of minsyms.h.

2016-09-23  Tom Tromey  <tom@tromey.com>

* utils.c (struct restore_ui_out_closure): Remove.
* objfiles.h (terminate_minimal_symbol_table): Don't declare.

Replace sprintf with xsnprintf in nat/linux-osdata.c

I see the following build warning when I build GDB with GCC trunk.

../../binutils-gdb/gdb/nat/linux-osdata.c: In function ‘LONGEST linux_xfer_osdata_fds(gdb_byte*, ULONGEST, ULONGEST)’:
../../binutils-gdb/gdb/nat/linux-osdata.c:767:1: error: ‘%s’ directive writing between 0 and 255 bytes into a region of size 11 [-Werror=format-length=]
linux_xfer_osdata_fds (gdb_byte *readbuf,
^~~~~~~~~~~~~~~~~~~~~
../../binutils-gdb/gdb/nat/linux-osdata.c:800:51: note: format output between 7 and 262 bytes into a destination of size 17
        sprintf (procentry, "/proc/%s", dp->d_name);
                                                   ^
../../binutils-gdb/gdb/nat/linux-osdata.c: In function ‘LONGEST linux_xfer_osdata_threads(gdb_byte*, ULONGEST, ULONGEST)’:
../../binutils-gdb/gdb/nat/linux-osdata.c:555:1: error: ‘%s’ directive writing between 0 and 255 bytes into a region of size 11 [-Werror=format-length=]
linux_xfer_osdata_threads (gdb_byte *readbuf,
^~~~~~~~~~~~~~~~~~~~~~~~~
../../binutils-gdb/gdb/nat/linux-osdata.c:588:51: note: format output between 7 and 262 bytes into a destination of size 17
        sprintf (procentry, "/proc/%s", dp->d_name);
                                                   ^
cc1plus: all warnings being treated as errors

The warning is a false positive, but we can workaround it by replacing
sprintf with xsnprintf.  On the other hand, it is always preferred to
use xsnprintf.

gdb:

2016-09-23  Yao Qi  <yao.qi@linaro.org>

* nat/linux-osdata.c (linux_xfer_osdata_threads): Replace
sprintf with xsnprintf.
(linux_xfer_osdata_fds): Likewise.

gdb: Replace operator new / operator new[]

If xmalloc fails allocating memory, usually because something tried a
huge allocation, like xmalloc(-1) or some such, GDB asks the user what
to do:

  .../src/gdb/utils.c:1079: internal-error: virtual memory exhausted.
  A problem internal to GDB has been detected,
  further debugging may prove unreliable.
  Quit this debugging session? (y or n)

If the user says "n", that throws a QUIT exception, which is caught by
one of the multiple CATCH(RETURN_MASK_ALL) blocks somewhere up the
stack.

The default implementations of operator new / operator new[] call
malloc directly, and on memory allocation failure throw
std::bad_alloc.  Currently, if that happens, since nothing catches it,
the exception escapes out of main, and GDB aborts from unhandled
exception.

This patch replaces the default operator new variants with versions
that, just like xmalloc:

#1 - Raise an internal-error on memory allocation failure.

#2 - Throw a QUIT gdb_exception, so that the exact same CATCH blocks
      continue handling memory allocation problems.

A minor complication of #2 is that operator new can _only_ throw
std::bad_alloc, or something that extends it:

  void* operator new (std::size_t size) throw (std::bad_alloc);

That means that if we let a gdb QUIT exception escape from within
operator new, the C++ runtime aborts due to unexpected exception
thrown.

So to bridge the gap, this patch adds a new gdb_quit_bad_alloc
exception type that inherits both std::bad_alloc and gdb_exception,
and throws _that_.

If we decide that we should be catching memory allocation errors in
fewer places than all the places we currently catch them (everywhere
we use RETURN_MASK_ALL currently), then we could change operator new
to throw plain std::bad_alloc then.  But I'm considering such a change
as separate matter from this one -- it'd make sense to do the same to
xmalloc at the same time, for instance.

Meanwhile, this allows using new/new[] instead of xmalloc/XNEW/etc.
without losing the "virtual memory exhausted" internal-error
safeguard.

Tested on x86_64 Fedora 23.

gdb/ChangeLog:
2016-09-23  Pedro Alves  <palves@redhat.com>

* Makefile.in (SFILES): Add common/new-op.c.
(COMMON_OBS): Add common/new-op.o.
(new-op.o): New rule.
* common/common-exceptions.h: Include <new>.
(struct gdb_quit_bad_alloc): New type.
* common/new-op.c: New file.

gdb/gdbserver/ChangeLog:
2016-09-23  Pedro Alves  <palves@redhat.com>

* Makefile.in (SFILES): Add common/new-op.c.
(OBS): Add common/new-op.o.
(new-op.o): New rule.

Delete relocations associatesd with deleted exidx entries.

PR ld/20595
ld * testsuite/ld-arm/unwind-4.d: Add -q option to linker command
line and -r option to objdump command line. Match emitted relocs
to make sure that superflous relocs are not generated.

bfd * elf-bfd.h (struct elf_backend_data): Add
elf_backend_count_output_relocs callback to count relocations in
the final output.
* elf-arm.c (elf32_arm_add_relocation): Deleted.
(elf32_arm_write_section): Move additional relocation to emit_relocs.
(elf32_arm_count_output_relocs): New function.
(emit_relocs): New function.
(elf32_arm_emit_relocs): New function.
(elf32_arm_vxworks_emit_relocs): New function.
(elf_backend_emit_relocs): Updated to use the new functions.
(elf_backend_count_output_relocs): New define.
* bfd/elflink.c (bfd_elf_final_link): Do not add additional_reloc_count
to the relocation count.
(_bfd_elf_link_size_reloc_section): Use callback to count the
relocations which will be in output.
(_bfd_elf_default_count_output_relocs): New function.
* bfd/elfxx-target.h (elf_backend_count_output_relocs): New define.

S/390: Move start of 64 bit binaries from 2GB to 256MB.

ld/ChangeLog:

2016-09-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com>

* emulparams/elf64_s390.sh: Change TEXT_START_ADDR to 256MB.
* testsuite/ld-s390/tlsbin_64.dd: Adjust testcase accordingly.
* testsuite/ld-s390/tlsbin_64.rd: Likewise.

Automatic date update in version.in

Close gdbserver in mi_gdb_exit

In commit 6423214f (testsuite: Don't use expect_background to reap
gdbserver), we override gdb_exit in lib/gdbserver-support.exp, so
that we can close gdbserver first.  However, we don't close gdbserver
in mi_gdb_exit.  This makes a problem in my aarch64 mulit-arch testing,
in which I run some mi tests, mi-watch.exp for example, in different
variations (aarch64 and arm),

Schedule of variations:
    junor0-2
    junor0-2-arm/-marm
    junor0-2-arm/-mthumb

When the test is done in the first variation (aarch64), test case is
recompiled for arm, but GDBserver with aarch64 program is still
running.  When the second variation is started, GDB loads arm program,
but GDBserver still loads aarch64 program because the old GDBserver
process is using it.  We'll get,

47-target-select remote junor0-2:2350^M
&"warning: Selected architecture arm is not compatible with reported target architecture aarch64\n"^M
&"warning: Architecture rejected target-supplied description\n"

This patch fixes this problem by closing GDBserver in mi_gdb_exit.

gdb/testsuite:

2016-09-22  Yao Qi  <yao.qi@linaro.org>

* lib/gdbserver-support.exp: Rename mi_gdb_exit.
(gdb_exit): Rename it to ...
(gdbserver_gdb_exit): ...  Close GDBserver.
(gdb_exit): New proc, call gdbserver_gdb_exit.
(mi_gdb_exit): Likewise.

Fix build breakage from commit 6ec2b2

I was notified by buildbot that my patch (commit 6ec2b2) has broken the build
on x86_64:

../../binutils-gdb/gdb/rs6000-tdep.c: In function int ppc_process_record_op31(gdbarch*, regcache*, CORE_ADDR, uint32_t):
../../binutils-gdb/gdb/rs6000-tdep.c:4705:50: error: cannot convert CORE_ADDR* {aka long unsigned int*} to ULONGEST* {aka long long unsigned int*} for argument 3 to register_status regcache_raw_read_unsigned(regcache*, int, ULONGEST*)
         tdep->ppc_gp0_regnum + PPC_RA (insn), &ea);
                                                  ^
../../binutils-gdb/gdb/rs6000-tdep.c:4718:50: error: cannot convert CORE_ADDR* {aka long unsigned int*} to ULONGEST* {aka long long unsigned int*} for argument 3 to register_status regcache_raw_read_unsigned(regcache*, int, ULONGEST*)
         tdep->ppc_gp0_regnum + PPC_RA (insn), &ea);
                                                  ^
The patch below should fix it.

gdb/ChangeLog:
2016-09-22  Edjunior Barbosa Machado  <emachado@linux.vnet.ibm.com>

* rs6000-tdep.c (ppc_process_record_op31): Fix
regcache_raw_read_unsigned call using the correct parameter type.

Use gdbserver-base in remote-gdbserver-on-localhost.exp

This patch is to make remote-gdbserver-on-localhost.exp use gdbserver-base
and remove duplicated code.

gdb/testsuite:

2016-09-22 Yao Qi <yao.qi@linaro.org>

* boards/gdbserver-base.exp (gdb_server_prog): Set the absolute
path.
* boards/remote-gdbserver-on-localhost.exp: Use gdbserver-base.
Remove duplication.

Report failed attempts to locate DT_NEEDED files when --verbose is in effect.

* emultempl/elf32.em (_try_needed): In verbose mode, report failed
attempts to find a needed library.

arc: Fix ARI warning for printf(%p)

Replace printf ("%p") with printf ("%s", host_address_to_string ()). Printing
host addrss might make sense here because pointers can be null and this would
affect how function behaves.

This particular warning is printed only when option -Wari is passed to
contrib/ari/gdb_ari.sh

gdb/ChangeLog:

* arc-tdep.c: Fix ARI warning for printf(%p).

Remove legacy basepri_mask MRS/MSR special reg

2016-09-22 Thomas Preud'homme <thomas.preudhomme@arm.com>

gas/
* config/tc-arm.c (v7m_psrs): Remove BASEPRI_MASK MRS/MSR special
register and redundant basepri_max.

Check the right proc name

In lib/gdbserver-support.exp, we rename gdb_exit to
gdbserver_orig_gdb_exit, but we check the existence gdbserver_gdb_exit.
We should check gdbserver_orig_gdb_exit instead. Looks it is a typo
or an oversight.

gdb/testsuite:

2016-09-22 Yao Qi <yao.qi@linaro.org>

* lib/gdbserver-support.exp: Check the existence of
gdbserver_orig_gdb_exit rather than gdbserver_gdb_exit.

Automatic date update in version.in

Add myself as a write-after-approval GDB maintainer

gdb/ChangeLog:

* MAINTAINERS (Write After Approval): Add Anton Kolesov.

arc: New Synopsys ARC port

ARC is a family of licensable processors developed by Synopsys.

This is an initial patch that doesn't yet support some of the features, that
are already available in Synopsys' fork of GDB, namely:

  * longjmp support
  * signal frame handling
  * prologue analysis
  * Linux targets support
  * native Linux support

ARC cores are configurable and extensible, which means from debugger
perspective that some registers and debug capabilities are optional, therefore
it is up to the GDB stub to determine exact list of register available on
target and supply it to GDB via XML target descriptions.  List of registers
that is known to GDB and is required is intentionally kept small to simplify
requirements to GDB stub and implementation of a GDB client.

gdb/ChangeLog:

* Makefile.in (ALL_TARGET_OBS): Add arc-tdep.o.
(HFILES_NO_SRCDIR): Add arc-tdep.h.
(ALLDEPFILES): Add arc-tdep.c.
* NEWS: Mention new ARC port.
* configure.tgt: Add ARC.
* arc-tdep.c: New file.
* arc-tdep.h: New file.
* features/Makefile (XMLTOC): Add arc-v2.xml and arc-arcompact.xml.
* features/arc-v2.xml: New file.
* features/arc-v2.c: New file (generated).
* features/arc-arcompact.xml: New file.
* features/arc-arcompact.c: New file (generated).

gdb/doc/ChangeLog:

* gdb.texinfo (Embedded Processors): Document ARC.
(Synopsys ARC): New section.
(Standard Target Features): Document ARC features.
(ARC Features): New section.

gdb/testsuite/ChangeLog:

* gdb.xml/tdesc-regs.exp: set core-regs for arc*-*-elf32.

ppc: Fix return of instruction handlers in ppc_process_record_op63

some instruction handlers in ppc_process_record_op63() seem to be missing
return or incorrectly using break. This patch aims to fix that.

gdb/ChangeLog:
2016-09-21 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>

* rs6000-tdep.c (ppc_process_record_op63): Fix return of instruction
handlers.

PR gdb/20604 - fix "quit" when an invalid expression is used

This fixes PR gdb/20604.  The bug here is that passing an invalid
expression to "quit" -- e.g., "quit()" -- causes gdb to enter a
non-functioning state.

The immediate problem is that quit_force resets the terminal before
evaluating the expression.  However, it seemed to me that it doesn't
really make sense to pass the quit_force argument to kill_or_detach
(which passes it to to_detach), first because conflating the exit
status for "quit" and the signal to pass when detaching doesn't make
sense, and second because to_detach implementations generally only
accept a constant here, while "quit" accepts an expression.  So, I
removed that.

As an aside, I think the "detach SIGNO" functionality is not
documented.

Built and regtested on x86-64 Fedora 24.

2016-09-21  Tom Tromey  <tom@tromey.com>

PR gdb/20604:
* top.h (quit_force): Update.
* top.c (quit_force): Changed type of first argument.  Don't
evaluate expression.  Pass NULL to kill_or_detach.
* cli/cli-cmds.c (quit_command): Evaluate "args".

2016-09-21  Tom Tromey  <tom@tromey.com>

PR gdb/20604:
* gdb.base/quit.exp: New file.

Update and add .gitignore's

This patch adds a bunch of generated files to gdb's gitignore files.
There are still a bunch of "stamp" files that are not ignored, but I
think the rule for them should be put in the top-level gitignore.

Users and developers are encouraged to build out-of-tree, but some
people prefer the simplicity to build in-tree, so it should be useful
for them.

gdb/ChangeLog:

* .gitignore: Ignore more files.
* data-directory/.gitignore: Likewise.

gdb/doc/ChangeLog:

* .gitignore: New file.

gdb/gdbserver/ChangeLog:

* .gitinore: Ignore more files.

gdb/testsuite/ChangeLog:

* .gitignore: New file.

ppc: Add Power ISA 3.0/POWER9 instructions record support

gdb/ChangeLog:
2016-09-21 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>

* rs6000-tdep.c (PPC_DQ): New macro.
(ppc_process_record_op4): Add Power ISA 3.0 instructions.
(ppc_process_record_op19): Likewise.
(ppc_process_record_op31): Likewise.
(ppc_process_record_op59): Likewise.
(ppc_process_record_op60): Likewise.
(ppc_process_record_op63): Likewise.
(ppc_process_record): Likewise.
(ppc_process_record_op61): New function.

[AArch64] Print spaces after commas in addresses

I got an off-list request to make the AArch64 disassembler print
spaces after commas in addresses. This patch does that.

The same code is used to print operands in "did you mean" errors,
so to keep things consistent, the patch also prints spaces between
operands in those messages.

opcodes/
* aarch64-opc.c (print_immediate_offset_address): Print spaces
after commas in addresses.
(aarch64_print_operand): Likewise.

gas/
* config/tc-aarch64.c (print_operands): Print spaces between
operands.
* testsuite/gas/aarch64/ilp32-basic.d: Expect spaces after ","
in addresses.
* testsuite/gas/aarch64/ldst-reg-imm-post-ind.d: Likewise.
* testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d: Likewise.
* testsuite/gas/aarch64/ldst-reg-pair.d: Likewise.
* testsuite/gas/aarch64/ldst-reg-reg-offset.d: Likewise.
* testsuite/gas/aarch64/ldst-reg-uns-imm.d: Likewise.
* testsuite/gas/aarch64/ldst-reg-unscaled-imm.d: Likewise.
* testsuite/gas/aarch64/reloc-insn.d: Likewise.
* testsuite/gas/aarch64/sve.d: Likewise.
* testsuite/gas/aarch64/symbol.d: Likewise.
* testsuite/gas/aarch64/system.d: Likewise.
* testsuite/gas/aarch64/tls-desc.d: Likewise.
* testsuite/gas/aarch64/sve-invalid.l: Expect spaces after ","
in suggested alternatives.
* testsuite/gas/aarch64/verbose-error.l: Likewise.

ld/
* testsuite/ld-aarch64/emit-relocs-28.d: Expect spaces after ","
in addresses.
* testsuite/ld-aarch64/emit-relocs-301-be.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-301.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-302-be.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-302.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-310-be.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-310.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-313.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-515-be.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-515.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-516-be.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-516.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-531.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-532.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-533.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-534.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-535.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-536.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-537.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-538.d: Likewise.
* testsuite/ld-aarch64/erratum835769.d: Likewise.
* testsuite/ld-aarch64/erratum843419.d: Likewise.
* testsuite/ld-aarch64/farcall-b-plt.d: Likewise.
* testsuite/ld-aarch64/farcall-bl-plt.d: Likewise.
* testsuite/ld-aarch64/gc-plt-relocs.d: Likewise.
* testsuite/ld-aarch64/ifunc-21.d: Likewise.
* testsuite/ld-aarch64/ifunc-7c.d: Likewise.
* testsuite/ld-aarch64/tls-desc-ie.d: Likewise.
* testsuite/ld-aarch64/tls-large-desc-be.d: Likewise.
* testsuite/ld-aarch64/tls-large-desc.d: Likewise.
* testsuite/ld-aarch64/tls-large-ie-be.d: Likewise.
* testsuite/ld-aarch64/tls-large-ie.d: Likewise.
* testsuite/ld-aarch64/tls-relax-all.d: Likewise.
* testsuite/ld-aarch64/tls-relax-gd-ie.d: Likewise.
* testsuite/ld-aarch64/tls-relax-gdesc-ie-2.d: Likewise.
* testsuite/ld-aarch64/tls-relax-gdesc-ie.d: Likewise.
* testsuite/ld-aarch64/tls-relax-large-desc-ie-be.d: Likewise.
* testsuite/ld-aarch64/tls-relax-large-desc-ie.d: Likewise.
* testsuite/ld-aarch64/tls-tiny-desc.d: Likewise.
* testsuite/ld-aarch64/tls-tiny-gd.d: Likewise.

[AArch64] Use "must" rather than "should" in error messages

One of the review comments from the SVE series was that it would
be better to use "must" rather than "should" in error messages.
I think this patch fixes all cases in the AArch64 code.
It also uses "must be" instead of "expected to be".

opcodes/
* aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
rather than "should be" or "expected to be" in error messages.

gas/
* config/tc-aarch64.c (output_operand_error_record): Use "must be"
rather than "should be" or "expected to be" in error messages.
(parse_operands): Likewise.
* testsuite/gas/aarch64/diagnostic.l: Likewise.
* testsuite/gas/aarch64/legacy_reg_names.l: Likewise.
* testsuite/gas/aarch64/sve-invalid.l: Likewise.
* testsuite/gas/aarch64/sve-reg-diagnostic.l: Likewise.

[AArch64] Add SVE condition codes

SVE defines new names for existing NZCV conditions, to reflect the
result of instructions like PTEST.  This patch adds support for these
names.

The patch also adds comments to the disassembly output to show the
alternative names of a condition code.  For example:

cinv x0, x1, cc

becomes:

      cinv x0, x1, cc  // cc = lo, ul, last

and:

b.cc f0 <...>

becomes:

      b.cc f0 <...>  // b.lo, b.ul, b.last

Doing this for the SVE names follows the practice recommended by the
SVE specification and is definitely useful when reading SVE code.
If the feeling is that it's too distracting elsewhere, we could add
an option to turn it off.

include/
* opcode/aarch64.h (aarch64_cond): Bump array size to 4.

opcodes/
* aarch64-dis.c (remove_dot_suffix): New function, split out from...
(print_mnemonic_name): ...here.
(print_comment): New function.
(print_aarch64_insn): Call it.
* aarch64-opc.c (aarch64_conds): Add SVE names.
(aarch64_print_operand): Print alternative condition names in
a comment.

gas/
* config/tc-aarch64.c (opcode_lookup): Search for the end of
a condition name, rather than assuming that it will have exactly
2 characters.
(parse_operands): Likewise.
* testsuite/gas/aarch64/alias.d: Add new condition-code comments
to the expected output.
* testsuite/gas/aarch64/beq_1.d: Likewise.
* testsuite/gas/aarch64/float-fp16.d: Likewise.
* testsuite/gas/aarch64/int-insns.d: Likewise.
* testsuite/gas/aarch64/no-aliases.d: Likewise.
* testsuite/gas/aarch64/programmer-friendly.d: Likewise.
* testsuite/gas/aarch64/reloc-insn.d: Likewise.
* testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s:
New test.

ld/
* testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments.
* testsuite/ld-aarch64/weak-undefined.d: Likewise.

Fix misplaced ChangeLog

[AArch64][SVE 32/32] Add SVE tests

This patch adds new tests for SVE. It also extends diagnostic.[sl] with
checks for some inappropriate uses of MUL and MUL VL in base AArch64
instructions.

gas/testsuite/
* gas/aarch64/diagnostic.s, gas/aarch64/diagnostic.l: Add tests for
invalid uses of MUL VL and MUL in base AArch64 instructions.
* gas/aarch64/sve-add.s, gas/aarch64/sve-add.d, gas/aarch64/sve-dup.s,
gas/aarch64/sve-dup.d, gas/aarch64/sve-invalid.s,
gas/aarch64/sve-invalid.d, gas/aarch64/sve-invalid.l,
gas/aarch64/sve-reg-diagnostic.s, gas/aarch64/sve-reg-diagnostic.d,
gas/aarch64/sve-reg-diagnostic.l, gas/aarch64/sve.s,
gas/aarch64/sve.d: New tests.

[AArch64][SVE 31/32] Add SVE instructions

This patch adds the SVE instruction definitions and associated OP_*
enum values.

include/
* opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
(OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi)
(OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P)
(OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops.

opcodes/
* aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
(OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
(OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
(OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
(OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
(OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
(OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
(OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
(OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
(OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
(OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
(OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
(OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
(OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
(OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
(OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
(OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
(OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
(OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
(OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
(OP_SVE_XWU, OP_SVE_XXU): New macros.
(aarch64_feature_sve): New variable.
(SVE): New macro.
(_SVE_INSN): Likewise.
(aarch64_opcode_table): Add SVE instructions.
* aarch64-opc.h (extract_fields): Declare.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.c (extract_fields): Make global.
(do_misc_decoding): Handle the new SVE aarch64_ops.
* aarch64-dis-2.c: Regenerate.

gas/
* doc/c-aarch64.texi: Document the "sve" feature.
* config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type.
(get_reg_expected_msg): Handle it.
(parse_operands): When parsing operands of an SVE instruction,
disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP.
(aarch64_features): Add an entry for SVE.

[AArch64][SVE 30/32] Add SVE instruction classes

The main purpose of the SVE aarch64_insn_classes is to describe how
an index into an aarch64_opnd_qualifier_seq_t is represented in the
instruction encoding. Other instructions usually use flags for this
information, but (a) we're running out of those and (b) the iclass
would otherwise be unused for SVE.

include/
* opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc)
(sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred)
(sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New
aarch64_insn_classes.

opcodes/
* aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
(FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
* aarch64-asm.c (aarch64_get_variant): New function.
(aarch64_encode_variant_using_iclass): Likewise.
(aarch64_opcode_encode): Call it.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
(aarch64_opcode_decode): Call it.

[AArch64][SVE 29/32] Add new SVE core & FP register operands

SVE uses some new fields to store W, X and scalar FP registers.
This patch adds corresponding operands.

include/
* opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd.
(AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd)
(AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise.

opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
and FP register operands.
* aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
(FLD_SVE_Vn): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(aarch64_print_operand): Handle the new SVE core and FP register
operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm-2.c: Likewise.
* aarch64-dis-2.c: Likewise.

gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE core
and FP register operands.

[AArch64][SVE 28/32] Add SVE FP immediate operands

This patch adds support for the new SVE floating-point immediate
operands.  One operand uses the same 8-bit encoding as base AArch64,
but in a different position.  The others use a single bit to select
between two values.

One of the single-bit operands is a choice between 0 and 1, where 0
is not a valid 8-bit encoding.  I think the cleanest way of handling
these single-bit immediates is therefore to use the IEEE float encoding
itself as the immediate value and select between the two possible values
when encoding and decoding.

As described in the covering note for the patch that added F_STRICT,
we get better error messages by accepting unsuffixed vector registers
and leaving the qualifier matching code to report an error.  This means
that we carry on parsing the other operands, and so can try to parse FP
immediates for invalid instructions like:

fcpy z0, #2.5

In this case there is no suffix to tell us whether the immediate should
be treated as single or double precision.  Again, we get better error
messages by picking one (arbitrary) immediate size and reporting an error
for the missing suffix later.

include/
* opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd.
(AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO)
(AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise.

opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
immediate operands.
* aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
* aarch64-opc.c (fields): Add corresponding entry.
(operand_general_constraint_met_p): Handle the new SVE FP immediate
operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
(ins_sve_float_zero_one): New inserters.
* aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
(aarch64_ins_sve_float_half_two): Likewise.
(aarch64_ins_sve_float_zero_one): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
(ext_sve_float_zero_one): New extractors.
* aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
(aarch64_ext_sve_float_half_two): Likewise.
(aarch64_ext_sve_float_zero_one): Likewise.
* aarch64-dis-2.c: Regenerate.

gas/
* config/tc-aarch64.c (double_precision_operand_p): New function.
(parse_operands): Use it to calculate the dp_p input to
parse_aarch64_imm_float.  Handle the new SVE FP immediate operands.

[AArch64][SVE 27/32] Add SVE integer immediate operands

This patch adds the new SVE integer immediate operands.  There are
three kinds:

- simple signed and unsigned ranges, but with new widths and positions.

- 13-bit logical immediates.  These have the same form as in base AArch64,
  but at a different bit position.

  In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical
  immediate <limm> is not allowed to be a valid DUP immediate, since DUP
  is preferred over DUPM for constants that both instructions can handle.

- a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}".
  In some contexts the operand is signed and in others it's unsigned.
  As an extension, we allow shifted immediates to be written as a single
  integer, e.g. "#256" is equivalent to "#1, LSL #8".  We also use the
  shiftless form as the preferred disassembly, except for the special
  case of "#0, LSL #8" (a redundant encoding of 0).

include/
* opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd.
(AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM)
(AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM)
(AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED)
(AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED)
(AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5)
(AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6)
(AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3)
(AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8)
(AARCH64_OPND_SVE_UIMM8_53): Likewise.
(aarch64_sve_dupm_mov_immediate_p): Declare.

opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
integer immediate operands.
* aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
(FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
(FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
(operand_general_constraint_met_p): Handle the new SVE integer
immediate operands.
(aarch64_print_operand): Likewise.
(aarch64_sve_dupm_mov_immediate_p): New function.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
(ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
* aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
(aarch64_ins_limm): ...here.
(aarch64_ins_inv_limm): New function.
(aarch64_ins_sve_aimm): Likewise.
(aarch64_ins_sve_asimm): Likewise.
(aarch64_ins_sve_limm_mov): Likewise.
(aarch64_ins_sve_shlimm): Likewise.
(aarch64_ins_sve_shrimm): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
(ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
* aarch64-dis.c (decode_limm): New function, split out from...
(aarch64_ext_limm): ...here.
(aarch64_ext_inv_limm): New function.
(decode_sve_aimm): Likewise.
(aarch64_ext_sve_aimm): Likewise.
(aarch64_ext_sve_asimm): Likewise.
(aarch64_ext_sve_limm_mov): Likewise.
(aarch64_top_bit): Likewise.
(aarch64_ext_sve_shlimm): Likewise.
(aarch64_ext_sve_shrimm): Likewise.
* aarch64-dis-2.c: Regenerate.

gas/
* config/tc-aarch64.c (parse_operands): Handle the new SVE integer
immediate operands.

[AArch64][SVE 26/32] Add SVE MUL VL addressing modes

This patch adds support for addresses of the form:

[<base>, #<offset>, MUL VL]

This involves adding a new AARCH64_MOD_MUL_VL modifier, which is
why I split it out from the other addressing modes.

For LD2, LD3 and LD4, the offset must be a multiple of the structure
size, so for LD3 the possible values are 0, 3, 6, .... The patch
therefore extends value_aligned_p to handle non-power-of-2 alignments.

include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
(AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
(AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
(AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.

opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
operands.
* aarch64-opc.c (aarch64_operand_modifiers): Initialize
the AARCH64_MOD_MUL_VL entry.
(value_aligned_p): Cope with non-power-of-two alignments.
(operand_general_constraint_met_p): Handle the new MUL VL addresses.
(print_immediate_offset_address): Likewise.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
(ins_sve_addr_ri_s9xvl): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
(aarch64_ins_sve_addr_ri_s6xvl): Likewise.
(aarch64_ins_sve_addr_ri_s9xvl): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
(ext_sve_addr_ri_s9xvl): New extractors.
* aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
(aarch64_ext_sve_addr_ri_s4xvl): Likewise.
(aarch64_ext_sve_addr_ri_s6xvl): Likewise.
(aarch64_ext_sve_addr_ri_s9xvl): Likewise.
* aarch64-dis-2.c: Regenerate.

gas/
* config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New
parse_shift_modes.
(parse_shift): Handle SHIFTED_MUL_VL.
(parse_address_main): Add an imm_shift_mode parameter.
(parse_address, parse_sve_address): Update accordingly.
(parse_operands): Handle MUL VL addressing modes.

[AArch64][SVE 25/32] Add support for SVE addressing modes

This patch adds most of the new SVE addressing modes and associated
operands.  A follow-on patch adds MUL VL, since handling it separately
makes the changes easier to read.

The patch also introduces a new "operand-dependent data" field to the
operand flags, based closely on the existing one for opcode flags.
For SVE this new field needs only 2 bits, but it could be widened
in future if necessary.

include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd.
(AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4)
(AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR)
(AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2)
(AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX)
(AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2)
(AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ)
(AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2)
(AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14)
(AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5)
(AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4)
(AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL)
(AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW):
Likewise.

opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
address operands.
* aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
(FLD_SVE_xs_22): New aarch64_field_kinds.
(OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
(get_operand_specific_data): New function.
* aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
FLD_SVE_xs_14 and FLD_SVE_xs_22.
(operand_general_constraint_met_p): Handle the new SVE address
operands.
(sve_reg): New array.
(get_addr_sve_reg_name): New function.
(aarch64_print_operand): Handle the new SVE address operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
(ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
(ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
* aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
(aarch64_ins_sve_addr_rr_lsl): Likewise.
(aarch64_ins_sve_addr_rz_xtw): Likewise.
(aarch64_ins_sve_addr_zi_u5): Likewise.
(aarch64_ins_sve_addr_zz): Likewise.
(aarch64_ins_sve_addr_zz_lsl): Likewise.
(aarch64_ins_sve_addr_zz_sxtw): Likewise.
(aarch64_ins_sve_addr_zz_uxtw): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
(ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
(ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
* aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
(aarch64_ext_sve_addr_ri_u6): Likewise.
(aarch64_ext_sve_addr_rr_lsl): Likewise.
(aarch64_ext_sve_addr_rz_xtw): Likewise.
(aarch64_ext_sve_addr_zi_u5): Likewise.
(aarch64_ext_sve_addr_zz): Likewise.
(aarch64_ext_sve_addr_zz_lsl): Likewise.
(aarch64_ext_sve_addr_zz_sxtw): Likewise.
(aarch64_ext_sve_addr_zz_uxtw): Likewise.
* aarch64-dis-2.c: Regenerate.

gas/
* config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New
register types.
(get_reg_expected_msg): Handle them.
(aarch64_addr_reg_parse): New function, split out from
aarch64_reg_parse_32_64.  Handle Z registers too.
(aarch64_reg_parse_32_64): Call it.
(parse_address_main): Add base_qualifier, offset_qualifier,
base_type and offset_type parameters.  Handle SVE base and offset
registers.
(parse_address): Update call to parse_address_main.
(parse_sve_address): New function.
(parse_operands): Parse the new SVE address operands.

[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED

Some SVE instructions count the number of elements in a given vector
pattern and allow a scale factor of [1, 16] to be applied to the result.
This scale factor is written ", MUL #n", where "MUL" is a new operator.
E.g.:

UQINCD X0, POW2, MUL #2

This patch adds support for this kind of operand.

All existing operators were shifts of some kind, so there was a natural
range of [0, 63] regardless of context.  This was then narrowered further
by later checks (e.g. to [0, 31] when used for 32-bit values).

In contrast, MUL doesn't really have a natural context-independent range.
Rather than pick one arbitrarily, it seemed better to make the "shift"
amount a full 64-bit value and leave the range test to the usual
operand-checking code.  I've rearranged the fields of aarch64_opnd_info
so that this doesn't increase the size of the structure (although I don't
think its size is critical anyway).

include/
* opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New
aarch64_opnd.
(AARCH64_MOD_MUL): New aarch64_modifier_kind.
(aarch64_opnd_info): Make shifter.amount an int64_t and
rearrange the fields.

opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
* aarch64-opc.c (fields): Add a corresponding entry.
(set_multiplier_out_of_range_error): New function.
(aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
(operand_general_constraint_met_p): Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
(print_register_offset_address): Use PRIi64 to print the
shift amount.
(aarch64_print_operand): Likewise.  Handle
AARCH64_OPND_SVE_PATTERN_SCALED.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_scale): New inserter.
* aarch64-asm.c (aarch64_ins_sve_scale): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_scale): New inserter.
* aarch64-dis.c (aarch64_ext_sve_scale): New function.
* aarch64-dis-2.c: Regenerate.

gas/
* config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode.
(parse_shift): Handle it.  Reject AARCH64_MOD_MUL for all other
shift modes.  Skip range tests for AARCH64_MOD_MUL.
(process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED.
(parse_operands): Likewise.

[AArch64][SVE 23/32] Add SVE pattern and prfop operands

The SVE instructions have two enumerated operands: one to select a
vector pattern and another to select a prefetch operation. The latter
is a cut-down version of the base AArch64 prefetch operation.

Both types of operand can also be specified as raw enum values such as #31.
Reserved values can only be specified this way.

If it hadn't been for the pattern operand, I would have been tempted
to use the existing parsing for prefetch operations and add extra
checks for SVE. However, since the patterns needed new enum parsing
code anyway, it seeemed cleaner to reuse it for the prefetches too.

Because of the small number of enum values, I don't think we'd gain
anything by using hash tables.

include/
* opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd.
(AARCH64_OPND_SVE_PRFOP): Likewise.
(aarch64_sve_pattern_array): Declare.
(aarch64_sve_prfop_array): Likewise.

opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
* aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
(FLD_SVE_prfop): Likewise.
* aarch64-opc.c: Include libiberty.h.
(aarch64_sve_pattern_array): New variable.
(aarch64_sve_prfop_array): Likewise.
(fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
(aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
AARCH64_OPND_SVE_PRFOP.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.

gas/
* config/tc-aarch64.c (parse_enum_string): New function.
(po_enum_or_fail): New macro.
(parse_operands): Handle AARCH64_OPND_SVE_PATTERN and
AARCH64_OPND_SVE_PRFOP.

[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predication

This patch adds qualifiers to represent /z and /m suffixes on
predicate registers.

include/
* opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
(AARCH64_OPND_QLF_P_M): Likewise.

opcodes/
* aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
AARCH64_OPND_QLF_P_[ZM].
(aarch64_print_operand): Print /z and /m where appropriate.

gas/
* config/tc-aarch64.c (vector_el_type): Add NT_zero and NT_merge.
(parse_vector_type_for_operand): Assert that the skipped character
is a '.'.
(parse_predication_for_operand): New function.
(parse_typed_reg): Parse /z and /m suffixes for predicate registers.
(vectype_to_qualifier): Handle NT_zero and NT_merge.

[AArch64][SVE 21/32] Add Zn and Pn registers

This patch adds the Zn and Pn registers, and associated fields and
operands.

include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.

opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length.  Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.

gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn.  Update the
call to parse_vector_type_for_operand.  Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.

[AArch64][SVE 20/32] Add support for tied operands

SVE has some instructions in which the same register appears twice
in the assembly string, once as an input and once as an output.
This patch adds a general mechanism for that.

The patch needs to add new information to the instruction entries.
One option would have been to extend the flags field of the opcode
to 64 bits (since we already rely on 64-bit integers being available
on the host). However, the *_INSN macros mean that it's easy to add
new information as top-level fields without affecting the existing
table entries too much. Going for that option seemed to give slightly
neater code.

include/
* opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
(AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.

opcodes/
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
(_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
(V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
* aarch64-opc.c (aarch64_match_operands_constraint): Check for
tied operands.

gas/
* config/tc-aarch64.c (output_operand_error_record): Handle
AARCH64_OPDE_UNTIED_OPERAND.

[AArch64][SVE 19/32] Refactor address-printing code

SVE adds addresses in which the base or offset are vector registers.
The addresses otherwise have the same kind of form as normal AArch64
addresses, including things like SXTW with or without a shift, UXTW
with or without a shift, and LSL.

This patch therefore refactors the address-printing code so that it
can cope with both scalar and vector registers.

opcodes/
* aarch64-opc.c (get_offset_int_reg_name): New function.
(print_immediate_offset_address): Likewise.
(print_register_offset_address): Take the base and offset
registers as parameters.
(aarch64_print_operand): Update caller accordingly. Use
print_immediate_offset_address.

[AArch64][SVE 18/32] Tidy definition of aarch64-opc.c:int_reg

Use a macro to define 31 regular registers followed by a supplied
value for 0b11111. The SVE code will also use this for vector base
and offset registers.

opcodes/
* aarch64-opc.c (BANK): New macro.
(R32, R64): Take a register number as argument
(int_reg): Use BANK.

[AArch64][SVE 17/32] Add a prefix parameter to print_register_list

This patch generalises the interface to print_register_list so
that it can print register lists involving SVE z registers as
well as AdvSIMD v ones.

opcodes/
* aarch64-opc.c (print_register_list): Add a prefix parameter.
(aarch64_print_operand): Update accordingly.

[AArch64][SVE 16/32] Use specific insert/extract methods for fpimm

FPIMM used the normal "imm" insert/extract methods, with a specific
test for FPIMM in the extract method. SVE needs to use the same
extractors, so rather than add extra checks for specific operand types,
it seemed cleaner to use a separate insert/extract method.

opcodes/
* aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
for FPIMM.
* aarch64-asm.h (ins_fpimm): New inserter.
* aarch64-asm.c (aarch64_ins_fpimm): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_fpimm): New extractor.
* aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
(aarch64_ext_fpimm): New function.
* aarch64-dis-2.c: Regenerate.

[AArch64][SVE 15/32] Add {insert,extract}_all_fields helpers

Several of the SVE operands use the aarch64_operand fields array
to store the fields that make up the operand, rather than hard-coding
the names in the C code. This patch adds helpers for inserting and
extracting those fields.

opcodes/
* aarch64-asm.c: Include libiberty.h.
(insert_fields): New function.
(aarch64_ins_imm): Use it.
* aarch64-dis.c (extract_fields): New function.
(aarch64_ext_imm): Use it.

[AArch64][SVE 14/32] Make aarch64_logical_immediate_p take an element size

SVE supports logical immediate operations on 8-bit, 16-bit and 32-bit
elements, treating them as aliases of operations on 64-bit elements in
which the immediate is replicated. This patch therefore replaces the
"32-bit/64-bit" input to aarch64_logical_immediate_p with a more
general "number of bytes" input.

opcodes/
* aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
with an esize parameter.
(operand_general_constraint_met_p): Update accordingly.
Fix misindented code.
* aarch64-asm.c (aarch64_ins_limm): Update call to
aarch64_logical_immediate_p.

[AArch64][SVE 13/32] Add an F_STRICT flag

SVE predicate operands can appear in three forms:

1. unsuffixed: "Pn"
2. with a predication type: "Pn/[ZM]"
3. with a size suffix: "Pn.[BHSD]"

No variation is allowed: unsuffixed operands cannot have a (redundant)
suffix, and the suffixes can never be dropped.  Unsuffixed Pn are used
in LDR and STR, but they are also used for Pg operands in cases where
the result is scalar and where there is therefore no choice to be made
between "merging" and "zeroing".  This means that some Pg operands have
suffixes and others don't.

It would be possible to use context-sensitive parsing to handle
this difference.  The tc-aarch64.c code would then raise an error
if the wrong kind of suffix is used for a particular instruction.

However, we get much more user-friendly error messages if we parse
all three forms for all SVE instructions and record the suffix as a
qualifier.  The normal qualifier matching code can then report cases
where the wrong kind of suffix is used.  This is a slight extension
of existing usage, which really only checks for the wrong choice of
suffix within a particular kind of suffix.

The only catch is a that a "NIL" entry in the qualifier list
specifically means "no suffix should be present" (case 1 above).
NIL isn't a wildcard here.  It also means that an instruction that
requires all-NIL qualifiers can fail to match (because a suffix was
supplied when it shouldn't have been); this requires a slight change
to find_best_match.

This patch adds an F_STRICT flag to select this behaviour.
The flag will be set for all SVE instructions.  The behaviour
for other instructions doesn't change.

include/
* opcode/aarch64.h (F_STRICT): New flag.

opcodes/
* aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.

gas/
* config/tc-aarch64.c (find_best_match): Simplify, allowing an
instruction with all-NIL qualifiers to fail to match.

[AArch64][SVE 12/32] Remove boolean parameters from parse_address_main

In the review of the original version of this series, Richard didn't
like the use of boolean parameters to parse_address_main.  I think we
can just get rid of them and leave the callers to check the addressing
modes.  As it happens, the handling of ADDR_SIMM9{,_2} already did this
for relocation operators (i.e. it used parse_address_reloc and then
rejected relocations).

The callers are already set up to reject invalid register post-indexed
addressing, so we can simply remove the accept_reg_post_index parameter
without adding any more checks.  This again creates a corner case where:

.equ x2, 1
ldr w0, [x1], x2

was previously an acceptable way of writing "ldr w0, [x1], #1" but
is now rejected.

Removing the "reloc" parameter means that two cases need to check
explicitly for relocation operators.

ADDR_SIMM9_2 appers to be unused.  I'll send a separate patch
to remove it.

This patch makes parse_address temporarily equivalent to
parse_address_main, but later patches in the series will need
to keep the distinction.

gas/
* config/tc-aarch64.c (parse_address_main): Remove reloc and
accept_reg_post_index parameters.  Parse relocations and register
post indexes unconditionally.
(parse_address): Remove accept_reg_post_index parameter.
Update call to parse_address_main.
(parse_address_reloc): Delete.
(parse_operands): Call parse_address instead of parse_address_main.
Update existing callers of parse_address and make them check
inst.reloc.type where appropriate.
* testsuite/gas/aarch64/diagnostic.s: Add tests for relocations
in ADDR_SIMPLE, SIMD_ADDR_SIMPLE, ADDR_SIMM7 and ADDR_SIMM9 addresses.
Also test for invalid uses of post-index register addressing.
* testsuite/gas/aarch64/diagnostic.l: Update accordingly.

[AArch64][SVE 11/32] Tweak aarch64_reg_parse_32_64 interface

aarch64_reg_parse_32_64 is currently used to parse address registers,
among other things.  It returns two bits of information about the
register: whether it's W rather than X, and whether it's a zero register.

SVE adds addressing modes in which the base or offset can be a vector
register instead of a scalar, so a choice between W and X is no longer
enough.  It's more convenient to pass the type of register around as
a qualifier instead.

As it happens, two callers of aarch64_reg_parse_32_64 already wanted
the information in the form of a qualifier, so the change feels pretty
natural even without SVE.

Also, the function took two parameters to control whether {W}SP
and (W|X)ZR should be accepted.  We tend to get slightly better
error messages by accepting them regardless and getting the caller
to do the check, rather than potentially treating "xzr", "sp" etc.
as constants.  This is easier to do if the function returns the
reg_entry rather than just the register number.

This does create a corner case where:

.equ sp, 1
ldr w0, [x0, sp]

was previously an acceptable way of writing "ldr w0, [x0, #1]",
but I don't think it's important to continue supporting that.
We already rejected things like:

.equ sp, 1
add x0, x1, sp

To ensure these new error messages "win" when matching against
several candidate instruction entries, we need to use the same
address-parsing code for all addresses, including ADDR_SIMPLE
and SIMD_ADDR_SIMPLE.  The next patch also relies on this.

Finally, aarcch64_check_reg_type was written in a pretty
conservative way.  It should always be equivalent to a single
bit test.

gas/
* config/tc-aarch64.c (REG_TYPE_R_Z, REG_TYPE_R_SP): New register
types.
(get_reg_expected_msg): Handle them and REG_TYPE_R64_SP.
(aarch64_check_reg_type): Simplify.
(aarch64_reg_parse_32_64): Return the reg_entry instead of the
register number.  Return the type as a qualifier rather than an
"isreg32" boolean.  Remove reject_sp, reject_rz and isregzero
parameters.
(parse_shifter_operand): Update call to aarch64_parse_32_64_reg.
Use get_reg_expected_msg.
(parse_address_main): Likewise.  Use aarch64_check_reg_type.
(po_int_reg_or_fail): Replace reject_sp and reject_rz parameters
with a reg_type parameter.  Update call to aarch64_parse_32_64_reg.
Use aarch64_check_reg_type to test the result.
(parse_operands): Update after the above changes.  Parse ADDR_SIMPLE
addresses normally before enforcing the syntax restrictions.
* testsuite/gas/aarch64/diagnostic.s: Add tests for a post-index
zero register and for a stack pointer index.
* testsuite/gas/aarch64/diagnostic.l: Update accordingly.
Also update existing diagnostic messages after the above changes.
* testsuite/gas/aarch64/illegal-lse.l: Update the error message
for 32-bit register bases.

[AArch64][SVE 10/32] Move range check out of parse_aarch64_imm_float

Since some SVE constants are no longer explicitly tied to the 8-bit
FP immediate format, it seems better to move the range checks out of
parse_aarch64_imm_float and into the callers.

gas/
* config/tc-aarch64.c (parse_aarch64_imm_float): Remove range check.
(parse_operands): Check the range of 8-bit FP immediates here instead.

[AArch64][SVE 09/32] Improve error messages for invalid floats

Previously:

        fmov d0, #2

would give an error:

        Operand 2 should be an integer register

whereas the user probably just forgot to add the ".0" to make:

        fmov d0, #2.0

This patch reports an invalid floating point constant unless the
operand is obviously a register.

The FPIMM8 handling is only relevant for SVE.  Without it:

        fmov z0, z1

would try to parse z1 as an integer immediate zero (the res2 path),
whereas it's more likely that the user forgot the predicate.  This is
tested by the final patch.

gas/
* config/tc-aarch64.c (parse_aarch64_imm_float): Report a specific
low-severity error for registers.
(parse_operands): Report an invalid floating point constant for
if parsing an FPIMM8 fails, and if no better error has been
recorded.
* testsuite/gas/aarch64/diagnostic.s,
testsuite/gas/aarch64/diagnostic.l: Add tests for integer operands
to FMOV.

[AArch64][SVE 08/32] Generalise aarch64_double_precision_fmovable

SVE has single-bit floating-point constants that don't really
have any relation to the AArch64 8-bit floating-point encoding.
(E.g. one of the constants selects between 0 and 1.)  The easiest
way of representing them in the aarch64_opnd_info seemed to be
to use the IEEE float representation directly, rather than invent
some new scheme.

This patch paves the way for that by making the code that converts IEEE
doubles to IEEE floats accept any value in the range of an IEEE float,
not just zero and 8-bit floats.  It leaves the range checking to the
caller (which already handles it).

gas/
* config/tc-aarch64.c (aarch64_double_precision_fmovable): Rename
to...
(can_convert_double_to_float): ...this.  Accept any double-precision
value that converts to single precision without loss of precision.
(parse_aarch64_imm_float): Update accordingly.

[AArch64][SVE 07/32] Replace hard-coded uses of REG_TYPE_R_Z_BHSDQ_V

To remove parsing ambiguities and to avoid register names being
accidentally added to the symbol table, the immediate parsing
routines reject things like:

.equ x0, 0
add v0.4s, v0.4s, x0

An explicit '#' must be used instead:

.equ x0, 0
add v0.4s, v0.4s, #x0

Of course, it wasn't possible to predict what other register
names might be added in future, so this behaviour was restricted
to the register names that were defined at the time.  For backwards
compatibility, we should continue to allow things like:

.equ p0, 0
add v0.4s, v0.4s, p0

even though p0 is now an SVE register.

However, it seems reasonable to extend the x0 behaviour above to
SVE registers when parsing SVE instructions, especially since none
of the SVE immediate formats are relocatable.  Doing so removes the
same parsing ambiguity for SVE instructions as the x0 behaviour removes
for base AArch64 instructions.

As a prerequisite, we then need to be able to tell the parsing routines
which registers to reject.  This patch changes the interface to make
that possible, although the set of rejected registers doesn't change
at this stage.

gas/
* config/tc-aarch64.c (parse_immediate_expression): Add a
reg_type parameter.
(parse_constant_immediate): Likewise, and update calls.
(parse_aarch64_imm_float): Likewise.
(parse_big_immediate): Likewise.
(po_imm_nc_or_fail): Update accordingly, passing down a new
imm_reg_type variable.
(po_imm_of_fail): Likewise.
(parse_operands): Likewise.

[AArch64][SVE 06/32] Generalise parse_neon_reg_list

Rename parse_neon_reg_list to parse_vector_reg_list and take
in the required register type as an argument. Later patches
will reuse the function for SVE registers.

gas/
* config/tc-aarch64.c (parse_neon_reg_list): Rename to...
(parse_vector_reg_list): ...this and take a register type
as input.
(parse_operands): Update accordingly.