Eric Anholt [Thu, 9 Apr 2020 17:45:24 +0000 (10:45 -0700)]
freedreno/ir3: Leave bools as 1-bit, storing them in full regs.
If use NIR's 1-bit bool representation , we get exactly the bool behavior
the hardware provides: CMPS produces true or false, AND/OR/XOR work as
intended without extra absnegs, and we can pass those half values directly
to other CMPS. We emit an absneg for b2b1 ("turn a memory load into a
1-bit NIR boolean"), but we would have done so for the ir3_n2b() on the
use of that value anyway. The most awkward bit is that inot(a@1) is now a
sub(1, a), but we can encode the 1 as an immediate so it's fine.
No significant changes to GL_TIME_ELAPSED on my set of traces (n=21).
instructions in affected programs: 1570638 -> 1548702 (-1.40%)
nops in affected programs: 624053 -> 611381 (-2.03%)
non-nops in affected programs: 959061 -> 949797 (-0.97%)
mov in affected programs: 5258 -> 5252 (-0.11%)
cov in affected programs: 15099 -> 15902 (5.32%)
dwords in affected programs: 469600 -> 452768 (-3.58%)
last-baryf in affected programs: 162211 -> 154726 (-4.61%)
full in affected programs: 4881 -> 4797 (-1.72%)
sstall in affected programs: 173953 -> 174545 (0.34%)
(ss) in affected programs: 10922 -> 10934 (0.11%)
(sy) in affected programs: 728 -> 745 (2.34%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4518>
Eric Anholt [Sat, 11 Apr 2020 04:54:58 +0000 (21:54 -0700)]
freedreno/ir3: Drop redundant IR3_REG_HALF setup in ALU ops.
It's set by ir3_put_dst() immediately after.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4518>
Marek Olšák [Tue, 28 Apr 2020 16:51:22 +0000 (12:51 -0400)]
radeonsi: revert an accidental change in si_clear_buffer
The change was in:
7b0b085c94347cb9c94d88e11a64a6c341d95477
Fixes:
7b0b085c943 ("radeonsi: drop the negation from fmask_is_not_identity")
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4761>
Marek Olšák [Tue, 28 Apr 2020 15:19:23 +0000 (11:19 -0400)]
radeonsi: fix si_compute_clear_render_target with render condition enabled
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4761>
Marek Olšák [Sun, 26 Apr 2020 14:50:24 +0000 (10:50 -0400)]
radeonsi: add a workaround to fix KHR-GL45.texture_view.view_classes on gfx9
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4761>
Marek Olšák [Sun, 26 Apr 2020 12:38:54 +0000 (08:38 -0400)]
radeonsi: implement and use compute-based DCC decompression on gfx9-10
DCC_DECOMPRESS doesn't work. Instead of trying to figure out why,
use a compute blit where the load is compressed and the store is
uncompressed.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4761>
Marek Olšák [Sun, 26 Apr 2020 11:45:34 +0000 (07:45 -0400)]
radeonsi: add SI_IMAGE_ACCESS_DCC_OFF to ignore DCC for shader images
A shader-based DCC decompress pass will use this.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4761>
Marek Olšák [Mon, 27 Apr 2020 01:36:59 +0000 (21:36 -0400)]
radeonsi: bind shader images after DCC is disabled for image stores
This prevents an infinite recursion with a compute-based DCC decompression
when it restores shader images.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4761>
Marek Olšák [Sun, 26 Apr 2020 11:22:52 +0000 (07:22 -0400)]
radeonsi: clean up and deduplicate code around internal compute dispatches
In addition to the cleanup, there are these changes in behavior:
- clear_render_target waits for idle after the dispatch and then flushes
L0-L1 caches (this was missing)
- sL0 is no longer invalidated before the dispatch, because src resources
don't use it
- sL0 is no longer invalidated after the dispatch if dst is an image
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4761>
Marek Olšák [Sun, 26 Apr 2020 05:23:11 +0000 (01:23 -0400)]
radeonsi: unify and align down the max SSBO/TBO/UBO buffer binding size
Rounding down the size fixes:
KHR-GL45.enhanced_layouts.ssb_member_invalid_offset_alignment
Fixes:
03e2adc990d239119619f22599204c1b37b83134
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4761>
Marek Olšák [Sun, 26 Apr 2020 12:55:08 +0000 (08:55 -0400)]
tgsi_to_nir: handle TGSI_OPCODE_BARRIER
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4761>
Marek Olšák [Sun, 26 Apr 2020 12:37:42 +0000 (08:37 -0400)]
tgsi_to_nir: handle TGSI_SEMANTIC_BLOCK_SIZE
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4761>
Marek Olšák [Fri, 6 Mar 2020 21:56:54 +0000 (16:56 -0500)]
glthread: upload non-VBO vertices and indices for non-Indirect non-IBM draws
This is basically the same thing u_vbuf does.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Marek Olšák [Sat, 21 Mar 2020 06:58:51 +0000 (02:58 -0400)]
glthread: handle gl{Push,Pop}ClientAttrib{DefaultEXT} for glthread states
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Marek Olšák [Tue, 24 Mar 2020 03:35:58 +0000 (23:35 -0400)]
glthread: handle POS vs GENERIC0 aliasing
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Marek Olšák [Sat, 21 Mar 2020 06:24:28 +0000 (02:24 -0400)]
glthread: initialize VAOs properly
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Marek Olšák [Sat, 7 Mar 2020 00:00:03 +0000 (19:00 -0500)]
glthread: track primitive restart state
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Marek Olšák [Thu, 5 Mar 2020 00:24:34 +0000 (19:24 -0500)]
glthread: track instance divisor changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Marek Olšák [Fri, 28 Feb 2020 02:58:35 +0000 (21:58 -0500)]
glthread: track pointers and strides for Pointer & EXT_dsa attrib functions
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Marek Olšák [Sun, 22 Mar 2020 18:45:14 +0000 (14:45 -0400)]
glthread: don't use atomics for refcounting to decrease overhead on AMD Zen
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Marek Olšák [Fri, 6 Mar 2020 02:50:17 +0000 (21:50 -0500)]
glthread: do glBufferSubData as unsynchronized upload + GPU copy
1. glthread has a private upload buffer (as struct gl_buffer_object *)
2. the new function glInternalBufferSubDataCopyMESA is used to execute the copy
(the source buffer parameter type is struct gl_buffer_object * as GLintptr)
Now glthread can handle arbitrary glBufferSubData sizes without syncing.
This is a good exercise for uploading data outside of the driver thread.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Marek Olšák [Sat, 7 Mar 2020 01:37:57 +0000 (20:37 -0500)]
mesa: add _mesa_InternalBind{ElementBuffer,VertexBuffers} for glthread
Uploaded non-VBO user data will be set via these functions.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Marek Olšák [Sat, 7 Mar 2020 01:19:11 +0000 (20:19 -0500)]
mesa: add glInternalBufferSubDataCopyMESA for glthread
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Marek Olšák [Fri, 27 Mar 2020 11:57:07 +0000 (07:57 -0400)]
mesa: inline vbo_context inside gl_context to remove vbo_context dereferences
The number of lines in the disassembly of vbo_exec_api.c.o decreased
by 4.5%, which roughly corresponds to a decrease in instructions
for immediate mode thanks to the removal of ctx->vbo_context dereferences.
It increases performance in one Viewperf11 subtest by 2.8%.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Marek Olšák [Fri, 27 Mar 2020 09:07:02 +0000 (05:07 -0400)]
mesa,st/mesa: add a fast path for non-static VAOs
Skip most of _mesa_update_vao_derived_arrays if the VAO is not static.
Drivers need a separate codepath for this.
This increases performance by 7% with glthread and the game "torcs".
The reason is that glthread uploads vertices and sets vertex buffers
every draw call, so the overhead is very noticable. glthread doesn't
hide the overhead, because the driver thread is the busiest thread.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Marek Olšák [Sun, 22 Mar 2020 05:07:54 +0000 (01:07 -0400)]
mesa: don't update shaders on fixed-func state changes if user shaders are bound
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Marek Olšák [Sun, 22 Mar 2020 04:47:23 +0000 (00:47 -0400)]
mesa: don't set unnecessary program flags in _mesa_update_state
_NEW_PROGRAM is already set.
_NEW_FRAG_CLAMP is not used by the fixed-func fragment shader.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Mathias Fröhlich [Thu, 27 Feb 2020 07:13:07 +0000 (08:13 +0100)]
mesa: set _NEW_FRAG_CLAMP only when needed
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Marek Olšák [Sun, 22 Mar 2020 04:30:40 +0000 (00:30 -0400)]
mesa: don't call _mesa_update_state for _mesa_get_clamp_fragment_color
It's not needed.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Mathias Fröhlich [Mon, 12 Aug 2019 10:16:16 +0000 (12:16 +0200)]
st/mesa: Move _NEW_FRAG_CLAMP to NewFragClamp driver flag.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Marek Olšák [Sun, 22 Mar 2020 02:15:20 +0000 (22:15 -0400)]
mesa: optimize glPush/PopClientAttrib by removing malloc overhead
just declare all structures needed by the stack in gl_context.
This improves performance by 5.6% in the game "torcs". FPS: 101.01 -> 106.73
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4314>
Rob Clark [Thu, 30 Apr 2020 20:54:49 +0000 (13:54 -0700)]
freedreno/a6xx: don't set SP_FS_CTRL_REG0.VARYING for fragcoord
Similar change to
5785bcc8a0ff9c5072c647337bf73f696c63cbe6. It appears
on a6xx and in fact this could cause varying corruption before the FS
had a chance to consume the varyings from varying storage.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2838
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4838>
Lionel Landwerlin [Tue, 21 Apr 2020 09:25:44 +0000 (12:25 +0300)]
iris: don't assert on unfinished aux import in copy paths
After a resource is created the first command using it could be a copy
command.
In iris_state we finish the import on surface/view creation but we
don't do that for copies.
v2: Move finish call to gallium entrypoints (Ken)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2725
Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4657>
Rob Clark [Thu, 30 Apr 2020 17:12:28 +0000 (10:12 -0700)]
freedreno: sync registers with envytools
Pull in the `SP_xS_BRANCH_COND` regs to keep the mesa and envytools
copies from getting out of sync.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Rob Clark [Wed, 22 Apr 2020 22:41:12 +0000 (15:41 -0700)]
freedreno/a6xx: more OUT_REG()
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Rob Clark [Wed, 22 Apr 2020 22:26:02 +0000 (15:26 -0700)]
freedreno: scissor vs disabled scissor micro-opt
We don't need to deref and check rast state every time scissor changes,
only when rast state changes.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Rob Clark [Wed, 29 Apr 2020 17:09:28 +0000 (10:09 -0700)]
freedreno/a6xx: convert const emit to OUT_PKT()
This is another hot packet. This splits out each of the four cases
(geom vs frag, and indirect vs inline) intentionally, to avoid some
parity bit calc.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Rob Clark [Wed, 22 Apr 2020 18:51:42 +0000 (11:51 -0700)]
freedreno/ir3: inline const emit
Drop vfunc callbacks for per-gen packet emit, and instead have a header
that is #include'd once per gen.
We'll end up with multiple copies of some of this, but since we never
have multiple gen's of adreno on a single device, only one copy will be
paged in (and hopefully in the I-cache for hot-paths)
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Rob Clark [Wed, 22 Apr 2020 18:20:25 +0000 (11:20 -0700)]
freedreno/a6xx: split out const emit
In order to inline the const emit and drop the per-gen vfuncs to emit
the correct sort of packet, we should consolidate all of the entry-
points to const emit in one object file, otherwise we'll end up with
multiple copies per gen.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Rob Clark [Wed, 29 Apr 2020 17:01:23 +0000 (10:01 -0700)]
freedreno/a6xx: convert draw packet to OUT_PKT()
This is one of the hotter pkt7 packets, since it is guaranteed to happen
on every draw. Switch to OUT_PKT() for less driver overhead in the draw
path.
Slight bit of cheating for using CP_DRAW_INDX_OFFSET_0 for the first
dword in all cases. Possibly *gen_header.py* could be more clever
and use typedef's in the cases of bitsets like vgt_draw_initiator.
But this works out because it is always the first dword.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Rob Clark [Wed, 29 Apr 2020 16:58:38 +0000 (09:58 -0700)]
freedreno/a6xx: add OUT_PKT()
Similar to OUT_REG(), this has the benefits of:
1. No more messing up pkt size
2. Detects errors of mixing up the order of dwords in the packet
3. Optimizes to more efficient code
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Rob Clark [Tue, 21 Apr 2020 16:05:55 +0000 (09:05 -0700)]
freedreno/a6xx: skip unnecessary MRT blend state
To lower CP overhead.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Rob Clark [Thu, 16 Apr 2020 22:25:27 +0000 (15:25 -0700)]
freedreno/a6xx: combine sample mask into blend state
This gets rid of one lone register we used to emit directly in IB2
whenever blend state changes, at the expense of needing blend state
variants when sample-mask changes. I think typically sample-mask
should not change frequently, so this seems like a fair trade-off.
To further limit the # of variants, we ignore sample-mask bits that
are not relavant for the current # of samples.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Rob Clark [Thu, 16 Apr 2020 22:18:08 +0000 (15:18 -0700)]
freedreno/a6xx: move blend-color to stateobj
To reduce CP overhead for draws skipped in a bin.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Rob Clark [Thu, 16 Apr 2020 21:52:29 +0000 (14:52 -0700)]
freedreno/a6xx: limit LRZ state emit
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Rob Clark [Thu, 16 Apr 2020 21:33:50 +0000 (14:33 -0700)]
freedreno/a6xx: limit PROG_FB_RAST state emit
The dependency on RASTERIZER state is only when rasterizer_discard
changes.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Rob Clark [Thu, 16 Apr 2020 21:13:39 +0000 (14:13 -0700)]
freedreno/a6xx: move scissor state to stateobj
To reduce CP overhead for draws skipped in a given tile.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Rob Clark [Thu, 16 Apr 2020 19:55:35 +0000 (12:55 -0700)]
freedreno/a6xx: move const state to single stateobj
In practice, we end up updating all the shader stages at the same time.
So collapse this into a single group.
Reduces CP overhead.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Rob Clark [Thu, 16 Apr 2020 17:18:29 +0000 (10:18 -0700)]
freedreno/a6xx: avoid unnecessary clearing VS DP state
If there is no (potentially unflushed) VS driver-param state, we don't
need to emit a DISABLE on each frame. So avoid that to reduce CP
overhead.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Rob Clark [Tue, 21 Apr 2020 16:06:28 +0000 (09:06 -0700)]
freedreno/a6xx: small query cleanup
Don't open-code `fd6_event_write()`
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Rob Clark [Fri, 17 Apr 2020 19:34:52 +0000 (12:34 -0700)]
freedreno/drm: inline the things
The existing structure dates back to when this code was part of libdrm,
and we wanted some of this not to be exposed as ABI between libdrm and
mesa. Now that this is no longer a constraint, inline things.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Rob Clark [Fri, 17 Apr 2020 19:25:22 +0000 (12:25 -0700)]
freedreno/drm: drop atomic refcnts
Since we dropped the async flush_queue, we no longer need the refcnts to
be atomic.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4813>
Eric Anholt [Wed, 29 Apr 2020 23:55:16 +0000 (16:55 -0700)]
freedreno/ir3: Initialize the unused dwords of the immediates consts.
Avoids having spurious differences (and weird values to look at!) in
traces from uninitialized memory.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4824>
Jason Ekstrand [Wed, 29 Apr 2020 22:50:42 +0000 (17:50 -0500)]
Revert "anv/gen12: Temporarily disable VK_KHR_buffer_device_address (and EXT)"
This reverts commit
c61ad77cd260ce7666b257ce411e512e0ca12ec8. We now no
longer have a problem with these.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4819>
Jason Ekstrand [Wed, 29 Apr 2020 22:14:58 +0000 (17:14 -0500)]
intel/eu: Use non-coherent mode (BTI=253) for stateless A64 messages
We don't care about full IA coherency since we always have the
opportunity in GL or Vulkan to flush the data cache. Using IA-coherent
mode is likely just making A64 access slower than it needs to be.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4819>
Tomeu Vizoso [Mon, 27 Apr 2020 14:10:16 +0000 (16:10 +0200)]
pan/decode: Use correct printf modifier for long int
As reported by Coverity:
>>> CID 1462605: API usage errors (PRINTF_ARGS)
>>> Argument "p->zero5" to format specifier "%x" was expected to have type "unsigned int" but has type "unsigned long".
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4724>
Tomeu Vizoso [Mon, 27 Apr 2020 14:09:57 +0000 (16:09 +0200)]
pan/decode: Check for correct unknown field
As reported by Coverity:
>>> CID 1462606: Incorrect expression (COPY_PASTE_ERROR)
>>> "unk1" in "s->unk1" looks like a copy-paste error.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4724>
Tomeu Vizoso [Mon, 27 Apr 2020 14:09:02 +0000 (16:09 +0200)]
panfrost: Don't leak temporary descriptors array
As found by Coverity:
>>> CID 1462596: Resource leaks (RESOURCE_LEAK)
>>> Variable "descriptors" going out of scope leaks the storage it points to.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4724>
Tomeu Vizoso [Fri, 24 Apr 2020 06:40:51 +0000 (08:40 +0200)]
panfrost: Emit blend descriptors on Bifrost
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4724>
Alyssa Rosenzweig [Thu, 23 Apr 2020 23:25:44 +0000 (19:25 -0400)]
panfrost: Enumify bifrost blend types
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4724>
Andres Gomez [Mon, 20 Apr 2020 11:19:26 +0000 (14:19 +0300)]
gitlab-ci: update tracie README after changes in main script
v2:
- Update the default location for the traces when there is no
traces-db entry in the traces definition file (Alexandros).
Fixes:
90a39af5f65 "(ci: Drop the git dependency in tracie)"
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4640>
Andres Gomez [Fri, 24 Apr 2020 19:59:02 +0000 (22:59 +0300)]
.mailmap: add an alias for Andres Gomez
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4739>
Andres Gomez [Fri, 24 Apr 2020 19:56:10 +0000 (22:56 +0300)]
.mailmap: add an alias for Iago Toral Quiroga
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4739>
Lionel Landwerlin [Thu, 16 Apr 2020 18:48:32 +0000 (21:48 +0300)]
ci: Add intel to shaderdb runs
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4594>
Lionel Landwerlin [Wed, 15 Apr 2020 21:17:39 +0000 (00:17 +0300)]
intel: add stub_gpu tool
Run shaderdb like this :
intel_stub_gpu -p bxt ./run ./shaders/*
List of platform names is available from
gen_device_name_to_pci_device_id() (src/intel/dev/gen_device_info.c).
v2: Add missing getparam support
Raise max soft limit of file descriptors
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4594>
Lionel Landwerlin [Thu, 16 Apr 2020 18:45:23 +0000 (21:45 +0300)]
intel/dev: print out error when platform is not found by name
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4594>
Lionel Landwerlin [Sat, 25 Apr 2020 09:58:58 +0000 (12:58 +0300)]
drm-shim: silence warnings
Matt is seeing a bunch of warnings :
drm_shim.c:312:4: warning: ignoring return value of ‘asprintf’, declared with attribute warn_unused_result [-Wunused-result]
v2: Add nofail variants of *asprintf (Eric)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4594>
Lionel Landwerlin [Sat, 25 Apr 2020 09:47:04 +0000 (12:47 +0300)]
drm-shim: don't create a memfd per BO
Running shader-db on big servers with many cores, we're running out of
file descriptors.
Use a single 4Gb memfd instead and allocate from it using a VMA.
v2: Align VMA allocation to 4096 (Eric)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4594>
Lionel Landwerlin [Sat, 25 Apr 2020 09:23:39 +0000 (12:23 +0300)]
drm-shim: move handle lock to shim_fd
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4594>
Rob Clark [Thu, 30 Apr 2020 00:31:56 +0000 (17:31 -0700)]
gallium: extract out logicop helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4826>
Roland Scheidegger [Wed, 29 Apr 2020 04:38:12 +0000 (06:38 +0200)]
gallivm: fix half to float conversions with llvm 11
LLVM 11 removes the intrinsic for half to float conversion, so use the fpext
function instead. This function actually works now with half to float, albeit
a quick experiment showed at least the x86 backend cannot lower it itself if
the cpu doesn't support it natively and tries to call external library, which
crashes (and would be very slow anyway as it would be lowered to scalar code),
so for now only use it where we previously used the f16c intrinsic.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2603
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4800>
Eric Engestrom [Wed, 29 Apr 2020 18:11:20 +0000 (20:11 +0200)]
cut 20.1 branch
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4823>
Francisco Jerez [Tue, 28 Apr 2020 22:06:18 +0000 (15:06 -0700)]
intel/ir: Update performance analysis parameters for memory fence codegen changes.
The SFID field of the SHADER_OPCODE_MEMORY_FENCE and
SHADER_OPCODE_INTERLOCK instructions now indicates the target function
of the memory fence. Account the cycle-count cost to the right shared
unit.
Fixes:
f858fa26b4cca8834c8687f01d2ba431fcc8e006 ("intel/fs,vec4: Pull stall logic for memory fences up into the IR")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4817>
Dylan Baker [Wed, 29 Apr 2020 23:15:32 +0000 (16:15 -0700)]
docs: update calendar, add news item, and link releases notes for 20.0.6
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4822>
Dylan Baker [Wed, 29 Apr 2020 23:10:57 +0000 (16:10 -0700)]
docs: Add SHA256 sums for 20.0.6
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4822>
Dylan Baker [Wed, 29 Apr 2020 22:33:42 +0000 (15:33 -0700)]
docs: Add release notes for 20.0.6
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4822>
Alyssa Rosenzweig [Wed, 29 Apr 2020 22:01:50 +0000 (18:01 -0400)]
pan/mdg: Be a bit more pedantic in invert passes
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4820>
Alyssa Rosenzweig [Wed, 29 Apr 2020 20:29:01 +0000 (16:29 -0400)]
pan/mdg: Track more types
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4820>
Rob Clark [Wed, 29 Apr 2020 22:23:26 +0000 (15:23 -0700)]
freedreno: fix buffer import
`rsc->layout.cpp` is zero until we `fd_resource_layout_init()`
Fixes:
5a8718f01b3 ("freedreno: Make the slice pitch be bytes, not pixels.")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4818>
Marcin Ślusarz [Wed, 29 Apr 2020 14:52:40 +0000 (16:52 +0200)]
i965: remove unused variable
Last use was removed in
54525808aa58.
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4809>
Bas Nieuwenhuizen [Wed, 29 Apr 2020 20:35:54 +0000 (22:35 +0200)]
radv: Fix implicit sync with recent allocation changes.
the implicit sync flag gets set at the beginning at the function,
but I used = instead of |= later.
Fixes:
bec92850270 "radv: Stop using memory type indices."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4814>
Rob Clark [Tue, 28 Apr 2020 20:07:16 +0000 (13:07 -0700)]
freedreno: switch to simple_mtx
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4810>
Rob Clark [Tue, 28 Apr 2020 20:04:16 +0000 (13:04 -0700)]
freedreno: add screen lock wrappers
This will make it easier to swap out to simple_mtx_t
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4810>
Rob Clark [Tue, 28 Apr 2020 19:39:32 +0000 (12:39 -0700)]
util/simple_mtx: add assert_locked()
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4810>
Jonathan Marek [Tue, 28 Apr 2020 23:54:06 +0000 (19:54 -0400)]
turnip: fix wrong substream size in parse_multisample_and_color_blend
Missed updating this when adding tu6_emit_sample_locations
Fixes:
a92d2e11095 ("turnip: implement VK_EXT_sample_locations")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4795>
Eric Anholt [Mon, 13 Apr 2020 18:14:23 +0000 (11:14 -0700)]
util/ra: Improve ra_set_finalize() performance.
BITSET_FOR_EACH_SET can walk a sparse set (such as a register class's set
of registers) much faster than just iterating over individual bits.
Improves freedreno startup time (as measured by shader-db ./run
shaders/closed/gputest/triangle on my x86 system) by -4.12679% +/-
1.99006% (n=151)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4537>
Eric Anholt [Mon, 13 Apr 2020 17:47:17 +0000 (10:47 -0700)]
util/ra: Use util_dynarray for handling the conflict lists.
Again, shortens the code significantly.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4537>
Eric Anholt [Mon, 13 Apr 2020 17:36:08 +0000 (10:36 -0700)]
util/ra: Use util_dynarray for the adjacency list.
This make the code significantly more readable, I think (along with
shorter). Also, using util_dynarray_delete_unordered() saves us a move of
the rest of the list when removing adjacency on a node.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4537>
Eric Anholt [Thu, 9 Apr 2020 22:10:08 +0000 (15:10 -0700)]
util/ra: Sanity check that we're adding a valid reg to a class.
BITSET_SET might not segfault on you right away if you're just slightly
off, and an assert is nicer anyway.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4537>
Eric Anholt [Thu, 9 Apr 2020 21:11:51 +0000 (14:11 -0700)]
util/ra: Sanity check that the driver selected a valid reg.
freedreno was returning -1 when it didn't pick a reg from the given bitset
due to an off-by-a-small-number error.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4537>
Konrad Dybcio [Thu, 26 Mar 2020 16:48:52 +0000 (17:48 +0100)]
freedreno/a4xx: enable A405
This patch brings support for Adreno A405
as found on MSM8939. That chip is a cut-down
version of A4XX IP and requires no special handling.
Tested on Asus Zenfone 2 Laser (Z00T) smartphone.
Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4753>
Mike Blumenkrantz [Tue, 24 Mar 2020 15:58:29 +0000 (11:58 -0400)]
iris: handle PIPE_CAP_CLEAR_SCISSORED
this allows passing scissored clear calls through the driver where it can
be handled by a repclear shader
fix kwg/mesa#61
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4310>
Mike Blumenkrantz [Tue, 24 Mar 2020 16:02:51 +0000 (12:02 -0400)]
gallium: add pipe cap for scissored clears and pass scissor state to clear() hook
this adds a new pipe cap that drivers can support which enables passing buffer
clears with scissor test enabled through to be handled by the driver instead
of having mesa draw a quad
also adjust all existing clear() hooks to have the new parameter
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4310>
Caio Marcelo de Oliveira Filho [Wed, 29 Apr 2020 04:05:05 +0000 (21:05 -0700)]
i965: Use correct constant for max_variable_local_size
Fixes:
5664bd6db38 ("i965: Implement ARB_compute_variable_group_size")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4799>
Mike Blumenkrantz [Mon, 30 Mar 2020 14:37:29 +0000 (10:37 -0400)]
iris: move iris_vtable to iris_screen
instead of inlining this into every context, now a struct is used in the screen
struct to reduce memory usage and simplify a couple of the methods
Closes: https://gitlab.freedesktop.org/kwg/mesa/-/issues/6
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4376>
Jason Ekstrand [Mon, 27 Apr 2020 20:31:12 +0000 (15:31 -0500)]
intel/fs: Don't delete coalesced MOVs if they have a cmod
Shader-db results on ICL:
total instructions in shared programs:
17133088 ->
17133287 (<.01%)
instructions in affected programs: 61300 -> 61499 (0.32%)
helped: 0
HURT: 199
This means it's likely fixing 199 bugs. :-) All the changed shaders are
in Mad Max. It's surprisingly difficult to get the back-end compiler to
generate a pattern that hits this we don't tend to emit a lot coalescable
MOVs. The pattern in Mad Max that's able to hit is fsign(fsat(x)) under
the right conditions.
Closes: #2820
Cc: mesa-stable@lists.freedesktop.org
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4773>
Marek Olšák [Mon, 27 Apr 2020 03:17:41 +0000 (23:17 -0400)]
st/mesa: expose more SPIR-V capabilities
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4760>
Marek Olšák [Mon, 27 Apr 2020 05:03:38 +0000 (01:03 -0400)]
mesa: report GL_INVALID_OPERATION for invalid glTextureBuffer target
This fixes:
KHR-GL46.direct_state_access.textures_buffer_errors
KHR-GL46.direct_state_access.textures_buffer_range_errors
Fixes:
98e64e538af - main: Added entry point for glTextureBuffer
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4759>
Alyssa Rosenzweig [Tue, 28 Apr 2020 21:44:39 +0000 (17:44 -0400)]
pan/mdg: Replicate 16-bit swizzles
We don't support vec8 quite yet anyway, this fixes dot products.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>
Alyssa Rosenzweig [Tue, 28 Apr 2020 21:44:19 +0000 (17:44 -0400)]
pan/mdg: Ensure fdot is scalar out in disasm
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4793>