pan/bi: Assume SSA in mod prop

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Assume SSA in copyprop

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Don't use bi_temp_reg

We've already broken SSA irreparably at this point. We can just change what
"normal" means and avoid the disjointed indexing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Clear reg in squeeze_index

SSA is broken at this point. Let's not pretend otherwise. The numbering produced
by squeeze_index already disambiguates what-used-to-be SSA variables and
registers. A few shader-db changes because this shuffles the register allocation
around because LCRA is stupid.

total instructions in shared programs: 2658849 -> 2650196 (-0.33%)
instructions in affected programs: 463733 -> 455080 (-1.87%)
helped: 1089
HURT: 135
helped stats (abs) min: 1.0 max: 43.0 x̄: 8.20 x̃: 5
helped stats (rel) min: 0.11% max: 17.05% x̄: 2.28% x̃: 1.52%
HURT stats (abs)   min: 1.0 max: 7.0 x̄: 2.07 x̃: 2
HURT stats (rel)   min: 0.10% max: 2.97% x̄: 1.03% x̃: 0.83%
95% mean confidence interval for instructions value: -7.52 -6.62
95% mean confidence interval for instructions %-change: -2.04% -1.78%
Instructions are helped.

total cycles in shared programs: 140617.52 -> 140613.14 (<.01%)
cycles in affected programs: 227.45 -> 223.08 (-1.92%)
helped: 45
HURT: 1
helped stats (abs) min: 0.015625 max: 0.4375 x̄: 0.10 x̃: 0
helped stats (rel) min: 0.43% max: 17.72% x̄: 2.79% x̃: 1.29%
HURT stats (abs)   min: 0.015625 max: 0.015625 x̄: 0.02 x̃: 0
HURT stats (rel)   min: 1.47% max: 1.47% x̄: 1.47% x̃: 1.47%
95% mean confidence interval for cycles value: -0.12 -0.07
95% mean confidence interval for cycles %-change: -3.76% -1.64%
Cycles are helped.

total cvt in shared programs: 13877.61 -> 13742.41 (-0.97%)
cvt in affected programs: 3432 -> 3296.80 (-3.94%)
helped: 1089
HURT: 135
helped stats (abs) min: 0.015625 max: 0.671875 x̄: 0.13 x̃: 0
helped stats (rel) min: 0.18% max: 28.36% x̄: 5.05% x̃: 3.38%
HURT stats (abs)   min: 0.015625 max: 0.109375 x̄: 0.03 x̃: 0
HURT stats (rel)   min: 0.15% max: 8.33% x̄: 2.87% x̃: 2.27%
95% mean confidence interval for cvt value: -0.12 -0.10
95% mean confidence interval for cvt %-change: -4.46% -3.88%
Cvt are helped.

total quadwords in shared programs: 1442328 -> 1437776 (-0.32%)
quadwords in affected programs: 106240 -> 101688 (-4.28%)
helped: 478
HURT: 17
helped stats (abs) min: 8.0 max: 24.0 x̄: 9.81 x̃: 8
helped stats (rel) min: 1.54% max: 20.00% x̄: 5.27% x̃: 3.70%
HURT stats (abs)   min: 8.0 max: 8.0 x̄: 8.00 x̃: 8
HURT stats (rel)   min: 1.61% max: 14.29% x̄: 6.42% x̃: 6.25%
95% mean confidence interval for quadwords value: -9.61 -8.78
95% mean confidence interval for quadwords %-change: -5.20% -4.54%
Quadwords are helped.

total threads in shared programs: 53557 -> 53550 (-0.01%)
threads in affected programs: 14 -> 7 (-50.00%)
helped: 0
HURT: 7
HURT stats (abs)   min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: -1.00 -1.00
95% mean confidence interval for threads %-change: -50.00% -50.00%
Threads are HURT.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Clean up after converting to SSA

nir_invalidate_divergence was introduced in aa765c54bdd ("pan/bi: Add divergent
intrinsic lowering pass"), which needed divergence information for a late NIR
pass but not otherwise in the backend. Unfortunately, nir_convert_from_ssa is
less aggressive about coalescing when divergence information makes it look like
the coalescing would make the code worse -- even though that's not actually an
issue on Mali.

Now that we don't use nir_convert_from_ssa, we don't need the hack.

Likewise for the vec.reg hack, which was introduced because the split/collect
cache relies on SSA form.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Preserve SSA form from NIR

Don't call nir_convert_from_ssa, preserve the SSA from NIR. This gets us real
SSA for all frontend passes. The RA becomes a black box that takes SSA in and
outputs register allocated code out. The "broken" SSA form never escapes RA,
which means we can clean up special cases in the rest of the compiler. It also
gets us ready for exploiting SSA form in the RA itself.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Reduce some moves when going out-of-SSA

This is still pretty brainless.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Add brainless out-of-SSA pass

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Add SSA-based liveness pass

Adapted from NIR's liveness analysis. This is different from our non-SSA
liveness pass for a few reasons:

1. It must handle phi nodes. This implies significant changes to the worklist
   algorithm.
2. It only handles SSA. It doesn't need funny labelling schemes for
   handling nir_registers in parallel with SSA defs.
3. It is scalar-only. The vector liveness information isn't interesting when
   vectors are handled via COLLECT and SPLIT. This means it uses a bitset (uses
   8x less memory to store livenss information, should be easier on the caches
   too).

Eventually, this will become our only pre-RA liveness pass. For now, both passes
are maintained in parallel: the SSA pass used before out-of-SSA, the non-SSA
pass used after out-of-SSA and before RA, and the post-RA pass used after RA.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Translate phis from NIR

Code lifted from AGX, which in turn is based on ir3 and aco.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Inline DCE into bi_lower_vector

This needs on after going out-of-SSA, which is a separate DCE algorithm. Split
out.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Validate before&after pre-RA sched

Pre-RA scheduling can move instructions around in nontrivial ways, yet it must
maintain the IR's ordering invariants (for preloads, phis, etc.) Running
validation before and after makes scheduler bugs more obvious.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Don't reorder phis in pre-RA scheduling

Treat them like preloads which are also required to be at the start of the
block.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Don't optimize if without else

We need to emit a jump over the else body when constructing the IR, even if the
else body appears empty in NIR, because instructions could be added when
going out-of-SSA. This optimization should instead happen post-RA, but doing so
is nontrivial and the cycle count regression is minimal, so punting on this for
now.

total instructions in shared programs: 2728364 -> 2731495 (0.11%)
instructions in affected programs: 580462 -> 583593 (0.54%)
helped: 0
HURT: 1272
HURT stats (abs)   min: 1.0 max: 17.0 x̄: 2.46 x̃: 2
HURT stats (rel)   min: 0.09% max: 22.22% x̄: 0.88% x̃: 0.59%
95% mean confidence interval for instructions value: 2.37 2.56
95% mean confidence interval for instructions %-change: 0.80% 0.97%
Instructions are HURT.

total cycles in shared programs: 140628.52 -> 140631.50 (<.01%)
cycles in affected programs: 474.45 -> 477.44 (0.63%)
helped: 0
HURT: 116
HURT stats (abs)   min: 0.015625 max: 0.0625 x̄: 0.03 x̃: 0
HURT stats (rel)   min: 0.21% max: 9.09% x̄: 1.16% x̃: 0.39%
95% mean confidence interval for cycles value: 0.02 0.03
95% mean confidence interval for cycles %-change: 0.88% 1.43%
Cycles are HURT.

total cvt in shared programs: 14816.20 -> 14865.12 (0.33%)
cvt in affected programs: 4954.31 -> 5003.23 (0.99%)
helped: 0
HURT: 1272
HURT stats (abs)   min: 0.015625 max: 0.265625 x̄: 0.04 x̃: 0
HURT stats (rel)   min: 0.16% max: 28.57% x̄: 1.88% x̃: 1.17%
95% mean confidence interval for cvt value: 0.04 0.04
95% mean confidence interval for cvt %-change: 1.74% 2.02%
Cvt are HURT.

total quadwords in shared programs: 1476536 -> 1478512 (0.13%)
quadwords in affected programs: 54496 -> 56472 (3.63%)
helped: 0
HURT: 247
HURT stats (abs)   min: 8.0 max: 8.0 x̄: 8.00 x̃: 8
HURT stats (rel)   min: 0.93% max: 20.00% x̄: 5.78% x̃: 4.17%
95% mean confidence interval for quadwords value: 8.00 8.00
95% mean confidence interval for quadwords %-change: 5.21% 6.34%
Quadwords are HURT.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Remove bogus assert lowering branches

We can get BRANCHZ.i16 since we lower JUMP early. This seems to have worked
before mainly by chance. With the change to how we optimize, we can get code
sequences like:

   block2 {
      BRANCHZ.i16.eq u256, u256 -> block5
      BRANCHZ.i16.eq u256, u256 -> block4
   } -> block5  from block1

which would choke the assert.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Don't lower FAU for phis

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Validate phi ordering

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Add phi nodes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Lift bi_predecessor_index helper

From AGX for handling phi node.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Add bi_after_block_logical helper

Useful for lowering phis.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Don't write registers in optimizer tests

The new SSA-based dead code elimination won't know how to deal with code of that
funny form. In actuality it doesn't have to, so we just make sure the optimizer
tests produce valid IR so this works as expected.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Dynamically allocate source/dests

Instead store a pointer to the storage. Ideally even these pointer would be
removed but that's quite cumbersome in C...

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Reduce memory of scheduler access array

Now that we have accurate source/dest counts, we don't need to worst case. Which
is good, because the worst case will become infinite once we allow phis.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Use builder for atomic lowering in scheduler

The last places where sources are appended. Fix them and we can move on.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Use builder for IADD -> IADDC opt

As before.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Use builder for MUX -> CSEL opt

This is yet another case where we add a source, which will require reallocation.
It's easy enough to rebuild the instruction here.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/va: Use builder in va_lower_isel

..where necessary to avoid appending sources. This removes a bunch more cases
where we would need to reallocate sources. The lifetime management is simpler if
we just reallocate the whole instruction. In theory this is a slight overhead
but it's probably worth it to avoid the complexity otherwise.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Rebuild DISCARD when optimizing

This avoids incrementing I->nr_srcs which will soon be invalid.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Rebuild some instructions when lowering

When we add a source, we need to build a new instruction (or at the very least
reallocate sources). This is less of a hack anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Use safe helpers to remove srcs/dests

Changing I->nr_srcs or I->nr_dests directly is generally unsafe, but the special
case of removing sources/destinations at the end is safe. Add and use helpers to
wrap this operation simplifying the remaining code audit before we can
dynamically allocate sources/destinations.

At this point in the series, nothing modifies I->nr_dests after allocation
except these helpers, so destinations should be safe to make dynamic. There's a
bit more work needed for sources.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Use variable src/dest for collect/split

This avoids the nr_srcs/nr_dests setting dance, and will allow the builder to
handle the required memory allocation when we switch to dynamic src/dest
allocation.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Add variable dest/src support to builder

This will allow pseudo instructions to be allocated in a cleaner way when we
dynamically allocate their sources/destinationa.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Don't read nonexistant sources

Codebase audit. In preparation to dynamically allocate sources.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Don't read nonexistant destinations

Codebase audit. In preparation to dynamically allocate destinations.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Assume destinations are non-NULL

We guarantee this now, no need to check it in every pass. There's an exception
on Bifrost after clause scheduling, but few passes run after clause scheduling
so this doesn't affect much.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Assert destinations are non-NULL

All uses of null destinations have been replaced with more appropriate
constructs. We can now assume this throughout.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Introduce TEXC_DUAL psuedoinstruction

There are two "shapes" of TEXC in the IR:

* Regular texturing. This TEXC writes a single set of staging registers.
* Dual texturing. This TEXC writes two sets of staging registers.

Currently we model both with a 2-destination TEXC, with a null second
destination for the usual case where dual texturing isn't used. This is awkward.
To make the "shapes" of instructions more predictable, make TEXC only write a
single set of staging registers (like the hardware instruction) and split off a
TEXC_DUAL pseudoinstruction for the second case, lowered late.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Use bi_emit_split_i32 for trimming vecs

This ensures the shape of the split is correct (no nulls in the destination).
This should not affect the register allocation, though it does "cost" extra
variable names.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Don't remove dests in DCE

Removing dests without removing instructions only makes sense for certain
pseudo-instructions, but it makes the IR needlessly complicated for all
instructions. There's no real reason to do so, we can signal this in a different
way instead.

No shader-db changes.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Register allocate BLEND dest on Valhall

On Bifrost, BLEND writes to the link register, acting like a function call. On
Valhall, BLEND does not write anything. But the BLEND instruction in our IR is a
pseudo-instruction with Bifrost semantics, expanding to a multi-instruction
sequence on Valhall. So it's not worth special casing Valhall in instruction
selection.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Improve register printing

Use "r0" style to denote machine registers, consistent with the assembly. Use
instead "nr0" for NIR registers so they don't collide. This reduces noise for
the average case (either register allocated or almost SSA).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Clean up destination printing

Now we can trust in I->nr_dests, avoiding a bunch of special cases and incorrect
printing for instructions without a destination. To compensate for those
instructions being hard to scan now, indent.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Remove trivial dest[0] = bi_null()

It's already NULL and will interfere with the more comprehensive src/dest
overwork we're doing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Add validation for nr_srcs/nr_dests

Now that we set nr_srcs/nr_dests accurately, assert as much in the validator.
This pass will be deleted later in the series, but having it here is expected to
be useful for bisection, in case there are cases missed. Certainly running the
CTS at this point in the series is helpful to prove completeness of the
beginning of this series.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Use nr_{srcs,dests} in bi_foreach_{src,dest}

This avoids crawling sources that must be null.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Consider nr_srcs/dests in CSE

Now that these are meaningful for COLLECT and SPLIT.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Model 3rd source for ATEST

ATEST on Valhall takes atest-param as an explicit encoded source. The source
also exists on Bifrost, but it's implied in the encoding. Rather than treating
it as a "ghost" source, model it in the IR explicitly so the count is correct.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Set I->nr_dests, I->nr_srcs

The builder is the primary producer of instructions, and generally the shape of
an instruction is fixed at build-time. It must set nr_dests/nr_srcs
appropriately. Likewise, when we modify sources later, we need to update
nr_srcs/nr_dests to keep everything consistent (and keep the tests passing).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/va: Split out compare instructions

The different combine modes form different instructions from each other and in
particular from the two-source version on Bifrost. Model them as such so we can
represent the relevant Valhall-specific lowering/optimizations accurately in the
compiler.

This requires updating the unit tests to use the new names since there's not
much point keeping around the aliases.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Model [IF]CMP_{OR,AND,MULTI} ops

Valhall-style comparisons are 3-source, allowing multiple comparisons to be
combined without bitwise arithmetic. For example, the sequence

   FCMP.f32.eq t, z, w
   FCMP_AND.f32.eq dest, x, y, t

calculates (z == w) && (y == t) in 2 instructions (would be 3 on Bifrost).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Consider all dests in helper_block_update

If an instruction has multiple destinations and *any* of them are needed by
helper invocations, we should keep helper invocations alive. This is a bug fix.
Consider the GLSL:

   first = texture(sampler, ...);
   float res = texture(sampler, vec2(first.y)).x + first.x;

Corresponding to the IR:

   first = ...
   x, y, z, w = SPLIT first
   second = TEX y, y
   x', y', z', w' = SPLIT second
   FADD res, x, x'

Here, x is not required by helper invocations (the coordinates to TEX) while y
is required. If we only look at only the first destinations, we incorrectly
decide that first is not required and fail to set the .skip bit, leading to
incorrect results.

Fixes: 5febeae58e0 ("pan/bi: Emit collect and split")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Fix out-of-bounds write in va_lower_split_64bit

...with dual source blending. Fixes shaders/dolphin/smg.1.shader_test

There are more IR sources than Valhall machine sources here.

Fixes: b48933d6411 ("pan/va: Include BLEND for va_swap_12")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

gallium/hud: Fixes compile error in hud/hud_context.c:

../../src/gallium/auxiliary/hud/hud_context.c:1017:1: error: static declaration of 'access' follows non-static declaration
These error will shown when any header #include <io.h>

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18333>

r600: fix warnings for missing-braces on clang

[2624/3754] Compiling C++ object src/gallium/drivers/r600/sfn/tests/libr600_test.a.p/sfn_test_shaders.cpp.o
../src/gallium/drivers/r600/sfn/tests/sfn_test_shaders.cpp:3066:27: warning: suggest braces around initialization of subobject [-Wmissing-braces]
   r600_shader_key key = {0};
                          ^
                          {}
1 warning generated.
[2711/3754] Compiling C++ object src/gallium/drivers/r600/libr600.a.p/sfn_sfn_nir_lower_64bit.cpp.o
../src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp:910:33: warning: suggest braces around initialization of subobject [-Wmissing-braces]
      nir_const_value val[4] = {0};
                                ^
                                {}
../src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp:1328:38: warning: suggest braces around initialization of subobject [-Wmissing-braces]
      nir_ssa_scalar channels[4] = { 0 };
                                     ^
                                     {}

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18307>

d3d12: fix warnings for missing-braces on clang

[3485/3754] Compiling C++ object src/gallium/drivers/d3d12/libd3d12.a.p/d3d12_screen.cpp.o
../src/gallium/drivers/d3d12/d3d12_screen.cpp:56:65: warning: suggest braces around initialization of subobject [-Wmissing-braces]
static GUID OpenGLOn12CreatorID = { 0x6bb3cd34, 0x0d19, 0x45ab, 0x97, 0xed, 0xd7, 0x20, 0xba, 0x3d, 0xfc, 0x80 };
                                                                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                                                                {                                             }

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18307>

llvmpipe: don't assume pipe_context is always available in flush_frontbuffer

Fixes: 91dcadf9569 ("llvmpipe: finish rendering before flushing frontbuffer resources.")

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18392>

pan/bi: Fix dual texturing with uniforms

The GLSL code sequence:

   texture2D(tex0, u_coords) + texture2D(tex1, u_coords)

will be optimized to

   TEXC_DUAL tex0/tex1, u_coords, #texture_descriptor

If this optimization happens after lowering FAU, the resulting TEXC instruction
is unschedulable: both the uniform and the constant descriptor fight for the
same FAU slot.

However, if this optimization happens before lowering FAU, then the FAU lowering
will move the descriptor into a register, complicating the dual texturing fixup
in RA.

To fix this interaction, fuse dual texturing before lowering FAU and keep
texture descriptors as constants when lowering FAU of TEXC.

Fixes scheduling failure in piglit drawoverhead -test 3 with uniform reordering.

Fixes: a4d3a296477 ("pan/bi: Enable dual texture fusing pass")
Fixes: 6b2eda6b729 ("pan/bi: Reorder pushed uniforms to avoid moves")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18378>

mesa/st: do not blit when using compressed fallback

If we're using the blit-path, we don't update the compressed image, which
will be needed if an application try to download the texture-image again
afterwards.

I previously fixed this for the memcpy-codepath, but we actually need to
fall back for the blit code-path as well. So let's move this early-out
earlier to catch both.

Fixes: 8f446322e1b ("mesa/st: do not use memcpy when using compressed fallback")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18342>

anv/hasvk: tweak loading failure messages

We don't want to print out too many :

  MESA: error: ../src/intel/vulkan/anv_device.c:769: anv does not support Intel(R) HD Graphics (HSW GT1); use hasvk (VK_ERROR_INCOMPATIBLE_DRIVER)

whenever anv is not able to load on a HSW device. Similarly hasvk
should not print error on anything gfx9+.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Remove anv_batch_emit_reloc and just open-code it

We don't need the relocation offsets anymore, and just want to pin the
BO, and combine the address into a uint64_t.  We can just open code
those two things; it's actually less code.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Inline write_reloc into the only remaining caller

This is writing an address and clflushing, but it's not really about
execbuf relocations.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Drop offset from anv_reloc_list_append

No longer used.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Make a helper function for pinning a state pool's BOs

A bit less duplicated code, though with all the success checking, it
doesn't actually save us a whole lot.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete has_bindless_images and has_bindless_samples flags

These are always true now.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete has_a64_buffer_access flag

It's always true.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete relocation support from batch submission

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete wrapper BOs for relocations

These were only used in the non-softpin case.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete anv_reloc_list_add()

We don't need the offset to write a relocation at any longer, so all
it does is call anv_reloc_list_add_bo() at this point.  Just use that.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete softpin checks

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete use_relocations flag

There are no relocations.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Drop state pool relocation munging

Now that the state pool's center is always 0, this is not needed.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete "back" allocation from anv_block_pool

This was only used with relocations.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete relocation support from anv_block_pool

We no longer use relocations.

v2: silence fedora builder warning

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete "back" allocation from state pool

This was only used with relocations, which no longer happen.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv/tests: Don't use relocations in a test case

We won't support relocations shortly.

v2: Deal with softpin padding requirement (Lionel)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv/tests: remove back allocation tests

We'll remove driver code for this in the following commits.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete shader constants UBO from descriptor sets

We now always softpin and use the load_global_constant case, so there's
no need to set up a UBO for NIR constants.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete batch buffer growing code.

This was only needed on Haswell and older due to the kernel command
parser not allowing us to chain batches.  anv no longer support this.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete image param support.

This was only used prior to Skylake, which anv no longer supports.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Drop checks for version 8 or 9

anv no longer supports versions below this.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Fail to create a device on ver < 9

These are now only supported by hasvk.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: remove unused gfx7 code

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: remove support for gfx7/8

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: silence fedora build warning

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

hasvk: remove mesh code

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

hasvk: remove ray tracing code

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

hasvk: remove acceleration structure code

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

hasvk: stop advertising Vk 1.3 on non-softpin

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

hasvk: remove entrypoints for gfx9+

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

intel: add a hasvk vulkan driver

This new driver is a copy of the current Anv code, it will only load
on gfx7/8 platforms though.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

pvr: remove image pointer from image view struct

A pointer is also stored in the base vk_image_view struct, so we can use this
one instead.

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18373>

intel/pci_ids: Add dg2 0x5698 pci-id

This motherboard-down pci-id was added in kernel commit 8618b8489ba6
("drm/i915: DG2 and ATS-M device ID updates").

Ref: bspec 44477
Ref: https://patchwork.freedesktop.org/patch/msgid/20220701152231.529511-2-matthew.d.roper@intel.com
Fixes: ad565f6b70d ("intel/dev: Enable first set of DG2 PCI IDs")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18385>

radeonsi/ci: trigger radeonsi-raven-skqp for any RADV changes

Otherwise SKQP VK won't be run.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7120
Co-authored-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18316>

intel/pci_ids: Update DG2 device names

Ref: bspec 44477
Ref: https://www.intel.com/content/www/us/en/products/details/discrete-gpus/arc/arc-a-series.html
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18303>

intel/pci_ids: Update ATS-M device names

Ref: bspec 44477
Ref: https://www.intel.com/content/www/us/en/products/details/discrete-gpus/data-center-gpu/flex-series/products.html
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18303>

meson: Only draw with llvm depends on native directly
Tests, softpipe or AMD drivers don't depend on it directly

Fixes: 3955dd07 ("meson/gallium: Add an option to not use LLVM for gallium draw module")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6817

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17675>

ci/fedora: Re-enable vulkan-layers=device-select,overlay

Fixes: ace13203f30 ("ci: remove broken device-select-layer from build")

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18044>

ci: Add debian-clang-release build pipeline

As the default build type is debug according to
.gitlab-ci/meson/build.sh, the specified line is:
-D buildtype=${BUILDTYPE:-debug}

So we use release for building optimized version for testing
if the compiler optimization are fine.

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18044>

ci: Enable all possible meson build options for clang

By doing this to makes more code be compiled with clang and guarded by bot

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18044>

ci: Enable GALLIUM_DUMP_CPU=true only in the clang job

This is used to show the cpu caps when running unit tests.
As clang have optimization bug about util_get_cpu_caps before, so
we monitor it by using GALLIUM_DUMP_CPU=true

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18044>