Gert Wollny [Thu, 10 Aug 2023 12:42:10 +0000 (14:42 +0200)]
r600/sfn: drop unused ControlFlowInstr type enum
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24638>
Gert Wollny [Mon, 7 Aug 2023 13:10:26 +0000 (15:10 +0200)]
r600/sfn: Make use of four clause local registers
The hardware is actually configures like this, but for fma64
we have to sacrifice a "normal" register to allocate z and w
channels, even though the result written there is not used.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24638>
Lionel Landwerlin [Tue, 8 Aug 2023 06:13:16 +0000 (09:13 +0300)]
intel/fs: limit register flag interaction of FIND_*LIVE_CHANNEL
Those instructions do not access the flag registers on Gfx8+. Removing
the interaction enables CSE to remove more of those instructions.
Results are a bit mixed (DG2 vulkan fossils):
ACO:
Totals from 127 (5.97% of 2128) affected shaders:
Instrs: 139966 -> 138972 (-0.71%); split: -0.85%, +0.14%
Cycles: 1685747 -> 1667480 (-1.08%); split: -2.35%, +1.26%
Max live registers: 10582 -> 10544 (-0.36%)
Max dispatch width: 1048 -> 1040 (-0.76%)
Cyberpunk 2077:
Totals from 2879 (27.95% of 10301) affected shaders:
Instrs: 4264789 -> 4225666 (-0.92%); split: -1.01%, +0.09%
Cycles:
72380209 ->
71619521 (-1.05%); split: -1.63%, +0.58%
Subgroup size: 30624 -> 30632 (+0.03%)
Spill count: 98 -> 101 (+3.06%)
Fill count: 90 -> 93 (+3.33%)
Scratch Memory Size: 8192 -> 9216 (+12.50%)
Max live registers: 217807 -> 217098 (-0.33%); split: -0.59%, +0.26%
Max dispatch width: 23792 -> 24112 (+1.34%)
Gaining 40 SIMD16 shaders
Rise Of The Tomb Raider:
Totals from 622 (5.06% of 12289) affected shaders:
Instrs: 437380 -> 434760 (-0.60%); split: -0.72%, +0.12%
Cycles:
261843085 ->
261580703 (-0.10%); split: -0.73%, +0.63%
Max live registers: 27731 -> 27766 (+0.13%); split: -1.01%, +1.14%
Max dispatch width: 5832 -> 5432 (-6.86%); split: +0.27%, -7.13%
Loosing 26 SIMD32 shaders
Strange Brigade:
Totals from 1298 (31.48% of 4123) affected shaders:
Instrs: 1504408 -> 1487968 (-1.09%); split: -1.17%, +0.08%
Cycles:
20735976 ->
20443216 (-1.41%); split: -1.60%, +0.19%
Max live registers: 89911 -> 89957 (+0.05%)
DG2 shader-db run:
total instructions in shared programs:
23130895 ->
23130036 (<.01%)
instructions in affected programs: 260956 -> 260097 (-0.33%)
helped: 234
HURT: 101
helped stats (abs) min: 1 max: 54 x̄: 6.36 x̃: 4
helped stats (rel) min: 0.05% max: 8.16% x̄: 2.01% x̃: 1.90%
HURT stats (abs) min: 1 max: 37 x̄: 6.23 x̃: 3
HURT stats (rel) min: 0.02% max: 5.67% x̄: 0.89% x̃: 0.55%
95% mean confidence interval for instructions value: -3.62 -1.51
95% mean confidence interval for instructions %-change: -1.33% -0.94%
Instructions are helped.
total loops in shared programs: 6071 -> 6071 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0
total cycles in shared programs:
898610645 ->
898557166 (<.01%)
cycles in affected programs:
18308201 ->
18254722 (-0.29%)
helped: 315
HURT: 48
helped stats (abs) min: 1 max: 19312 x̄: 404.23 x̃: 128
helped stats (rel) min: 0.02% max: 28.98% x̄: 3.92% x̃: 2.65%
HURT stats (abs) min: 2 max: 14478 x̄: 1538.60 x̃: 409
HURT stats (rel) min: <.01% max: 23.24% x̄: 3.34% x̃: 0.41%
95% mean confidence interval for cycles value: -333.68 39.03
95% mean confidence interval for cycles %-change: -3.51% -2.41%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 5964 -> 5964 (0.00%)
spills in affected programs: 0 -> 0
helped: 0
HURT: 0
total fills in shared programs: 6909 -> 6909 (0.00%)
fills in affected programs: 0 -> 0
helped: 0
HURT: 0
total sends in shared programs: 1040266 -> 1040266 (0.00%)
sends in affected programs: 0 -> 0
helped: 0
HURT: 0
LOST: 3
GAINED: 1
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24553>
Matt Coster [Mon, 4 Sep 2023 12:55:08 +0000 (13:55 +0100)]
pvr: Cleanup comments in pvr_physical_device_get_supported_*()
pvr_physical_device_get_supported_extensions() contained unneeded
/* clang-format off */ guards.
The section comments in pvr_physical_device_get_supported_features()
also now match the pattern in pvr_physical_device_get_properties().
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25033>
Vignesh Raman [Fri, 28 Jul 2023 09:22:19 +0000 (14:52 +0530)]
ci: enforce -Wimplicit-const-int-float-conversion for clang
All -Wimplicit-const-int-float-conversion warnings are fixed and ci
can drop -Wno-error=implicit-const-int-float-conversion.
Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Acked-by: Helen Koike <helen.koike@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24362>
Vignesh Raman [Mon, 4 Sep 2023 03:24:04 +0000 (08:54 +0530)]
Do explicit cast to suppress clang warnings
Do explicit cast to suppress the below clang warnings,
../src/mesa/main/get.c:86:31: error: implicit conversion from 'int' to 'float' changes value from
2147483647 to
2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
return ( ((F) * 65536.0f > INT_MAX) ? INT_MAX :
../src/mesa/main/texparam.c:967:27: error: implicit conversion from 'int' to 'float' changes value from
2147483647 to
2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
((param > INT_MAX) ? INT_MAX : (GLint) (param + 0.5)) :
../src/mesa/main/texparam.c:2609:65: error: implicit conversion from 'int' to 'float' changes value from
2147483647 to
2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
*params = LCLAMPF(obj->Sampler.Attrib.MinLod, INT_MIN, INT_MAX);
../src/mesa/main/texparam.c:2624:65: error: implicit conversion from 'int' to 'float' changes value from
2147483647 to
2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
*params = LCLAMPF(obj->Sampler.Attrib.MaxLod, INT_MIN, INT_MAX);
../src/mesa/main/texparam.c:2648:72: error: implicit conversion from 'int' to 'float' changes value from
2147483647 to
2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
*params = LCLAMPF(obj->Sampler.Attrib.MaxAnisotropy, INT_MIN, INT_MAX);
../src/mesa/main/texparam.c:2693:66: error: implicit conversion from 'int' to 'float' changes value from
2147483647 to
2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
*params = LCLAMPF(obj->Sampler.Attrib.LodBias, INT_MIN, INT_MAX);
../src/gallium/drivers/freedreno/a3xx/fd3_emit.c:731:43: error: implicit conversion from 'unsigned int' to 'float' changes value from
4294967295 to
4294967296 [-Werror,-Wimplicit-const-int-float-conversion]
OUT_RING(ring, (uint32_t)(zmin * 0xffffffff));
../src/gallium/drivers/freedreno/a3xx/fd3_emit.c:732:43: error: implicit conversion from 'unsigned int' to 'float' changes value from
4294967295 to
4294967296 [-Werror,-Wimplicit-const-int-float-conversion]
OUT_RING(ring, (uint32_t)(zmax * 0xffffffff));
../src/nouveau/codegen/nv50_ir_peephole.cpp:1647:30: error: implicit conversion from 'unsigned int' to 'float' changes value from
4294967295 to
4294967296 [-Werror,-Wimplicit-const-int-float-conversion]
CASE(TYPE_U32, u32, 0, UINT32_MAX, 0, INT32_MAX, 0, UINT32_MAX);
../src/nouveau/codegen/nv50_ir_peephole.cpp:1648:38: error: implicit conversion from 'int' to 'float' changes value from
2147483647 to
2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
CASE(TYPE_S32, s32, INT32_MIN, INT32_MAX, INT32_MIN, INT32_MAX, 0, INT32_MAX);
../src/gallium/drivers/radeonsi/si_nir_lower_vs_inputs.c:400:51: error: implicit conversion from 'unsigned long long' to 'double' changes value from
18446744073709551615 to
18446744073709551616 [-Werror,-Wimplicit-const-int-float-conversion]
loads[chan] = nir_fmul_imm(b, tmp, 1.0 / BITFIELD64_MASK(bits));
../src/gallium/drivers/radeonsi/si_nir_lower_vs_inputs.c:408:43: error: implicit conversion from 'unsigned long long' to 'double' changes value from
18446744073709551615 to
18446744073709551616 [-Werror,-Wimplicit-const-int-float-conversion]
tmp = nir_fmul_imm(b, tmp, 1.0 / BITFIELD64_MASK(bits - 1));
Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Acked-by: Helen Koike <helen.koike@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24362>
Vlad Schiller [Thu, 10 Aug 2023 12:14:38 +0000 (13:14 +0100)]
pvr: Remove PVR_WINSYS_BO_FLAG_ZERO_ON_ALLOC flag
There has been a recent change to the new powervr KMD to always zero buffer
objects at allocation time to avoid information leaks. This change was made to
address upstream feedback [1]. The result is that the
PVR_WINSYS_BO_FLAG_ZERO_ON_ALLOC no longer makes a difference when using this
KMD.
As the powervr KMD is the one we actually care about, it makes sense to mirror
this change when using the downstream pvrsrvkm KMD in order to avoid differences
in behaviour between the two KMDs. As this makes the
PVR_WINSYS_BO_FLAG_ZERO_ON_ALLOC flag entirely redundant, remove it.
[1] https://lists.freedesktop.org/archives/dri-devel/2023-August/418042.html
Signed-off-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24930>
Rohan Garg [Wed, 6 Sep 2023 11:14:42 +0000 (13:14 +0200)]
iris: migrate preemption streamwout wa to WA infra
Fixes: db6c374 ('iris: disable preemption for 3DPRIMITIVE during streamout')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25080>
Samuel Pitoiset [Wed, 6 Sep 2023 06:40:53 +0000 (08:40 +0200)]
zink/ci: merge piglit testing with deqp-runner for RADV
This avoids using an extra script to run GLCTS+piglit.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25062>
Samuel Pitoiset [Tue, 5 Sep 2023 15:54:30 +0000 (17:54 +0200)]
zink/ci: merge GLCTS testing with GLESx for RADV
Both testsuites used to be executed separately because of spurious
failures/hangs but they seem fixed now.
GLCTS+GLES might be faster to run now.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25062>
David Heidelberg [Wed, 30 Aug 2023 20:06:35 +0000 (22:06 +0200)]
ci/farms: no need to check RUNNER_TAG for Collabora farm
Since Google Freedreno and Collabora farm definition split,
we don't need to check for runner tag.
Reported-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24961>
Samuel Pitoiset [Wed, 6 Sep 2023 06:26:12 +0000 (08:26 +0200)]
radv: add support for DGC with SQTT
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25035>
Samuel Pitoiset [Tue, 5 Sep 2023 06:39:21 +0000 (08:39 +0200)]
radv: avoid emitting SQTT markers for DGC calls
This confuses RGP.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25035>
Jordan Justen [Tue, 15 Aug 2023 10:07:30 +0000 (03:07 -0700)]
intel/genxml: Fix comparing xml when node counts differ
This fix is more relevant to MR !20593. Normally when sorting the
number of nodes will be equivalent today, so this bug will not be
encountered. But in !20593, we can shrink (--import) or grow the
number of elements (--flatten) when the genxml_import.py tool is used.
Fixes:
e60a0b16163 ("intel/genxml: Move sorting & writing into GenXml class")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24902>
Jordan Justen [Tue, 15 Aug 2023 22:26:34 +0000 (15:26 -0700)]
intel/genxml: Ignore tail leading/trailing whitespace in node_validator()
When importing or flattening genxml with the genxml_import.py script
in MR !20593, it can lead to the tail portion of xml items differing
in whitespace.
If we strip the trailing and leading whitespace from the tail string,
and the strings are equivalent, then we can consider the xml items to
be equivalent.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24903>
Jordan Justen [Wed, 19 Jul 2023 00:01:28 +0000 (17:01 -0700)]
intel/dev/xe: Move placeholder subslice info into XEHP_FEATURES
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24418>
Chris Spencer [Sat, 12 Aug 2023 13:00:26 +0000 (14:00 +0100)]
radv/video: use correct enum value for max level IDC
Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24649>
Chris Spencer [Sat, 12 Aug 2023 13:00:14 +0000 (14:00 +0100)]
anv/video: use correct enum value for max level IDC
Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24649>
Marek Olšák [Sun, 9 Jul 2023 02:25:19 +0000 (22:25 -0400)]
ac/llvm: don't convert undef to 0 because nir_opt_undef does it now
TOTALS FROM AFFECTED SHADERS (29663/58918)
Code Size:
39163724 ->
37842360 (-3.37 %) bytes
Max Waves: 394813 -> 396334 (0.39 %)
Outputs: 84616 -> 84616 (0.00 %)
Patch Outputs: 0 -> 0 (0.00 %)
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24059>
Marek Olšák [Sat, 8 Jul 2023 23:33:31 +0000 (19:33 -0400)]
nir: remove nir_op_unpack_64 handling from nir_opt_undef
It's no longer needed because undef is replaced with 0 in this case.
It also has a bug that it doesn't freeze the undef value if undef has
multiple uses.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24059>
Marek Olšák [Thu, 6 Jul 2023 08:52:16 +0000 (04:52 -0400)]
nir: replace undef only used by ALU opcodes with 0 or NaN
If undef is consumed by an FP opcode, replace it with NaN to eliminate
that opcode, else replace it with 0, but there are exceptions, such as
when undef is used by stores or phis, it's not touched.
This also contains workarounds for viewperf shaders.
radeonsi:
TOTALS FROM AFFECTED SHADERS (1987/58918)
Code Size: 5158692 -> 5143796 (-0.29 %) bytes
Max Waves: 22456 -> 22513 (0.25 %)
Outputs: 3726 -> 3726 (0.00 %)
Patch Outputs: 0 -> 0 (0.00 %)
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24059>
Jordan Justen [Thu, 30 Mar 2023 07:50:10 +0000 (00:50 -0700)]
intel/clflush: Add support for clflushopt instruction
Rework:
* Split clflushopt into a separate file as recommended by Ken.
If we enable -mclflush on all driver source compilation, then
gcc may insert uses of it on processors that don't support it.
* Add uintptr_t casting to cpu_caps->cacheline usage
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
Jordan Justen [Thu, 30 Mar 2023 06:30:44 +0000 (23:30 -0700)]
meson: Check for the __builtin_ia32_clflushopt function
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
Jordan Justen [Thu, 30 Mar 2023 07:44:52 +0000 (00:44 -0700)]
util/u_cpu_detect: Detect clflushopt support
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
Jordan Justen [Sun, 9 Apr 2023 19:25:14 +0000 (12:25 -0700)]
util/u_cpu_detect: Drop unused has_tsc
This will allow us to add has_clflushopt without spilling into an new
unsigned.
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
Jordan Justen [Fri, 4 Aug 2023 19:55:15 +0000 (12:55 -0700)]
anvil,hasvk: Use intel_flush_range_no_fence to flush command buffers
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
Jordan Justen [Fri, 4 Aug 2023 18:30:17 +0000 (11:30 -0700)]
intel/common: Add intel_flush_range_no_fence
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
Jordan Justen [Fri, 4 Aug 2023 18:37:21 +0000 (11:37 -0700)]
anvil,hasvk: Replace intel_clflush_range with intel_flush_range
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
Jordan Justen [Mon, 10 Apr 2023 06:37:50 +0000 (23:37 -0700)]
intel/common: Move intel_clflush.h to intel_mem.h/intel_mem.c
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
Jordan Justen [Fri, 4 Aug 2023 18:22:05 +0000 (11:22 -0700)]
anvil,hasvk: Rename need_clflush to need_flush
$ git grep -l need_clflush | xargs sed -i 's/need_clflush/need_flush/g'
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>
Karol Herbst [Tue, 5 Sep 2023 15:58:19 +0000 (17:58 +0200)]
rusticl/mesa: create contexts with PIPE_CONTEXT_NO_LOD_BIAS
It's not a thing in OpenCL
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25067>
Sil Vilerino [Mon, 3 Jul 2023 12:54:18 +0000 (08:54 -0400)]
d3d12: Video Decode - Remove unnecessary copy for texture array case
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25069>
antonino [Mon, 21 Aug 2023 21:34:12 +0000 (23:34 +0200)]
drirc: enable `vk_wsi_force_swapchain_to_current_extent` for "Serious Sam Fusion"
This game handles swapchain size incorrecly and can crash because of
it.
Enable this driconf as a workaround.
Fixes:
6139493ae38 ("vulkan/wsi: return VK_SUBOPTIMAL_KHR for sw/x11 on window resize")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24818>
antonino [Mon, 21 Aug 2023 20:52:50 +0000 (22:52 +0200)]
drirc: enable `vk_wsi_force_swapchain_to_current_extent` for "The Talos Principle"
This game handles swapchain size incorrecly and can crash because of
it.
Enable this driconf as a workaround.
Fixes:
6139493ae38 ("vulkan/wsi: return VK_SUBOPTIMAL_KHR for sw/x11 on window resize")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24818>
antonino [Mon, 21 Aug 2023 20:50:34 +0000 (22:50 +0200)]
vulkan/wsi: add `vk_wsi_force_swapchain_to_current_extent` driconf
Add a driconf to force the swapchain size to match
`VkSurfaceCapabilities2KHR::currentExtent` as a workaround for
misbehaved games
Fixes:
6139493ae38 ("vulkan/wsi: return VK_SUBOPTIMAL_KHR for sw/x11 on window resize")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24818>
Dave Airlie [Fri, 1 Sep 2023 05:11:12 +0000 (15:11 +1000)]
llvmpipe: move to nir lowering for fquantize2f16
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24988>
Tapani Pälli [Mon, 4 Sep 2023 10:30:07 +0000 (13:30 +0300)]
driconf: use lower_depth_range_rate for The Spirit and The Mouse
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9738
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25029>
David Heidelberg [Tue, 5 Sep 2023 14:31:11 +0000 (20:01 +0530)]
Revert "ci: disable Google Freedreno farm, currently timeouting on all jobs"
This reverts commit
fc46062ee52e8c09f10bb8cc80e00b73b592e6f4.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25058>
David Rosca [Mon, 21 Aug 2023 09:01:39 +0000 (11:01 +0200)]
frontends/va: Support chroma sample location in postproc
Rename vlVaSetCscMatrix to vlVaSetProcParameters because it now does
more than just setting csc matrix.
Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24869>
David Rosca [Mon, 21 Aug 2023 08:31:40 +0000 (10:31 +0200)]
gallium/auxiliary/vl: Support chroma sample location in compute shaders
Used only in YUV to RGB video_buffer shader for now.
Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24869>
David Rosca [Mon, 21 Aug 2023 08:00:59 +0000 (10:00 +0200)]
gallium/auxiliary/vl: Clamp coordinates in compute shaders
Video textures include padding, so this is needed to avoid sampling
outside of src rect due to scaling or additional offset.
Fixes wrong colors on right/bottom edge.
Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24869>
David Rosca [Mon, 14 Aug 2023 06:58:01 +0000 (08:58 +0200)]
gallium/auxiliary/vl: Map range when updating constants
Use WRITE | DISCARD_RANGE to avoid having to read back the csc matrix
and luma min/max values.
Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24869>
David Rosca [Thu, 27 Jul 2023 11:22:18 +0000 (13:22 +0200)]
gallium/auxiliary: Fix util_compute_blit half texel offset with scaling
Video textures include padding, so make sure to not sample outside
src rect. Also remove the parameter and always use the offset.
When not scaling, this fixes blurry output.
When scaling, this fixes incorrect color at right/bottom edge.
Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24869>
Mike Blumenkrantz [Tue, 5 Sep 2023 14:15:58 +0000 (10:15 -0400)]
zink: polaris ci updates
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25056>
Alyssa Rosenzweig [Mon, 4 Sep 2023 13:44:08 +0000 (09:44 -0400)]
asahi: Skip LOD bias lowering for GLES
This reduces silliness in Dolphin ubershaders by eliminating the double
lowering. It also makes the GLES shader assembly nicer to read.
Dolphin ubershader performance at 4K on MMG improved by about 0.5%. Not massive,
but definitely noticeable and reduces the delta to macOS.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Mon, 4 Sep 2023 13:34:59 +0000 (09:34 -0400)]
gallium,mesa/st: Add PIPE_CONTEXT_NO_LOD_BIAS flag
While desktop GL supports sampler LOD bias, GLES does not. To support the GL use
case, all Gallium drivers are expected to handle sampler LOD bias. However, this
may require shader code to implement (lowering tex to txb, txl to fadd+txl) and
cost resources to push the LOD bias constants into the shader. The issue is
compounded with something like Dolphin's GLES renderer, which does this LOD bias
emulation itself -- meaning that LOD bias is lowered twice when using Dolphin
with GLES! As such, this commit adds a context flag for frontends to communicate
that they will never use sampler LOD bias, allowing the driver to omit the
lowering as a GLES fast path (or, for Dolphin, for performance parity between
GLES and GL).
This will be used on Asahi. It could also be used to optimize a path on
Mali-T720 supported in Panfrost, though I don't intend to write that patch.
Originally https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25034
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Sun, 3 Sep 2023 19:36:33 +0000 (15:36 -0400)]
asahi: Conditionally expose cube arrays
With =deqp. I don't want this exposed before geometry shaders since we run dEQP
(GLES) far more than Piglit (GL), and we need geometry shaders to get adequate
regression testing via dEQP-GLES.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Sun, 3 Sep 2023 19:22:51 +0000 (15:22 -0400)]
asahi: Handle linear 1D Arrays
Lowered to linear 2D Arrays, handle them like that. Fixes 1D Array case of
arb_shader_image_size-builtin.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Sun, 3 Sep 2023 19:22:22 +0000 (15:22 -0400)]
asahi: Forbid linear 1D Array images
Porbably a theoretical case, but these fall down the 2D path so better not allow
it at any rate.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Fri, 18 Aug 2023 23:05:36 +0000 (19:05 -0400)]
agx: Run opt_idiv_const after lowering texture
Shaves 10 instructions off the cube map array lowering.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Fri, 18 Aug 2023 23:04:08 +0000 (19:04 -0400)]
agx: Lower coordinates for cube map array images
Annoyingly different from texture coordinates.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Thu, 17 Aug 2023 17:03:03 +0000 (13:03 -0400)]
agx: Handle cube arrays when clamping arrays
Need to adjust the component.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Thu, 24 Aug 2023 20:27:08 +0000 (16:27 -0400)]
ail: Force page-alignment for layered attachments
When rendering to a layered depth/stencil attachment, we specify the layer
stride in pages. That means that depth/stencil targets must be page-aligned to
be rendered to correctly.
If we're merely sampling, not rendering, we do not need the extra alignment. So
we add a flag to handle this case so we keep passing the generated ail tests.
Fixes KHR-GLES31.core.texture_cube_map_array.color_depth_attachments
Similarly, we page-align colour attachments. I don't have a good theoretical
justification for this part, but it seems to be necessary and layered rendering
fails otherwise. Possibly the PBE requires page-aligned layers unconditionally?
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Thu, 17 Aug 2023 17:03:31 +0000 (13:03 -0400)]
asahi: Translate cube array dimension
Yet another enum.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Wed, 30 Aug 2023 14:10:17 +0000 (10:10 -0400)]
agx: Add unit test for cmp+sel fusing
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Wed, 30 Aug 2023 13:45:06 +0000 (09:45 -0400)]
agx: Add unit test for if_cmp fusing
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Wed, 30 Aug 2023 14:19:19 +0000 (10:19 -0400)]
agx: Fuse compares into selects
This lets us save a LOT of instructions at the cost of increased register
pressure. However, on my shader-db, this is still coming out ahead since no
shaders are hurt for thread count/spills, and only 1/10 of the shaders helped
for instruction count are hurt for register pressure. The shaders most hurt
for pressure have very low pressure (7 -> 15 is the worst case) and you need a
certain number of registers to use a 4 source instruction at all. Analyzing the
hurt shaders, nothing concerns me too much ... this isn't as bad as I feared.
So I think at this point it's worth ripping off the bandage, given the massive
potential for instruction count win. This is a big improvement for some of the
shaders I'm working on for my $SECRET_PROJECT.
total instructions in shared programs: 1784943 -> 1775169 (-0.55%)
instructions in affected programs: 644211 -> 634437 (-1.52%)
helped: 3498
HURT: 38
Instructions are helped.
total bytes in shared programs:
11720734 ->
11643224 (-0.66%)
bytes in affected programs: 4370986 -> 4293476 (-1.77%)
helped: 3572
HURT: 36
Bytes are helped.
total halfregs in shared programs: 474094 -> 475165 (0.23%)
halfregs in affected programs: 12821 -> 13892 (8.35%)
helped: 65
HURT: 247
Halfregs are HURT.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Wed, 30 Aug 2023 13:58:04 +0000 (09:58 -0400)]
agx: Fuse conditions into if's
Simple greedy thing that has the potential to inflate register pressure but
reduces instructions. Thanks to the recent loop work that turns if { break }
into while_icmp, this also implicitly handles fusing conditions into loops,
which is what actually prompted this.
Surprisingly, this helps register pressure on my shader-db (no change to thread
count), I guess by eliminating the boolean temps in case where the sources are
used multiple times.
total instructions in shared programs: 1786561 -> 1784943 (-0.09%)
instructions in affected programs: 128557 -> 126939 (-1.26%)
helped: 474
HURT: 13
Instructions are helped.
total bytes in shared programs:
11733236 ->
11720734 (-0.11%)
bytes in affected programs: 976034 -> 963532 (-1.28%)
helped: 521
HURT: 13
Bytes are helped.
total halfregs in shared programs: 474245 -> 474094 (-0.03%)
halfregs in affected programs: 1869 -> 1718 (-8.08%)
helped: 28
HURT: 7
Halfregs are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Wed, 30 Aug 2023 13:44:51 +0000 (09:44 -0400)]
agx: Generate unfused comparison pseudo ops
So we can optimize them easier.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Wed, 30 Aug 2023 13:40:54 +0000 (09:40 -0400)]
agx: Add pseudo-instructions for icmp/fcmp
Easier to optimize with.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 22:39:37 +0000 (18:39 -0400)]
agx: Only use nest by 1 for loops w/o continue
Apple doesn't do this, but it should be equivalent and it makes it easier to see
that we can use while_icmp for break_if_icmp in loops that don't use continue
(which Apple does do). So, the effect of this commit is to use while_icmp for
most breaks, which saves an instruction.
total instructions in shared programs: 1764199 -> 1764076 (<.01%)
instructions in affected programs: 24149 -> 24026 (-0.51%)
helped: 78
HURT: 0
Instructions are helped.
total bytes in shared programs:
11609306 ->
11608322 (<.01%)
bytes in affected programs: 164604 -> 163620 (-0.60%)
helped: 78
HURT: 0
Bytes are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 22:39:11 +0000 (18:39 -0400)]
agx: Add helper to determine if a NIR loop uses continue
We need to emit extra instructions to handle continues, but if we don't have
any, we can omit those.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 22:17:10 +0000 (18:17 -0400)]
agx: Omit while_icmp without continue
The only role of the while_icmp at the end of a NIR loop is to make continue
jumps work. If, after emitting the loop, we learn that there are no continues,
there is no need to insert a while_icmp since it would be a no-op anyway.
total instructions in shared programs: 1764311 -> 1764199 (<.01%)
instructions in affected programs: 26321 -> 26209 (-0.43%)
helped: 82
HURT: 0
Instructions are helped.
total bytes in shared programs:
11609978 ->
11609306 (<.01%)
bytes in affected programs: 178842 -> 178170 (-0.38%)
helped: 82
HURT: 0
Bytes are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 22:11:32 +0000 (18:11 -0400)]
agx: Omit push_exec at top level
In general, loops need a push_exec at the start for correctness. However, a
push_exec at the top level (non-nested) is a no-op, so we can omit and save a
few cycles.
total instructions in shared programs: 1764350 -> 1764311 (<.01%)
instructions in affected programs: 7339 -> 7300 (-0.53%)
helped: 36
HURT: 0
Instructions are helped.
total bytes in shared programs:
11610212 ->
11609978 (<.01%)
bytes in affected programs: 48638 -> 48404 (-0.48%)
helped: 36
HURT: 0
Bytes are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 21:01:54 +0000 (17:01 -0400)]
agx: Detect conditional breaks
Search for code like
if ... {
break
}
and replace with a break_if pseudo-instruction for optimized handling, since the
break_if lowering is better than the original code.
total instructions in shared programs: 1764596 -> 1764350 (-0.01%)
instructions in affected programs: 24540 -> 24294 (-1.00%)
helped: 78
HURT: 0
Instructions are helped.
total bytes in shared programs:
11611196 ->
11610212 (<.01%)
bytes in affected programs: 166458 -> 165474 (-0.59%)
helped: 78
HURT: 0
Bytes are helped.
shader-db probably understates the benefit here, since this optimizes the body
of loops.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 21:01:43 +0000 (17:01 -0400)]
agx: Use agx_first_instr
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 21:01:00 +0000 (17:01 -0400)]
agx: Add agx_first/last_instr helpers
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 19:12:00 +0000 (15:12 -0400)]
agx: Add break_if_*cmp instructions
To faciliate break optimizations. We use a more efficient lowering than the
literal transition of the NIR.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 18:57:44 +0000 (14:57 -0400)]
agx: Split nest instruction into begin_cf + break
We use it for two different things. Pseudo-instructions are cheap, split it up
for easier optimization passes. This also fixes the schedule classes.. we can
move the cf_begin around if we want, it's inert.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 18:52:40 +0000 (14:52 -0400)]
agx: Lower nest later
As part of pseudo op lowering. Simpler and will simplify control flow opts.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Wed, 30 Aug 2023 21:12:04 +0000 (17:12 -0400)]
agx: Expand nest
For breaking out of deeper control flow.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 18:50:43 +0000 (14:50 -0400)]
agx: Lower pseudo-ops later
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Tue, 29 Aug 2023 18:40:25 +0000 (14:40 -0400)]
agx: Remove logical_end instructions
They're more trouble than they're worth for us. They were originally lifted
unthinkingly from ACO, where I assume they're necessary for software CF
lowering, but they're just an inconvenient convenience for us. Remove em.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Sun, 3 Sep 2023 14:14:14 +0000 (10:14 -0400)]
asahi: Force translucency for ignored render targets
If we bound 4 render targets but we only write to 1 of them, the other 3 need
their contents preserved. This requires either properly configuring HSR to
implement colour masking (TODO) or using the big hammer of setting TRANSLUCENT.
This patch picks the latter for now.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Sat, 2 Sep 2023 20:30:43 +0000 (16:30 -0400)]
agx: Lower pack_32_4x8_split
Fixes test_integer_ops integer_dot_product.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Fri, 1 Sep 2023 09:52:14 +0000 (18:52 +0900)]
asahi: Allow no16 flag for disk cache
The debug flags are already plumbed into driver_flags for the disk
cache, so we just need to actually allow some flags instead of bailing
out of the disk cache init.
We only care about no16 for production right now, and it's probably a
good idea to disable disk caching during most debug sessions, so
allowlist only that one.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 30 Aug 2023 06:42:48 +0000 (15:42 +0900)]
driconf: Disable fp16 for browsers
There are way too many broken WebGL apps using the wrong precision
qualifiers, which causes anything from jittery geometry to complete
breakage (e.g. QuakeJS and other games).
In addition, a Firefox bug is breaking basic canvas rendering for the
same reason (mozilla bug #1845309).
Let's just disable fp16 for browsers. There is no hope of getting all
this broken stuff fixed.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 30 Aug 2023 06:42:04 +0000 (15:42 +0900)]
asahi: Add and support the no_fp16 driconf flag
This is the driconf equivalent of our debug no16 flag, which disables
fp16 support to work around apps using bad GLSL precision qualifiers.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 30 Aug 2023 06:40:27 +0000 (15:40 +0900)]
asahi: Add scaffolding for supporting driconf options
It's time to start using some of these, so add the required scaffolding
to be able to have driver-specific driconf handling for us.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 16 Aug 2023 12:39:19 +0000 (21:39 +0900)]
asahi: Fix VDM pipeline field width
The lower bits have a special meaning, like on the other pipelines.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 16 Aug 2023 12:36:43 +0000 (21:36 +0900)]
asahi: decode: Do not assert on buffer overruns
This kills the hypervisor, let's just print and return.
Also flush after decoding, so that if something else goes wrong at least
we get the logs up to that point.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 16 Aug 2023 12:33:18 +0000 (21:33 +0900)]
asahi: decode: Implement VDM call/ret
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 16 Aug 2023 12:32:44 +0000 (21:32 +0900)]
asahi: cmdbuf: Identify call/ret bits
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Fri, 1 Sep 2023 10:42:50 +0000 (19:42 +0900)]
asahi: Allocate staging resources as staging
We were never setting the flag, which made these resources
write-combine...
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Sat, 15 Apr 2023 23:49:47 +0000 (19:49 -0400)]
agx: Schedule for register pressure
Since we register allocate in SSA, the number of registers required (register
demand) equals to the maximum number of simultaneous live values (register
pressure). So if we can reduce register pressure, we are guaranteed to reduce
register demand. Even an ineffective heuristic like randomly swapping
instructions can only reduce pressure as long as it's conservative.
This implements one such heuristic: in each block, schedule backwards, selecting
the free instruction that looks like it will reduce liveness the most. In other
words, the greedy algorithm to reduce register pressure. At the end of the
block, if we haven't actually reduced pressure, we bail. This isn't optimal, but
it's well-motivated and optimally handles special cases (like 0-source
instructions).
This is based on the scheduler I originally wrote for Mali.
In my Dolphin ubershader branch, this improved performance at native 4K by 10fps
(105fps->115fps) when I measured together with some other optimizations. On top
of my current next (which notably includes nir_opt_sink improvements), this
commit alone goes (53fps->54fps) which is considerably less impressive :-p
shader-db results are a win, but not as large as we might hope. Instruction
count win seems to be from the smaller live ranges being easier on RA (fewer
swaps / moves). The two shaders affected for thread count are from fifa mobile,
which go from 640 threads ->
1024 (full occupancy). In other words... this heuristic does an excellent job in
a small subset of shaders. The Dolphin ubershader win was real, though :~)
Note these shader-db wins are on top of a branch with the nir_opt_sink
improvements. Without that, the stats are much better... The schedulers have
some overlap, but they're better together.
total instructions in shared programs: 1766635 -> 1763496 (-0.18%)
instructions in affected programs: 445855 -> 442716 (-0.70%)
helped: 1963
HURT: 350
Instructions are helped.
total bytes in shared programs:
11597648 ->
11586924 (-0.09%)
bytes in affected programs: 3106230 -> 3095506 (-0.35%)
helped: 2003
HURT: 374
Bytes are helped.
total halfregs in shared programs: 504609 -> 481980 (-4.48%)
halfregs in affected programs: 138322 -> 115693 (-16.36%)
helped: 3405
HURT: 311
Halfregs are helped.
total threads in shared programs:
18839936 ->
18840704 (<.01%)
threads in affected programs: 1280 -> 2048 (60.00%)
helped: 2
HURT: 0
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Thu, 24 Aug 2023 23:12:46 +0000 (19:12 -0400)]
agx: Include schedule class in the opcode info
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Thu, 24 Aug 2023 23:19:07 +0000 (19:19 -0400)]
agx: Add schedule-specialized get_sr variants
Some special registers imply scheduling constraints. We want to have a single
scheduling class per instruction in the IR, so fork off various get_sr variants
depending on what kind of SR we're reading, and validate that we use the right
kind.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Thu, 24 Aug 2023 23:05:47 +0000 (19:05 -0400)]
agx: Annotate opcodes with a scheduling class
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Sun, 20 Aug 2023 17:43:38 +0000 (13:43 -0400)]
agx/validate: Print to stderr
Otherwise unusable.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Sun, 20 Aug 2023 17:10:43 +0000 (13:10 -0400)]
agx: Fix jmp_exec_none encoding
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Thu, 24 Aug 2023 20:01:24 +0000 (16:01 -0400)]
asahi: Fixes for clang-warnings
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Christian Gmeiner [Thu, 24 Aug 2023 15:49:16 +0000 (17:49 +0200)]
agx/lower_address: Remove not used has_offset
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Christian Gmeiner [Thu, 24 Aug 2023 09:01:10 +0000 (11:01 +0200)]
agx/lower_address: Use intrinsics_pass
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Neal Gompa [Wed, 23 Aug 2023 17:02:37 +0000 (13:02 -0400)]
asahi: Fix 32-bit x86 build with correct data type for overflow error message
Currently, when building on 32-bit x86, we get compilation errors
due to data type mis-matches in the format string.
This should fix the issue.
Signed-off-by: Neal Gompa <neal@gompa.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Wed, 30 Aug 2023 09:13:56 +0000 (11:13 +0200)]
rusticl: enable asahi
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Fri, 1 Sep 2023 10:21:33 +0000 (12:21 +0200)]
rusticl/memory: fallback if allocating linear images fails
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Fri, 1 Sep 2023 09:57:02 +0000 (11:57 +0200)]
asahi: handle images in is_format_supported
Some frontends differentiate between textures and images more explicitly
than st/mesa. So we might end up with PIPE_BIND_SHADER_IMAGE but not
PIPE_BIND_SAMPLER_VIEW in is_format_supported.
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Fri, 1 Sep 2023 09:52:50 +0000 (11:52 +0200)]
asahi: gracefully handle allocating linear images
Frontends might try to allocate linear textures or images, we should
gracefully return NULL so frontends can do fallback paths.
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Wed, 30 Aug 2023 09:21:13 +0000 (11:21 +0200)]
asahi: implement clear_buffer
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Fri, 3 Feb 2023 17:42:50 +0000 (18:42 +0100)]
asahi: implement set_global_binding
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>