Apply suggestions to Intel extensions PR

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Update generated files

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Add SPV_INTEL_long_constant_composite extension

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Add SPV_INTEL_loop_fuse extension

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Add SPV_INTEL_fpga_cluster_attributes and SPV_INTEL_fp_fast_math_mode

Spec:
https://github.com/KhronosGroup/SPIRV-Registry/blob/7d96a31cf56c60de76a6ae7a26ace3c7bfd999bf/extensions/INTEL/SPV_INTEL_fpga_cluster_attributes.asciidoc
https://github.com/KhronosGroup/SPIRV-Registry/blob/7d96a31cf56c60de76a6ae7a26ace3c7bfd999bf/extensions/INTEL/SPV_INTEL_fp_fast_math_mode.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Update SPV_INTEL_fpga_loop_controls extension

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Update SPV_INTEL_kernel_attributes extension

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Update SPV_INTEL_function_pointers extension

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_float_controls2 extension

Spec:
https://github.com/intel/llvm/blob/39fa9b0cbfbae88327118990a05c5b387b56d2ef/sycl/doc/extensions/SPIRV/SPV_INTEL_float_controls2.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_vector_compute extension

Spec:
https://github.com/intel/llvm/blob/e185a6b49e4bc9806a799b774977f1196b24f0d6/sycl/doc/extensions/SPIRV/SPV_INTEL_vector_compute.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_fpga_memory_accesses extension

Spec:
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_fpga_memory_accesses.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_io_pipes extension

Spec:
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_io_pipes.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_variable_length_array extension

Spec:
https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_variable_length_array.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_usm_storage_classes extension

Spec:
https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_usm_storage_classes.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_arbitrary_precision_integers extensions

Spec:
https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_arbitrary_precision_int.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_inline_assembly extension

Spec:
https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_inline_assembly.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Upstream SPV_INTEL_fpga_buffer_location extension

Spec:
https://github.com/intel/llvm/blob/2237b42035f31cb10b16d4f9abaeed45bed98587/sycl/doc/extensions/SPIRV/SPV_INTEL_fpga_buffer_location.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Merge pull request #184 from dgkoch/dkoch_remove_hittkhr

remove HitTKHR alias

remove HitTKHR

It was not added to the SPV_KHR_ray_tracing extension since it is just
an alias of RayTMaxKHR.

Merge pull request #180 from dneto0/issue-179

MeshShadingNV enables builtins PrimitiveId, Layer, and ViewportIndex

MeshShadingNV enables builtins PrimitiveId, Layer, and ViewportIndex

Fixes #179

See extension SPV_NV_mesh_shader

Merge pull request #182 from dgkoch/khr_rt_final

Updates to final ray tracing extensions

de-alias/reassign OpIgnoreIntersectionKHR/OpTerminateRayKHR

vulkan/vulkan#2374

Raytracing and Rayquery updates for final

Updated headers for new trace/executeCallable and acceleration structure cast.

Reserve additional loop control bit for Intel extension (NoFusionINTEL) (#175)

Add EmbarkStudios/rust-gpu to vendor list. (#174)

Bump revision to 4, for SPIR-V 1.5.

Add SPV_EXT_shader_image_int64 (#170)

Co-authored-by: Arkadiusz Sarwa <arkadiusz.sarwa@amd.com>

Added SPV_KHR_fragment_shading_rate (#172)

 Register the Xenia emulator as a generator (#171)

Register the Messiah SPIR-V CodeGen (#169)

Register the ANGLE compiler (#168)

Rebuild of latest headers, which slightly moves OpTerminateInvocation

Reserve SPIR-V token range for upcoming Intel extensions. (#165)

Update BUILD.bazel and BUILD.gn (#166)

* Export NonSemantic.ClspvReflection.h for both
* Add exports for the extended instruction sets in the unified1
  directory (for use in SPIRV-Tools)

Publish the headers for the clspv embedded reflection non-semantic extended instruction set (#164)

* Clspv non-semantic reflection instruction set
* Version 1

Update the registry in spir-v.xml to modernize and split out opcodes. (#156)

Support SPV_KHR_terminate_invocation (#163)

* Support SPV_KHR_terminate_invocation

* Fix order in spirv.core.grammar.json

Co-authored-by: David Neto <dneto@google.com>

Merge pull request #162 from vkushwaha-nv/SPV_EXT_shader_atomic_float

Add changes for SPV_EXT_shader_atomic_float

Add changes for SPV_EXT_shader_atomic_float

Merge pull request #160 from dj2/reg_tint

Register the Tint compiler

Register the Tint compiler

Merge pull request #159 from dneto0/fix-quotes

spir-v.xml: Use plain ASCII quotes in comment

spir-v.xml: Use plain ASCII quotes in comment

Avoids parse error on Windows-based Python3.

Merge pull request #158 from mkinsner/mkinsner/fpfastmath_allocation_mechanism

Propose bit allocation mechanism for the FP Fast Math Mode bitfield

Rebuild headers against the previous grammar commit.

Merge pull request #150 from MrSidims/private/MrSidims/UpstreamIntelExt

Add Intel specific definitions from https://github.com/KhronosGroup/S…

Apply suggestions

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Add Intel specific definitions from KhronosGroup/SPIRV-LLVM-Translator

List of extensions:
SPV_INTEL_fpga_memory_attributes
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_fpga_memory_attributes.asciidoc

SPV_INTEL_kernel_attributes
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_kernel_attributes.asciidoc

SPV_INTEL_fpga_reg
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_fpga_reg.asciidoc

SPV_INTEL_blocking_pipes
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_blocking_pipes.asciidoc

SPV_INTEL_fpga_loop_controls
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_fpga_loop_controls.asciidoc

SPV_INTEL_unstructured_loop_controls
https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_unstructured_loop_controls.asciidoc

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Header build from previous grammar update.

Merge pull request #152 from MrSidims/private/MrSidims/FunctionPointers

Add SPV_INTEL_function_pointers preview extension

Propose bit allocation mechanism for the FP Fast Math Mode bitfield, following from the mechanism previously added for the loop control bitfield.

Merge pull request #157 from dneto0/update-example

Update example to use unified1 headers

Update example to use unified1 headers

Also remove the 1.1-specific example.

Update headers to SPIR-V 1.5 Revision 3

Add a bunch of missing "version" : "None" for ray tracing.

Rebuild the headers with the fixed grammar file.

See previous 2 commits.

Add missing "version" : "None" for ShaderCallKHR

Grammar: The ray-tracing updates were not done in numerical ordering.

This makes management difficult.  See the readme:

Care should be taken to follow existing precedent in populating the
details of reserved tokens. This includes:
 * keeping enumerants in numeric order

Discuss generator magic number reservations.

Add SPV_INTEL_function_pointers preview extension

Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>

Merge pull request #149 from dgkoch/prov_ray_tracing

Add SPV_KHR_ray_{tracing,query} to headers

Add shadercalls scope

and update copyright notices

Added ray flags, primitive culling flags, queries

Non-functional: Update header build to match Khronos spec. builder.

Merge pull request #135 from vulturm/patch-1

Also propagate SPIRV-Headers version to CMakeLists.txt

Update headers for SPV_KHR_ray_tracing.

Merge pull request #148 from null77/fix-gn

Add missing header to BUILD.gn.

Add missing header to BUILD.gn.

File: include/spirv/unified1/NonSemanticDebugPrintf.h was missing.
This was causing a presubmit step to fail in ANGLE.

Merge pull request #146 from s-perron/bazel

Export NonSemanticDebugPrintf.h in bazel build

Export NonSemanticDebugPrintf.h in bazel build

Merge pull request #145 from jeffbolznv/nonsemantic_debugprintf

Add NonSemantic.DebugPrintf JSON/header

Add NonSemantic.DebugPrintf JSON/header

Fix max enum value

Add grammars, C header, and header generator for vendor and KHR extended instruction sets (#143)

* Add JSON grammars for extened instruction sets

Add AMD extended instruction sets
Add DebugInfo
Add OpenCL.DebugInfo.100

* Add script to generate C headers from extinst grammar

This is cloned then adapted from the same-named script in SPIRV-Tools
(contributed under same authorship but different copyright).

Invoke the script as part of the overall header generation script.

* Add generated C header for extended instruction sets

Add for DebugInfo and OpenCLDebugInfo
Add for AMD vendor extended instruction sets

* Update the README for extinst header generation

* Fix header include guard to match directory structure

* Ensure generated header ends in newline

* Fix typo in file reference

* Fix name of AMD_shader_explicit_vertex_parameter.h

* Avoid duplicate generation

* Split Revision and Version enum values by newlines

Per code review request

* Convert C header generator driver to Python3

* Fix README for Python3 for extinst header generation

* Use 4-space in generated headers, consistently

Merge pull request #142 from mkinsner/additional_loop_control_bits

Allocate three loop control bits for an upcoming Intel extension

Allocate three bits for upcoming Intel extension

Merge pull request #141 from dneto0/update-buildgn-lic

Fix the license to match LICENSE

Fix the license to match LICENSE

(Code was committed by Googler, so it is owned by Google. I can change it.)

Merge pull request #140 from ShabbyX/add_build_gn

Add BUILD.gn

Add BUILD.gn

Signed-off-by: Shahbaz Youssefi <syoussefi@google.com>

Also propagate SPIRV-Headers version to CMakeLists.txt

Merge pull request #134 from Tobski/patch-1

Reserve a new block of 64 opcodes

Off-by-one errors

Reserve a new block of 64 opcodes

Versioning: Complete the versioning change in recent commits.

These didn't include a full rebuild of the headers.

Merge pull request #133 from nhaehnle/buildHeader-spv15

buildHeaders: update version to SPIR-V 1.5

buildHeaders: update version to SPIR-V 1.5

This seems to have gotten dropped in the latest update.

Merge pull request #131 from lukaszgotszaldintel/new_branch

add cmake option SPIRV_HEADERS_SKIP_INSTALL

Merge pull request #128 from amdrexu/bugfix

Bump the SPIR-V version to 1.5

Merge pull request #129 from ehsannas/update_doc

Improve the doc on using Bazel.

Improve the doc on using Bazel.

Merge pull request #127 from ehsannas/add_bazel_build

Add a Bazel build file.

add cmake option SPIRV_HEADERS_SKIP_INSTALL

Bump the SPIR-V version to 1.5

Update documentation.

Add a Bazel build file.

Add SPV_KHR_physical_storage_buffer.

This just parallels SPV_EXT_physical_storage_buffer.

SPIR-V 1.5.