Dylan Baker [Fri, 15 Jun 2018 20:53:25 +0000 (13:53 -0700)]
docs: Update release-notes and calendar
Dylan Baker [Fri, 15 Jun 2018 20:45:10 +0000 (13:45 -0700)]
docs: Add release notes for 18.1.2
Rafael Antognolli [Tue, 12 Jun 2018 19:18:19 +0000 (12:18 -0700)]
intel/aubinator: Use int to store getopt_long flags.
getopt_long flag parameter is an int pointer, so if we use bool to store
those values, when getopt_long writes to one of them, it might end up
overwriting the next one.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Samuel Pitoiset [Fri, 15 Jun 2018 14:50:11 +0000 (16:50 +0200)]
Revert "radv: always set/load both depth and stencil clear values"
This fixes a rendering regression with RoTR.
This reverts commit
4bdad9faddc82a4560603936ce5ade5707ecb254.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 15 Jun 2018 13:53:23 +0000 (15:53 +0200)]
radv: don't check for linear images in emit_fast_color_clear()
We don't enable CMASK for linear surfaces and addrlib only
enables DCC for tiling surfaces.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Jun 2018 09:06:02 +0000 (11:06 +0200)]
radv: allow RADV_PERFTEST=dccmsaa on GFX9
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Jun 2018 12:28:58 +0000 (14:28 +0200)]
radv: add RADV_DEBUG=checkir
This allows to run the LLVM verifier pass.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Jun 2018 11:26:23 +0000 (13:26 +0200)]
radv: update ZRANGE_PRECISION in radv_update_bound_fast_clear_ds()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Jun 2018 11:26:22 +0000 (13:26 +0200)]
radv: clean up radv_{set,load}_depth_clear_regs() helpers
And replace _regs by _metadata because it makes more sense.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Jun 2018 11:26:21 +0000 (13:26 +0200)]
radv: always set/load both depth and stencil clear values
I don't think that matter much to emit both values and that
makes the code a bit simpler.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Jun 2018 11:26:20 +0000 (13:26 +0200)]
radv: update the fast ds clear values only if the image is bound
It's unnecessary to update the fast depth/stencil clear values
if the fast cleared depth/stencil image isn't currently bound.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Jun 2018 11:26:19 +0000 (13:26 +0200)]
radv: clean up radv_{set,load}_color_clear_regs() helpers
And replace _regs by _metadata because it makes more sense.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 14 Jun 2018 11:26:18 +0000 (13:26 +0200)]
radv: update the fast color clear values only if the image is bound
It's unnecessary to update the fast color clear values if the
fast cleared color image isn't currently bound.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Christian Gmeiner [Fri, 15 Jun 2018 10:18:56 +0000 (12:18 +0200)]
util/bitset: include util/macro.h
BITSET_FFS(x) macro makes use of ARRAY_SIZE(x) macro which is
defined in util/macro.h. Include it directy to make usage more
straightforward.
Fixes:
692bd4a1ab9 ("util: replace Elements() with ARRAY_SIZE()")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Lukas Rusak [Mon, 4 Jun 2018 19:38:41 +0000 (12:38 -0700)]
meson: fix private libs when building without glx
I noticed that the generated pkg-config files will include
glx and x11 dependencies even when x11 isn't a selected platform.
This fixes the private libs and was tested by building kmscube
V2:
- check if gallium-xlib is being used for glx
Fixes:
108d257a16859898f5ce0 "meson: build libEGL"
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Rhys Perry [Fri, 15 Jun 2018 01:56:28 +0000 (19:56 -0600)]
docs: document addition of GL_ARB_sample_locations for nvc0
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com> (v2)
Rhys Perry [Fri, 15 Jun 2018 01:56:28 +0000 (19:56 -0600)]
nvc0: add support for programmable sample locations
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Rhys Perry [Fri, 15 Jun 2018 01:56:28 +0000 (19:56 -0600)]
st/mesa: add support for ARB_sample_locations
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
Rhys Perry [Fri, 15 Jun 2018 01:56:28 +0000 (19:56 -0600)]
gallium: add support for programmable sample locations
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
Rhys Perry [Fri, 15 Jun 2018 01:56:28 +0000 (19:56 -0600)]
mesa: add support for ARB_sample_locations
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
Eric Anholt [Wed, 13 Jun 2018 20:44:01 +0000 (13:44 -0700)]
v3d: Fix polygon offset for Z16 buffers.
Fixes:
dEQP-GLES3.functional.polygon_offset.fixed16_displacement_with_units
dEQP-GLES3.functional.polygon_offset.fixed16_render_with_units
Eric Anholt [Wed, 13 Jun 2018 20:38:33 +0000 (13:38 -0700)]
v3d: Fix configuration setup of mixed f32 and f16 render targets.
Fixes dEQP-GLES3.functional.fragment_out.random.26 and 6 others.
Eric Anholt [Wed, 13 Jun 2018 19:58:22 +0000 (12:58 -0700)]
v3d: Don't set the first_ez_state to DISABLED if after only UNDECIDED draws.
We need to have the RCL start with EZ enabled, since those undecided draws
had EZ enabled. But we do need to update from UNDECIDED to LT or GT as
necessary still.
Fixes many simulator assertion fails in deqp
fragment_ops/interaction/basic_shader/*
Eric Anholt [Fri, 8 Jun 2018 15:35:50 +0000 (08:35 -0700)]
v3d: Use the right size for v3d 4.x TEXTURE_SHADER_STATE BO.
This doesn't really matter, since they both get rounded up to 4096.
Eric Anholt [Fri, 8 Jun 2018 15:31:58 +0000 (08:31 -0700)]
v3d: Add static asserts for other packed packet sizes.
Eric Anholt [Fri, 8 Jun 2018 15:31:30 +0000 (08:31 -0700)]
v3d: Fix the size of the packed attribute state.
Fixes segfaults in dEQP-GLES3.functional.vertex_array_objects.all_attributes.
Eric Anholt [Fri, 8 Jun 2018 15:04:00 +0000 (08:04 -0700)]
v3d: Remove some unused context fields from vc4.
Eric Anholt [Fri, 8 Jun 2018 15:32:34 +0000 (08:32 -0700)]
v3d: Remove unused QUNIFORM_STENCIL left over from vc4.
Eric Anholt [Fri, 8 Jun 2018 15:00:31 +0000 (08:00 -0700)]
v3d: Use our #define for max attributes in shader caps.
Eric Anholt [Thu, 7 Jun 2018 04:06:44 +0000 (21:06 -0700)]
v3d: Fix undefined results for a swap_color_rb RT from a float shader output.
Fixes segfaults and undefined behavior in
dEQP-GLES3.functional.fragment_out.basic.fixed.srgb8_alpha8_lowp_float
Dave Airlie [Thu, 14 Jun 2018 22:48:54 +0000 (08:48 +1000)]
radv: remove multisample bit from shader key.
This wasn't being used anywhere inside the shader from what I can see.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Kenneth Graunke [Fri, 8 Jun 2018 21:24:16 +0000 (14:24 -0700)]
intel/compiler: Properly consider UBO loads that cross 32B boundaries.
The UBO push analysis pass incorrectly assumed that all values would fit
within a 32B chunk, and only recorded a bit for the 32B chunk containing
the starting offset.
For example, if a UBO contained the following, tightly packed:
vec4 a; // [0, 16)
float b; // [16, 20)
vec4 c; // [20, 36)
then, c would start at offset 20 / 32 = 0 and end at 36 / 32 = 1,
which means that we ought to record two 32B chunks in the bitfield.
Similarly, dvec4s would suffer from the same problem.
v2: Rewrite the accounting, my calculations were wrong.
v3: Write a comment about partial values (requested by Jason).
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> [v1]
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> [v3]
Ian Romanick [Tue, 5 Jun 2018 23:02:25 +0000 (16:02 -0700)]
glsl: Don't copy propagate elements from SSBO or shared variables either
Since SSBOs can be written by a different GPU thread, copy propagating a
read can cause the value to magically change. SSBO reads are also very
expensive, so doing it twice will be slower.
The same shader was helped by this patch and the previous.
Haswell, Broadwell, and Skylake had similar results. (Skylake shown)
total instructions in shared programs:
14399119 ->
14399113 (<.01%)
instructions in affected programs: 683 -> 677 (-0.88%)
helped: 1
HURT: 0
total cycles in shared programs:
532973113 ->
532971865 (<.01%)
cycles in affected programs: 524666 -> 523418 (-0.24%)
helped: 1
HURT: 0
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106774
Ian Romanick [Tue, 5 Jun 2018 22:04:24 +0000 (15:04 -0700)]
glsl: Don't copy propagate from SSBO or shared variables either
Since SSBOs can be written by other GPU threads, copy propagating a read
can cause the value to magically change. SSBO reads are also very
expensive, so doing it twice will be slower.
Haswell, Broadwell, and Skylake had similar results. (Skylake shown)
total instructions in shared programs:
14399120 ->
14399119 (<.01%)
instructions in affected programs: 684 -> 683 (-0.15%)
helped: 1
HURT: 0
total cycles in shared programs:
532978931 ->
532973113 (<.01%)
cycles in affected programs: 530484 -> 524666 (-1.10%)
helped: 1
HURT: 0
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106774
Lukas Rusak [Fri, 1 Jun 2018 21:09:42 +0000 (14:09 -0700)]
meson: only build vl_winsys_dri.c when x11 platform is used
This seems to have been missed in the move from autotools
This fixes the following build issue:
../src/gallium/auxiliary/vl/vl_winsys_dri.c:34:10: fatal error: X11/Xlib-xcb.h: No such file or directory
#include <X11/Xlib-xcb.h>
^~~~~~~~~~~~~~~~
Fixes:
b1b65397d0c4978e36a84c0a1c98a4bd6cb9588e
("meson: Build gallium auxiliary")
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Brian Paul [Thu, 14 Jun 2018 15:12:19 +0000 (09:12 -0600)]
st/mesa: add missing switch cases in glsl_to_tgsi_visitor::visit()
To silence compiler warning about unhandled switch cases.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Bas Nieuwenhuizen [Wed, 13 Jun 2018 21:31:54 +0000 (23:31 +0200)]
radv: Fix output for sparse MRTs.
We need to init the cb_shader_format correctly with the changed
col_format, so this moves the col_format adjustment to before the
adjustment to before the cb_shader_mask gets generated.
Fixes:
06d3c650980 "radv: fix a GPU hang when MRTs are sparse"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106903
CC: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Wed, 13 Jun 2018 12:27:40 +0000 (14:27 +0200)]
radv: update the ZRANGE_PRECISION value for the TC-compat bug
On GFX8+, there is a bug that affects TC-compatible depth surfaces
when the ZRange is not reset after LateZ kills pixels.
The workaround is to always set DB_Z_INFO.ZRANGE_PRECISION to match
the last fast clear value. Because the value is set to 1 by default,
we only need to update it when clearing Z to 0.0.
We also need to set the depth clear regs and to update
ZRANGE_PRECISION when initializing a TC-compat depth image to 0.
Original patch from James Legg.
This fixes random CTS fails with
dEQP-VK.renderpass.suballocation.formats.d32_sfloat_s8_uint.input.*
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105396
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Iglesias Gonsálvez [Mon, 28 May 2018 09:42:15 +0000 (11:42 +0200)]
anv: reduce maxFragmentInputComponents
If the application asks for the maximum number of fragment input
components (128), use all of them plus some builtins that are
passed in the VUE, then we exceed the maximum number of used VUE
slots (32) and we break one assert that checks this limit.
Also, with separate shader objects, we add CLIP_DIST0, CLIP_DIST1
builtins in brw_compute_vue_map() because we don't know if
gl_ClipDistance is going to be read/write by an adjacent stage.
Fixes VK-GL-CTS CL#2569.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Marek Olšák [Fri, 1 Jun 2018 23:29:45 +0000 (19:29 -0400)]
radeonsi/gfx9: fix si_get_buffer_from_descriptors for 48-bit pointers
This fixes:
GL45-CTS.pipeline_statistics_query_tests_ARB.functional_compute_shader_invocations
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Fri, 1 Jun 2018 04:33:57 +0000 (00:33 -0400)]
radeonsi/gfx9: update & clean up a DPBB heuristic
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Fri, 1 Jun 2018 04:21:49 +0000 (00:21 -0400)]
radeonsi/gfx9: set POPS_DRAIN_PS_ON_OVERLAP due to a hw bug
This may not be needed yet, but let's set it now.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Fri, 1 Jun 2018 04:06:35 +0000 (00:06 -0400)]
radeonsi/gfx9: remove UINT_MAX array terminators in bin size tables
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Fri, 1 Jun 2018 03:48:03 +0000 (23:48 -0400)]
radeonsi/gfx9: update bin sizes
This is based on our docs (recently updated), not amdvlk.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Fri, 1 Jun 2018 03:47:17 +0000 (23:47 -0400)]
radeonsi/gfx9: update primitive binning code for EQAA
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Thu, 31 May 2018 03:21:28 +0000 (23:21 -0400)]
radeonsi: assume that rasterizer state is non-NULL in draw_vbo
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Thu, 31 May 2018 02:59:41 +0000 (22:59 -0400)]
radeonsi: micro-optimize prim checking and fix guardband with lines+adjacency
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Thu, 31 May 2018 02:38:05 +0000 (22:38 -0400)]
radeonsi: move the guardband registers into a separate state atom
They have a different frequency of updates and don't change when scissors
change.
I think this even fixes something in si_update_vs_viewport_state.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Thu, 31 May 2018 02:02:00 +0000 (22:02 -0400)]
radeonsi/gfx9: implement the scissor bug workaround without performance drop
This might improve performance on Vega10 and Raven.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Thu, 31 May 2018 01:24:06 +0000 (21:24 -0400)]
radeonsi: don't set VGT_LS_HS_CONFIG if it doesn't change
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Thu, 31 May 2018 01:16:14 +0000 (21:16 -0400)]
radeonsi: move VGT_GS_OUT_PRIM_TYPE into si_shader_gs
same as amdvlk.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Fri, 25 May 2018 21:37:51 +0000 (17:37 -0400)]
radeonsi: record CLIPVERTEX output usage properly for compatibility profiles
This was missed when adding CLIPVERTEX support into GS & tess.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Fri, 18 May 2018 03:26:56 +0000 (23:26 -0400)]
radeonsi: fix FBFETCH with 2D MSAA arrays
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Fri, 18 May 2018 03:23:24 +0000 (23:23 -0400)]
ac: handle undefined EQAA samples in ac_apply_fmask_to_sample
RADV might wanna use this helper too.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Marek Olšák [Wed, 13 Jun 2018 01:13:44 +0000 (21:13 -0400)]
radeonsi: return real memory usage instead of per-process usage
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Marek Olšák [Wed, 13 Jun 2018 00:59:42 +0000 (20:59 -0400)]
ac/gpu_info: report real total memory sizes
The change from MIN2 to MAX2 is intentional.
Cc: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Thu, 14 Jun 2018 00:37:28 +0000 (10:37 +1000)]
docs: mark virgl GL 4.0 features as complete.
virgl should now expose GL4.1 where it can.
Dave Airlie [Fri, 8 Jun 2018 04:38:14 +0000 (14:38 +1000)]
virgl: add ARB_tessellation_shader support. (v2)
This should add all the pieces to enable tess shaders on virgl.
v2: fixup transform to handle tess and strip out precise.
set default for max patch varyings to work around issue when
tess gets enabled from v1 caps but v2 caps aren't in place. (Elie)
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Dave Airlie [Wed, 13 Jun 2018 23:52:21 +0000 (09:52 +1000)]
glsl: allow standalone semicolons outside main()
GLSL 4.60 offically added this but games and older CTS suites actually
had shaders that did this, we may as well enable it everywhere.
Adding stable because it appears apps in the wild do this.
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Samuel Pitoiset [Wed, 13 Jun 2018 18:19:23 +0000 (20:19 +0200)]
radv: don't fast clear HTILE for 16-bit depth surfaces on GFX8
This causes rendering issues in Shadow Warrior 2 with DXVK.
Cc: mesa-stable@lists.freedesktop.org
Fixes:
ccc64f3133 ("radv: enable TC-compat HTILE for 16-bit depth surfaces on GFX8")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106912
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Andrew Galante [Mon, 11 Jun 2018 22:05:25 +0000 (15:05 -0700)]
configure.ac: Test for __atomic_add_fetch in atomic checks
Some platforms have 64-bit __atomic_load_n but not 64-bit
__atomic_add_fetch, so test for both of them.
Bug: https://bugs.gentoo.org/655616
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Andrew Galante [Mon, 11 Jun 2018 22:03:36 +0000 (15:03 -0700)]
meson: Test for __atomic_add_fetch in atomic checks
Some platforms have 64-bit __atomic_load_n but not 64-bit
__atomic_add_fetch, so test for both of them.
Bug: https://bugs.gentoo.org/655616
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Matt Turner [Mon, 11 Jun 2018 21:56:26 +0000 (14:56 -0700)]
meson: Fix -latomic check
Commit
54ba73ef102f (configure.ac/meson.build: Fix -latomic test) fixed
some checks for -latomic, and then commit
54bbe600ec26 (configure.ac:
rework -latomic check) further extended the fixes in configure.ac but
not in Meson. This commit extends those fixes to the Meson tests.
Fixes:
54bbe600ec26 (configure.ac: rework -latomic check)
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Dylan Baker [Tue, 12 Jun 2018 16:03:28 +0000 (09:03 -0700)]
meson: Remove various completed todos
v3: - Remove "won't do" todos, so only completed todo's are now removed.
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com> (v2)
Dylan Baker [Thu, 7 Jun 2018 18:22:48 +0000 (11:22 -0700)]
meson: Make use of optional modules
meson 0.43 gained support for optional modules, which clover wold like
to use. Since we require 0.44.1 now we can rely on them being available
for clover.
compile tested only.
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Dylan Baker [Thu, 7 Jun 2018 18:13:34 +0000 (11:13 -0700)]
meson: Add support for ppc assembly/optimizations
v2: - Use -mpower8-vector in compiler test for altivec
- rename altivec option to power8
- reword power8 option description to be more clear, originally I
had made it a boolean, but replaced it with an auto option.
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Dylan Baker [Thu, 7 Jun 2018 17:58:06 +0000 (10:58 -0700)]
meson: Add support for SPARC assembly
This was blindly copied from autotools and tested by a helpful gentoo
user.
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Dylan Baker [Mon, 11 Jun 2018 17:12:46 +0000 (10:12 -0700)]
meson: Set include dirs for asm
v2: - split this from the next patch
- Only include x86-64 and not x86 when buiding x86_64
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Dylan Baker [Mon, 11 Jun 2018 17:15:15 +0000 (10:15 -0700)]
meson: move cc and cpp definitions to top of main meson.build
This just makes using cc and cpp easier.
v2: - Add this patch to fix altivec
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Wed, 13 Jun 2018 16:23:28 +0000 (09:23 -0700)]
Revert "intel/compiler: Properly consider UBO loads that cross 32B boundaries."
This reverts commit
b8fa847c2ed9c7c743f31e57560a09fae3992f46.
This broke about 30k Vulkan CTS tests.
Kenneth Graunke [Fri, 8 Jun 2018 21:24:16 +0000 (14:24 -0700)]
intel/compiler: Properly consider UBO loads that cross 32B boundaries.
The UBO push analysis pass incorrectly assumed that all values would fit
within a 32B chunk, and only recorded a bit for the 32B chunk containing
the starting offset.
For example, if a UBO contained the following, tightly packed:
vec4 a; // [0, 16)
float b; // [16, 20)
vec4 c; // [20, 36)
then, c would start at offset 20 / 32 = 0 and end at 36 / 32 = 1,
which means that we ought to record two 32B chunks in the bitfield.
Similarly, dvec4s would suffer from the same problem.
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Ross Burton [Tue, 12 Jun 2018 10:59:01 +0000 (11:59 +0100)]
drivers/dri/i965: add missing #include
brw_bufmgr.h uses time_t without include time.h, so the build fails under musl.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Mauro Rossi [Sun, 3 Jun 2018 18:41:59 +0000 (20:41 +0200)]
anv/android: Use an address for each anv_image plane
Fixes to avoid building error after change in image->planes[] structure,
{bo,bo_offset} has to be replaced by address.{bo,offset}
and update is needed also in the assert() for debug builds.
external/mesa/src/intel/vulkan/anv_android.c:188:21:
error: no member named 'bo' in 'struct anv_image::(anonymous at external/mesa/src/intel/vulkan/anv_private.h:2647:4)'
image->planes[0].bo = bo;
~~~~~~~~~~~~~~~~ ^
1 error generated.
Fixes:
bf34ef16ac ("anv: Use an address for each anv_image plane")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Mauro Rossi [Mon, 4 Jun 2018 00:48:09 +0000 (02:48 +0200)]
anv/android: Set the BO flags in bo_cache_import (v2)
Changes to avoid building error:
external/mesa/src/intel/vulkan/anv_android.c:131:72:
error: too few arguments to function call, expected 5, have 4
result = anv_bo_cache_import(device, &device->bo_cache, dma_buf, &bo);
~~~~~~~~~~~~~~~~~~~ ^
1 error generated.
(v2) Set the correct bo_flags based on support of 48bit addresses and soft-pin
Fixes:
b0d50247a7 ("anv/allocator: Set the BO flags in bo_cache_alloc/import")
Fixes:
e7d0378bd9 ("anv: Soft-pin client-allocated memory")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Thu, 7 Jun 2018 22:44:43 +0000 (15:44 -0700)]
anv: Disable __gen_validate_value if NDEBUG is set.
We were enabling undefined memory checking for genxml values based on
Valgrind being installed at build time, even for release builds. This
generates piles and piles of assembly whenever you touch genxml.
With gcc 7.3.1 and -O3 and -march=native on a Kabylake with Valgrind
installed at build time:
text data bss dec hex filename
5978385 262884 13488 6254757 5f70a5 libvulkan_intel.so
3799377 262884 13488 4075749 3e30e5 libvulkan_intel.so
That's a 36% reduction in text size.
Fixes:
047ed02723071d7eccbed3210b5be6ae73603a53 (vk/emit: Use valgrind to validate every packed field)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Engestrom [Mon, 11 Jun 2018 17:34:42 +0000 (18:34 +0100)]
README: wording fix for previous commit
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 11 Jun 2018 17:31:06 +0000 (18:31 +0100)]
README: add link to WhosWho for IRC nicks
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Fri, 8 Jun 2018 15:56:03 +0000 (16:56 +0100)]
add project README
Now that we're using GitLab, let's take advantage of the "landing page"
README feature with some minimal information, mostly to point people to
the right resources.
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Sun, 10 Jun 2018 17:42:45 +0000 (18:42 +0100)]
i965: fix resource leak
v2: intel_miptree_release() already takes care of the planes, no need
to hand-code the loop (Lionel)
Coverity ID: 1436909
Fixes:
3352f2d746d3959b22ca4 "i965: Create multiple miptrees for planar YUV images"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Rob Clark [Thu, 7 Jun 2018 19:44:28 +0000 (15:44 -0400)]
freedreno/ir3: use pipe_image_view's cpp
At least for PIPE_BUFFER, we could get the resource used as (for
example) R32F imageBuffer. So using cpp=1 from the rsc is wrong.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 7 Jun 2018 17:54:15 +0000 (13:54 -0400)]
freedreno/ir3: fix image dimensions offset
copy-pasta fail from how SSBO sizes are handled.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 5 Jun 2018 13:50:26 +0000 (09:50 -0400)]
freedreno/a5xx: correct image/ssbo offset
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 4 Jun 2018 20:40:52 +0000 (16:40 -0400)]
freedreno/ir3: use saml always if we have lod
In some cases we get plain tex opcodes (but w/ a lod argument).. in this
case always use the saml instruction.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 4 Jun 2018 17:31:47 +0000 (13:31 -0400)]
freedreno/ir3: don't cp absneg into meta:fi
If using a fanin (collect) to collect of consecutive registers together,
we can CP mov's into the fanin, but not (abs) or (neg). No places that
allow those modifiers are consuming a fanin anyways. But this caused an
absneg to be lost between a ldgb and stgb for shaders like:
outputs[n] = abs(input[n])
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 26 Apr 2018 18:54:24 +0000 (14:54 -0400)]
freedreno/ir3: rework size/type conversion instructions
With 8b and 16b, there are a lot more to handle.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 26 Apr 2018 18:52:09 +0000 (14:52 -0400)]
freedreno/ir3: propagate HALF flag across fanout
If we have a fanout (split) meta instruction to split the result of a
vector instruction, propagate the HALF flag back to the original
instruction. Otherwise result ends up in a full precision register
while instruction(s) that use the result look in a half-precision
register.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 1 Jun 2018 18:56:57 +0000 (14:56 -0400)]
freedreno/a5xx: add sample-id/sample-mask-in
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 1 Jun 2018 18:56:38 +0000 (14:56 -0400)]
freedreno/ir3: add sample-id/sample-mask-in
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 1 Jun 2018 15:59:04 +0000 (11:59 -0400)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 31 May 2018 23:17:30 +0000 (19:17 -0400)]
freedreno/ir3: image atomics use image-store path
image reads are handled via tex state, whereas image writes and atomics
are handled via SSBO state block. Previously we were only considering
image write, and not image atomics which also uses the SSBO state block.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Kyle Brenneman [Wed, 6 Jun 2018 15:08:47 +0000 (09:08 -0600)]
egl/glvnd: Fix a segfault in eglGetProcAddress.
If FindProcIndex in egldispatchstubs.c is called with a name that's less than
the first entry in the array, it would end up trying to store an index of -1 in
an unsigned integer, wrap around to 2^32, and then crash when it tries to look
that up.
Change FindProcIndex so that it uses bsearch(3) instead of implementing its own
binary search, like the GLX equivalent FindGLXFunction does.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Jordan Justen [Wed, 6 Jun 2018 08:57:15 +0000 (01:57 -0700)]
mesa/program_binary: add implicit UseProgram after successful ProgramBinary
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106810
Fixes:
b4c37ce2140 "i965: Add ARB_get_program_binary support using nir_serialization"
Ref:
3fe8d04a6d6 "mesa: don't always set _NEW_PROGRAM when linking"
Ref:
c505d6d8522 "mesa: use gl_program for CurrentProgram rather than gl_shader_program"
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Dave Airlie [Mon, 11 Jun 2018 00:49:14 +0000 (10:49 +1000)]
features.txt: update virgl GL4.1 status.
All the features for GL4.1 are done (64-bit attribs were part of
the fp64 enable).
Once tessellation shaders land this will be advertised
Dave Airlie [Mon, 21 May 2018 04:00:37 +0000 (14:00 +1000)]
virgl: enable ARB_gpu_shader_fp64
This enables ARB_gpu_shader_fp64 if the host provides it.
Tested-by: Gurchetan Singh <gurchetansingh@chromium.org>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Samuel Pitoiset [Fri, 8 Jun 2018 09:38:01 +0000 (11:38 +0200)]
radv: add a workaround for DXVK hangs by setting amdgpu-skip-threshold
Workaround for bug in llvm that causes the GPU to hang in presence
of nested loops because there is an exec mask issue. The proper
solution is to fix LLVM but this might require a bunch of work.
This fixes a bunch of GPU hangs that happen with DXVK.
Vega10:
Totals from affected shaders:
SGPRS: 110456 -> 110456 (0.00 %)
VGPRS: 122800 -> 122800 (0.00 %)
Spilled SGPRs: 7478 -> 7478 (0.00 %)
Spilled VGPRs: 36 -> 36 (0.00 %)
Code Size: 9901104 -> 9922928 (0.22 %) bytes
Max Waves: 7143 -> 7143 (0.00 %)
Code size slightly increases because it inserts more branch
instructions but that's expected. I don't see any real performance
changes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105613
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 8 Jun 2018 15:59:49 +0000 (17:59 +0200)]
radv: fix missing ZRANGE_PRECISION(1) for GFX9+
ZRANGE_PRECISION(1) seems to be the default optimal value, but
it was only set for VI and older chips.
This fixes a rendering issue with Banished through DXVK, and
might fix more than that.
There is still the ZRANGE_PRECISION bug that we need to handle
but that can be fixed later.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Gustavo Lima Chaves [Tue, 20 Mar 2018 06:06:45 +0000 (23:06 -0700)]
anv: enable VK_EXT_shader_stencil_export
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Gustavo Lima Chaves [Mon, 12 Feb 2018 02:26:40 +0000 (18:26 -0800)]
spirv: add/hookup SpvCapabilityStencilExportEXT
v2:
An attempt to support SpvExecutionModeStencilRefReplacingEXT's behavior
also follows, with the interpretation to said mode being we prevent
writes to the built-in FragStencilRefEXT variable when the execution
mode isn't set.
v3:
A more cautious reading of
1db44252d01bf7539452ccc2b5210c74b8dcd573 led
me to a missing change that would stop (what I later discovered were)
GPU hangs on the CTS test written to exercise this.
v4:
Turn FragStencilRefEXT decoration usage without StencilRefReplacingEXT
mode into a warning, instead of trying to make the variable read-only.
If we are to follow the originating extension on GL, the built-in
variable in question should never be readable anyway.
v5/v6: rebases.
v7:
Fix check for gen9 lost in rebase. (Ilia)
Reduce the scope of the bool used to track whether
SpvExecutionModeStencilRefReplacingEXT was used. Was in shader_info,
moved to vtn_builder. (Jason)
v8:
Assert for fragment shader handling StencilRefReplacingEXT execution
mode. (Caio)
Remove warning logic, since an entry point might not have
StencilRefReplacingEXT execution mode, but the global output variable
might still exist for another entry point in the module. (Jason)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Anholt [Mon, 4 Jun 2018 22:32:14 +0000 (15:32 -0700)]
travis: Add the v3d driver to the automake build.
Hopefully this reduces the number of fixup commits we need for the
automake build.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Anholt [Tue, 5 Jun 2018 15:18:51 +0000 (08:18 -0700)]
travis: Do our automake build tests with srcdir != builddir.
This will catch many automake bugs that end-users get to experience first,
otherwise.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>