Simon Pilgrim [Sat, 1 Jun 2019 14:05:46 +0000 (14:05 +0000)]
[X86][AVX] Add tests for CONCAT(MOVDDUP(x),MOVDDUP(y))
llvm-svn: 362300
Simon Atanasyan [Sat, 1 Jun 2019 13:55:18 +0000 (13:55 +0000)]
[mips] Extend range of register indexes accepted by cfcmsa/ctcmsa
The `cfcmsa` and `ctcmsa` instructions accept index of MSA control
register. The MIPS64 SIMD Architecture define eight MSA control
registers. But register index for `cfcmsa` and `ctcmsa` instructions
might be any number in 0..31 range. If the index is greater then 7,
`cfcmsa` writes zero to the destination registers and `ctcmsa` does
nothing [1].
[1] MIPS Architecture for Programmers Volume IV-j:
The MIPS64 SIMD Architecture Module
https://www.mips.com/?do-download=the-mips64-simd-architecture-module
Differential Revision: https://reviews.llvm.org/D62597
llvm-svn: 362299
Dylan McKay [Sat, 1 Jun 2019 12:38:56 +0000 (12:38 +0000)]
[AVR] Disable register coalescing to the PTRDISPREGS class
If we would allow register coalescing on PTRDISPREGS class then register
allocator can lock Z register to some virtual register. Larger instructions
requiring a memory acces then fail during the register allocation phase since
there is no available register to hold a pointer if Y register was already
taken for a stack frame. This patch prevents it by keeping Z register
spillable. It does it by not allowing coalescer to lock it.
Original discussion on https://github.com/avr-rust/rust/issues/128.
llvm-svn: 362298
Simon Pilgrim [Sat, 1 Jun 2019 12:35:03 +0000 (12:35 +0000)]
[SLPVectorizer][X86] Add other tests described in PR28474
llvm-svn: 362297
Simon Pilgrim [Sat, 1 Jun 2019 12:10:29 +0000 (12:10 +0000)]
[SLPVectorizer][X86] This test was from PR28474
llvm-svn: 362296
Roman Lebedev [Sat, 1 Jun 2019 11:08:29 +0000 (11:08 +0000)]
[NFC][Codegen] shift-amount-mod.ll: drop innermost operation
I have initially added it in for test to display both
whether the binop w/ constant is sinked or hoisted.
But as it can be seen from the 'sub (sub C, %x), %y'
test, that actually conceals the issues it is supposed to test.
At least two more patterns are unhandled:
* 'add (sub C, %x), %y' - D62266
* 'sub (sub C, %x), %y'
llvm-svn: 362295
Fangrui Song [Sat, 1 Jun 2019 11:01:26 +0000 (11:01 +0000)]
[ELF][test] Reorganize some AArch64 tests
Delete aarch64-got.s because it is covered by aarch64-tls-iele.s
Merge got-aarch64.s into aarch64-fpic-got.s by adding disassembly to the latter
Create aarch64-gnu-ifunc-nonpreemptable to unify aarch64-gnu-ifunc3.s (position-dependent executable) and aarch64-gnu-ifunc-address-pie.s (PIE)
Rename aarch64-got-reloc.s to aarch64-got-weak-undef.s
Add --no-show-raw-insn to llvm-objdump -d RUN lines
Add -pie test to arch64-tls-iele.s
Delete aarch64-tls-pie.s: it is covered by arch64-tls-iele.s and aarch64-tls-le.s
Rename aarch64-copy2.s to aarch64-nopic-plt.s: "copy2" gives false impression that the test is related to copy relocation
llvm-svn: 362294
Nico Weber [Sat, 1 Jun 2019 10:12:07 +0000 (10:12 +0000)]
msabi: Fix exponential mangling time for certain pathological inputs
Template back references used to be recursively recomputed, add a
memoization cache to cut down on this.
Since there are now two different types of argument maps, rename the
existing TypeBackReferences to FunArgBackReferences, and rename
mangleArgumentType() to mangleFunctionArgumentType().
Fixes PR42091, the input there now takes 50ms instead of 7s to compile.
No intended behavior change.
Differential Revision: https://reviews.llvm.org/D62746
llvm-svn: 362293
Nikita Popov [Sat, 1 Jun 2019 09:40:18 +0000 (09:40 +0000)]
[IndVarSimplify] Fixup nowrap flags during LFTR (PR31181)
Fix for https://bugs.llvm.org/show_bug.cgi?id=31181 and partial fix
for LFTR poison handling issues in general.
When LFTR moves a condition from pre-inc to post-inc, it may now
depend on value that is poison due to nowrap flags. To avoid this,
we clear any nowrap flag that SCEV cannot prove for the post-inc
addrec.
Additionally, LFTR may switch to a different IV that is dynamically
dead and as such may be arbitrarily poison. This patch will correct
nowrap flags in some but not all cases where this happens. This is
related to the adoption of IR nowrap flags for the pre-inc addrec.
(See some of the switch_to_different_iv tests, where flags are not
dropped or insufficiently dropped.)
Finally, there are likely similar issues with the handling of GEP
inbounds, but we don't have a test case for this yet.
Differential Revision: https://reviews.llvm.org/D60935
llvm-svn: 362292
Nikita Popov [Sat, 1 Jun 2019 09:40:09 +0000 (09:40 +0000)]
[IndVarSimplify] Add additional PR33181 tests; NFC
Two more tests with a switch to a dynamically dead IV, with poison
occuring on the first or second iteration.
llvm-svn: 362291
Dylan McKay [Sat, 1 Jun 2019 09:18:26 +0000 (09:18 +0000)]
Extend the DWARFExpression address handling to support 16-bit addresses
This allows the DWARFExpression class to handle addresses without
crashing on targets with 16-bit pointers like AVR.
This is required in order to generate assembly from clang via the '-S'
flag.
This fixes an error with the following message:
clang: llvm/include/llvm/DebugInfo/DWARF/DWARFExpression.h:132: llvm::DWARFExpression::DWARFExpression(llvm::DataExtractor, uint16_t, uint8_t):
Assertion `AddressSize == 8 || AddressSize == 4' failed.
llvm-svn: 362290
Alex Brachet [Sat, 1 Jun 2019 07:36:57 +0000 (07:36 +0000)]
[llvm-objcopy] test commit
llvm-svn: 362289
Craig Topper [Sat, 1 Jun 2019 06:20:59 +0000 (06:20 +0000)]
[X86] Add AVX512BF16 and AVX512VP2INTERSECT instructions to the loading folding tables.
llvm-svn: 362288
Craig Topper [Sat, 1 Jun 2019 06:20:55 +0000 (06:20 +0000)]
[X86] Make the X86FoldTablesEmitter functional again. Fix the spacing in the output to make it easier to diff.
Fix a few other formatting issues in the manual table. And remove some
old FIXMEs.
llvm-svn: 362287
Nick Desaulniers [Sat, 1 Jun 2019 04:51:26 +0000 (04:51 +0000)]
[RuntimeDyld] fix too-small-bitmask error
Summary:
This was flagged in https://www.viva64.com/en/b/0629/ under "Snippet No.
33".
It seems that this statement is doing the standard bitwise trick for
adjusting a value to have a specific alignment.
The issue is that getStubAlignment() returns an unsigned, while DataSize
is declared a uint64_t. The right hand side of the expression is not
extended to 64b before bitwise negation, resulting in the top half of
the mask being 0s, which is not correct for realignment.
Reviewers: lhames, MaskRay
Reviewed By: MaskRay
Subscribers: RKSimon, MaskRay, hiraditya, llvm-commits, srhines
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62227
llvm-svn: 362286
Richard Trieu [Sat, 1 Jun 2019 03:32:20 +0000 (03:32 +0000)]
Inline variable into assert to fix unused variable warning.
llvm-svn: 362285
Philip Reames [Sat, 1 Jun 2019 03:09:28 +0000 (03:09 +0000)]
[LoopPred] Eliminate a redundant/confusing cover function [NFC]
llvm-svn: 362284
Tom Tan [Sat, 1 Jun 2019 02:38:08 +0000 (02:38 +0000)]
[COFF, ARM64] Fix location of ARM64 CodeView test
ARM64 CodeView test was incorrectly put under test/DebugInfo/COFF folder which
runs for all all architectures. This fix moves it to a subfolder AArch64 with
lit.local.cfg which specify it supports AArch64 only.
llvm-svn: 362283
Philip Reames [Sat, 1 Jun 2019 00:31:58 +0000 (00:31 +0000)]
[LoopPred] Handle a subset of NE comparison based latches
At the moment, LoopPredication completely bails out if it sees a latch of the form:
%cmp = icmp ne %iv, %N
br i1 %cmp, label %loop, label %exit
OR
%cmp = icmp ne %iv.next, %NPlus1
br i1 %cmp, label %loop, label %exit
This is unfortunate since this is exactly the form that LFTR likes to produce. So, go ahead and recognize simple cases where we can.
For pre-increment loops, we leverage the fact that LFTR likes canonical counters (i.e. those starting at zero) and a (presumed) range fact on RHS to discharge the check trivially.
For post-increment forms, the key insight is in remembering that LFTR had to insert a (N+1) for the RHS. CVP can hopefully prove that add nsw/nuw (if there's appropriate range on N to start with). This leaves us both with the post-inc IV and the RHS involving an nsw/nuw add, and SCEV can discharge that with no problem.
This does still need to be extended to handle non-one steps, or other harder patterns of variable (but range restricted) starting values. That'll come later.
Differential Revision: https://reviews.llvm.org/D62748
llvm-svn: 362282
Eli Friedman [Sat, 1 Jun 2019 00:08:54 +0000 (00:08 +0000)]
[CodeGen] Fix hashing for MO_ExternalSymbol MachineOperands.
We were hashing the string pointer, not the string, so two instructions
could be identical (isIdenticalTo), but have different hash codes.
This showed up as a very rare, non-deterministic assertion failure
rehashing a DenseMap constructed by MachineOutliner. So there's no
"real" testcase, just a unittest which checks that the hash function
behaves correctly.
I'm a little scared fixing this is going to cause a regression in
outlining or MachineCSE, but hopefully we won't run into any issues.
Differential Revision: https://reviews.llvm.org/D61975
llvm-svn: 362281
Tom Tan [Fri, 31 May 2019 23:43:31 +0000 (23:43 +0000)]
[COFF, ARM64] Add CodeView register mapping
CodeView has its own register map which is defined in cvconst.h. Missing this
mapping before saving register to CodeView causes debugger to show incorrect
value for all register based variables, like variables in register and local
variables addressed by register (stack pointer + offset).
This change added mapping between LLVM register and CodeView register so the
correct register number will be stored to CodeView/PDB, it aso fixed the
mapping from CodeView register number to register name based on current
CPUType but print PDB to yaml still assumes X86 CPU and needs to be fixed.
Differential Revision: https://reviews.llvm.org/D62608
llvm-svn: 362280
Stephane Moore [Fri, 31 May 2019 23:41:15 +0000 (23:41 +0000)]
Revise the google-objc-global-variable-declaration check to match the style guide.
Summary:
Revise the google-objc-global-variable-declaration check to match the style guide.
This commit updates the check as follows:
(1) Do not emit fixes for extern global constants.
(2) Allow the second character of prefixes for constants to be numeric (the new guideline is that global constants should generally be named with a prefix that begins with a capital letter followed by one or more capital letters or numbers).
https://google.github.io/styleguide/objcguide.html#prefixes
This is an amended re-submission of https://reviews.llvm.org/rG12e3726fadb0b2a4d8aeed0a2817b5159f9d029d.
Contributed By: yaqiji
Reviewers: Wizard, benhamilton, stephanemoore
Reviewed By: benhamilton, stephanemoore
Subscribers: mgorny, cfe-commits, yaqiji
Tags: #clang
Differential Revision: https://reviews.llvm.org/D62045
llvm-svn: 362279
Nick Desaulniers [Fri, 31 May 2019 23:02:13 +0000 (23:02 +0000)]
[PowerPC] check for INLINEASM_BR along w/ INLINEASM
Summary:
It looks like since INLINEASM_BR was created off of INLINEASM (r353563),
a few checks for INLINEASM needed to be updated to check for either
case.
pr/41999
Reviewers: hfinkel
Reviewed By: hfinkel
Subscribers: nemanjai, hiraditya, kbarton, jsji, llvm-commits, craig.topper, srhines
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62403
llvm-svn: 362278
Reid Kleckner [Fri, 31 May 2019 22:55:03 +0000 (22:55 +0000)]
[codeview] Revert inline line table change of r362264
Testing with debuggers shows that our previous behavior was correct.
The reason I thought MSVC did things differently is that MSVC prefers to
use the 0xB combined code offset and code length update opcode when
inline sites are discontiguous.
Keep the test changes, and update the llvm-pdbutil inline line table
dumper to account for this new interpretation of the opcodes.
llvm-svn: 362277
Sam Clegg [Fri, 31 May 2019 22:51:59 +0000 (22:51 +0000)]
[WebAssembly] Don't export __data_end and __heap_base by default.
These can still be exported via --export if needed.
Differential Revision: https://reviews.llvm.org/D62744
llvm-svn: 362276
Matt Arsenault [Fri, 31 May 2019 22:47:36 +0000 (22:47 +0000)]
AMDGPU: Fix not adding ImplicitBufferPtr as a live-in
Fixes missing test from r293000.
llvm-svn: 362275
Erik Pilkington [Fri, 31 May 2019 22:41:36 +0000 (22:41 +0000)]
[SimplifyLibCalls] Fold more fortified functions into non-fortified variants
When the object size argument is -1, no checking can be done, so calling the
_chk variant is unnecessary. We already did this for a bunch of these
functions.
rdar://
50797197
Differential revision: https://reviews.llvm.org/D62358
llvm-svn: 362272
Erik Pilkington [Fri, 31 May 2019 22:41:31 +0000 (22:41 +0000)]
NFC: Pull out a function to reduce some duplication
Part of https://reviews.llvm.org/D62358
llvm-svn: 362271
Philip Reames [Fri, 31 May 2019 22:22:29 +0000 (22:22 +0000)]
[Tests] Better represent the postinc form produced by LFTR in LoopPred tests
llvm-svn: 362270
Craig Topper [Fri, 31 May 2019 22:18:45 +0000 (22:18 +0000)]
[SelectionDAG] Make the code in mutateStrictFPToFP less aware of how many operands each node has. NFCI
Just copy all of the operands except the chain and call MorphNode on that.
This removes the IsUnary and IsTernary flags.
Also always get the result type from the result type of the original
nodes. Previously we got it from the operand except for two nodes
where that didn't work.
llvm-svn: 362269
Alex Langford [Fri, 31 May 2019 22:15:29 +0000 (22:15 +0000)]
[Commands] Stop hardcoding languages in CommandObjectType
llvm-svn: 362268
Nick Desaulniers [Fri, 31 May 2019 21:36:21 +0000 (21:36 +0000)]
[Bugpoint] fix another use-after-move. NFC
Summary:
This was flagged in https://www.viva64.com/en/b/0629/ under "Snippet No.
7".
These statements are order independent, short of the use-after-move.
Reviewers: echristo, srhines, RKSimon
Reviewed By: RKSimon
Subscribers: dblaikie, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62114
llvm-svn: 362267
Aaron Puchert [Fri, 31 May 2019 21:27:39 +0000 (21:27 +0000)]
Clarify when fix-it hints on warnings are appropriate
Summary:
This is not a change in the rules, it's meant as a clarification about
warnings. Since the recovery from warnings is a no-op, the fix-it hints
on warnings shouldn't change anything. Anything that doesn't just
suppress the warning and changes the meaning of the code (even if it's
for the better) should be on an additional note.
Reviewers: rsmith, aaron.ballman
Reviewed By: aaron.ballman
Subscribers: cfe-commits, thakis
Tags: #clang
Differential Revision: https://reviews.llvm.org/D62470
llvm-svn: 362266
Nick Desaulniers [Fri, 31 May 2019 21:20:13 +0000 (21:20 +0000)]
[RegisterCoalescer] fix potential use of undef value. NFC
Summary:
Fixes a warning produced from scan-build (llvm.org/reports/scan-build/),
further warnings found by annotation isMoveInstr [[nodiscard]].
isMoveInstr potentially does not assign to its parameters, so if they
were uninitialized, they will potentially stay uninitialized. It seems
most call sites pass references to uninitialized values, then use them
without checking the return value.
Reviewers: wmi
Reviewed By: wmi
Subscribers: MatzeB, qcolombet, hiraditya, tpr, llvm-commits, srhines
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62109
llvm-svn: 362265
Reid Kleckner [Fri, 31 May 2019 20:55:31 +0000 (20:55 +0000)]
[codeview] Fix inline line table accuracy for discontiguous segments
After improving the inline line table dumper in llvm-pdbutil and looking
at MSVC's inline line tables, it is clear that setting the length of the
inlined code region does not update the code offset. This means that the
delta to the beginning of a new discontiguous inlined code region should
be calculated relative to the last code offset, excluding the length.
Implementing this is a one line fix for MC: simply don't update
LastLabel.
While I'm updating these test cases, switch them to use llvm-objdump -d
and llvm-pdbutil. This allows us to show offsets of each instruction and
correlate the line table offsets to the actual code.
llvm-svn: 362264
Nikita Popov [Fri, 31 May 2019 20:48:26 +0000 (20:48 +0000)]
Reapply [CVP] Simplify non-overflowing saturating add/sub
If we can determine that a saturating add/sub will not overflow based
on range analysis, convert it into a simple binary operation. This is
a sibling transform to the existing with.overflow handling.
Reapplying this with an additional check that the saturating intrinsic
has integer type, as LVI currently does not support vector types.
Differential Revision: https://reviews.llvm.org/D62703
llvm-svn: 362263
Nikita Popov [Fri, 31 May 2019 20:42:13 +0000 (20:42 +0000)]
[CVP] Add vector saturating add test; NFC
Extra test for the assertion failure from D62703.
llvm-svn: 362262
Nikita Popov [Fri, 31 May 2019 20:42:07 +0000 (20:42 +0000)]
[CVP] Fix assertion failure on vector with.overflow
Noticed on D62703. LVI only handles plain integers, not vectors of
integers. This was previously not an issue, because vector support
for with.overflow is only a relatively recent addition.
llvm-svn: 362261
Philip Reames [Fri, 31 May 2019 20:34:57 +0000 (20:34 +0000)]
[Tests] Add ne icmp tests w/preinc forms for LoopPredication
Turns out this is substaintially easier to match then the post increment form, so let's start there.
llvm-svn: 362260
Alex Langford [Fri, 31 May 2019 20:17:21 +0000 (20:17 +0000)]
[Target] Remove ABI's dependence on ExpressionParser
llvm-svn: 362259
Michael Kruse [Fri, 31 May 2019 19:40:20 +0000 (19:40 +0000)]
[ScopBuilder] Move verifyInvariantLoads function from ScopInfo. NFC.
Refactor Scop and ScopBuilder class. Move verifyInvariantLoads from Scop
class to ScopBuilder class.
Patch by: Dominik Adamski <adamski.dominik@gmail.com>
Differential Revision: https://reviews.llvm.org/D62628
llvm-svn: 362258
Michael Kruse [Fri, 31 May 2019 19:26:57 +0000 (19:26 +0000)]
[ScheduleOptimizer] Hoist extension nodes after schedule optimization.
Extension nodes make schedule trees are less flexible: Many operations,
such as rescheduling, do not work on such schedule trees with extension.
As such, some functionality such as determining parallel loops in isl's
AST are disabled.
Currently, only the pattern-matching generalized matrix-matrix
multiplication optimization adds extension nodes (to add copy-in
statements).
This patch removes all extension nodes as the last step of the schedule
optimization by hoisting the extension node's added domain up to the
root domain node. All following passes can assume that schedule trees
work without restrictions, including the parallelism test. Mark the
outermost loop of the optimized matrix-matrix multiplication as parallel
such that -polly-parallel is able to parallelize that loop.
Differential Revision: https://reviews.llvm.org/D58202
llvm-svn: 362257
Craig Topper [Fri, 31 May 2019 19:18:07 +0000 (19:18 +0000)]
[X86] Resync Host.cpp with compiler-rt's cpu_model.c to enable 0x55 to be identified as cascadelake when avx512vnni is detected.
Some other formatting changes.
llvm-svn: 362256
Cameron McInally [Fri, 31 May 2019 19:12:59 +0000 (19:12 +0000)]
[NFC][InstCombine] Add unary FNeg tests to AMDGPU/amdgcn-intrinsics.ll
llvm-svn: 362255
Nikita Popov [Fri, 31 May 2019 19:04:47 +0000 (19:04 +0000)]
Revert "[CVP] Simplify non-overflowing saturating add/sub"
This reverts commit
1e692d1777ae34dcb93524b5798651a29defae09.
Causes assertion failure in builtins-wasm.c clang test.
llvm-svn: 362254
Cameron McInally [Fri, 31 May 2019 18:54:44 +0000 (18:54 +0000)]
[NFC][InstCombine] Add unary FNeg to cos-1.ll cos-2.ll cos-sin-intrinsic.ll
llvm-svn: 362253
Marshall Clow [Fri, 31 May 2019 18:35:30 +0000 (18:35 +0000)]
Add include for 'test_macros.h' to all the tests that were missing them. Thanks to Zoe for the (big, but simple) patch. NFC intended.
llvm-svn: 362252
Andrea Di Biagio [Fri, 31 May 2019 18:01:42 +0000 (18:01 +0000)]
[MCA] Remove unused fields from BottleneckAnalysis. NFC
This should appease the buildbots.
llvm-svn: 362251
Csaba Dabis [Fri, 31 May 2019 17:54:12 +0000 (17:54 +0000)]
[analyzer] print() JSONify: ExplodedNode revision
Summary: Revert node-ID removal.
Reviewers: NoQ, xazax.hun, ravikandhadai, baloghadamsoftware, Szelethus
Subscribers: szepet, rnkovacs, a.sidorin, mikhail.ramalho, donat.nagy, dkrupp,
cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D62658
llvm-svn: 362249
Chris Bieneman [Fri, 31 May 2019 17:40:49 +0000 (17:40 +0000)]
[CMake] Feed BUNDLE_PATH through llvm target wrappers
This feeds the new llvm_codsign BUNDLE_PATH option through from the llvm target wrapper functions, so that you can specify the BUNDLE_PATH on the target's codesign.
llvm-svn: 362248
Puyan Lotfi [Fri, 31 May 2019 17:34:25 +0000 (17:34 +0000)]
[MIR-Canon] Don't do vreg skip for independent instructions if there are none.
We don't want to create vregs if there is nothing to use them for. That causes
verifier errors.
Differential Revision: https://reviews.llvm.org/D62740
llvm-svn: 362247
Andrea Di Biagio [Fri, 31 May 2019 17:18:34 +0000 (17:18 +0000)]
[MCA] Refactor class BottleneckAnalysis. NFCI
The resource pressure distribution computation is now delegated by class
BottleneckAnalysis to an instance of class PressureTracker.
Class PressureTracker is also responsible for:
- tracking users of processor resource units.
- tracking the number of delay cycles caused by increases in backpressure.
BottleneckAnalysis internally initializes a dependency graph. Each nodes
represents an instruction in the input code sequence. Edges of the dependency
graph are critical register/memory/resource dependencies. Dependencies are only
added to the graph if they are seen as critical by backend pressure events.
The DependencyGraph is currently unused. It is possible to print the dependency
graph (see method DependencyGraph::dump()) for debugging purposes.
The long term goal is to use the information stored by the dependency graph in
order to do critical path computation.
llvm-svn: 362246
Erich Keane [Fri, 31 May 2019 17:00:48 +0000 (17:00 +0000)]
Replace 'default' in an enum-over-a-switch with the missing list.
This suppressed the Wswitch warning causing me to miss it and write an
assertion failure.
llvm-svn: 362245
Philip Reames [Fri, 31 May 2019 16:54:38 +0000 (16:54 +0000)]
[Tests] Add tests for loop predication of loops w/ne latch conditions
llvm-svn: 362244
Erich Keane [Fri, 31 May 2019 16:46:38 +0000 (16:46 +0000)]
Suppress nothrow/Exception spec conflict warning when we dont know the ES.
In any situation where the Exception Spec isn't clear, suppress the
warning to avoid false positives.
llvm-svn: 362243
Nikita Popov [Fri, 31 May 2019 16:46:05 +0000 (16:46 +0000)]
[CVP] Simplify non-overflowing saturating add/sub
If we can determine that a saturating add/sub will not overflow
based on range analysis, convert it into a simple binary operation.
This is a sibling transform to the existing with.overflow handling.
Differential Revision: https://reviews.llvm.org/D62703
llvm-svn: 362242
Kevin P. Neal [Fri, 31 May 2019 16:32:12 +0000 (16:32 +0000)]
Revert revert of r362112 with minor SystemZ test file corrections.
[FPEnv] Added a special UnrollVectorOp method to deal with the chain on StrictFP opcodes
This change creates UnrollVectorOp_StrictFP. The purpose of this is to address a failure that consistently occurs when calling StrictFP functions on vectors whose number of elements is 3 + 2n on most platforms, such as PowerPC or SystemZ. The old UnrollVectorOp method does not expect that the vector that it will unroll will have a chain, so it has an assert that prevents it from running if this is the case. This new StrictFP version of the method deals with the chain while unrolling the vector. With this new function in place during vector widending, llc can run vector-constrained-fp-intrinsics.ll for SystemZ successfully.
Submitted by: Drew Wock <drew.wock@sas.com>
Reviewed by: Cameron McInally, Kevin P. Neal
Approved by: Cameron McInally
Differential Revision: https://reviews.llvm.org/D62546
llvm-svn: 362241
Jonas Devlieghere [Fri, 31 May 2019 16:27:44 +0000 (16:27 +0000)]
[FormatEntity] Ignore ASCII escape sequences when colors are disabled.
This patch makes the FormatEntity honor the debugger's color settings by
not inserting ASCII escape sequences when colors are disabled.
Differential revision: https://reviews.llvm.org/D62714
llvm-svn: 362240
Stanislav Mekhanoshin [Fri, 31 May 2019 16:19:26 +0000 (16:19 +0000)]
[AMDGPU] Use InliningThresholdMultiplier for inline hint
AMDGPU uses multiplier 9 for the inline cost. It is taken into account
everywhere except for inline hint threshold. As a result we are penalizing
functions with the inline hint making them less probable to be inlined
than those without the hint. Defaults are 225 for a normal function and
325 for a function with an inline hint. Currently we have effective
threshold 225 * 9 = 2025 for normal functions and just 325 for those with
the hint. That is fixed by this patch.
Differential Revision: https://reviews.llvm.org/D62707
llvm-svn: 362239
Cameron McInally [Fri, 31 May 2019 16:17:04 +0000 (16:17 +0000)]
[NFC][InstCombine] Add unary FNeg tests to fabs.ll
llvm-svn: 362238
Guozhi Wei [Fri, 31 May 2019 16:11:17 +0000 (16:11 +0000)]
[PPC] Correctly adjust branch probability in PPCReduceCRLogicals
In PPCReduceCRLogicals after splitting the original MBB into 2, the 2 impacted branches still use original branch probability. This is unreasonable. Suppose we have following code, and the probability of each successor is 50%.
condc = conda || condb
br condc, label %target, label %fallthrough
It can be transformed to following,
br conda, label %target, label %newbb
newbb:
br condb, label %target, label %fallthrough
Since each branch has a probability of 50% to each successor, the total probability to %fallthrough is 25% now, and the total probability to %target is 75%. This actually changed the original profiling data. A more reasonable probability can be set to 70% to the false side for each branch instruction, so the total probability to %fallthrough is close to 50%.
This patch assumes the branch target with two incoming edges have same edge frequency and computes new probability fore each target, and keep the total probability to original targets unchanged.
Differential Revision: https://reviews.llvm.org/D62430
llvm-svn: 362237
Erich Keane [Fri, 31 May 2019 15:56:27 +0000 (15:56 +0000)]
Suppress nothrow/exception spec conflict warning when ES is parsed.
The previously added warning ended up causing false positives when
nothrow was used on member functions, where the exception specification
wasn't yet parsed. So, throw() and noexcept(true) both were incorrectly
warning. There doesn't seem to be a good way to force these to be parsed
to identify which they are (and likely should not be), so suppress the warning.
For now, unevaluated/uninstantiated are left as warnings as I am not
creative enough to find a reproducer that causes a false positive for
either.
llvm-svn: 362236
Fangrui Song [Fri, 31 May 2019 15:41:19 +0000 (15:41 +0000)]
[PPC64][test] Delete redundant labels from ppc64-relocs.s
llvm-svn: 362235
Cameron McInally [Fri, 31 May 2019 15:40:03 +0000 (15:40 +0000)]
[NFC][InstCombine] Add unary FNeg tests to fcmp.ll
llvm-svn: 362234
Jinsong Ji [Fri, 31 May 2019 15:35:19 +0000 (15:35 +0000)]
[MachinePipeliner][NFC] Add some debug log and statistics
This is to add some log and statistics for debugging
Differential Revision: https://reviews.llvm.org/D62165
llvm-svn: 362233
Michael Liao [Fri, 31 May 2019 15:29:55 +0000 (15:29 +0000)]
Revise test case due to the change from CUDA 10+.
llvm-svn: 362232
Cameron McInally [Fri, 31 May 2019 15:10:34 +0000 (15:10 +0000)]
[NFC][InstCombine] Add unary FNeg tests to fdiv.ll
llvm-svn: 362231
Simon Pilgrim [Fri, 31 May 2019 15:06:51 +0000 (15:06 +0000)]
[AMDGPU] Regenerate add/sub shrink constant tests for an upcoming patch
llvm-svn: 362230
Simon Pilgrim [Fri, 31 May 2019 15:06:14 +0000 (15:06 +0000)]
[AMDGPU] Regenerate CTLZ tests for an upcoming patch
llvm-svn: 362229
Simon Pilgrim [Fri, 31 May 2019 15:05:06 +0000 (15:05 +0000)]
[UpdateTestChecks] Add support for -march=r600 to match existing -march=amdgcn support
llvm-svn: 362228
Cameron McInally [Fri, 31 May 2019 14:49:31 +0000 (14:49 +0000)]
[NFC][InstCombine] Add unary FNeg tests to fma.ll
llvm-svn: 362227
Haojian Wu [Fri, 31 May 2019 14:38:16 +0000 (14:38 +0000)]
[clangd] Add missing license for rename.cpp, NFC.
llvm-svn: 362226
Erich Keane [Fri, 31 May 2019 14:26:19 +0000 (14:26 +0000)]
Fix for PR42089, regression from r362119
The implementation of the NoThrow ExceptionSpecificationType missed a
switch statement for forming the diagnostic when an out-of-line member
redeclaration misses the exception specification. This patch adds the
correct case statement.
llvm-svn: 362225
George Rimar [Fri, 31 May 2019 13:16:21 +0000 (13:16 +0000)]
[llvm-readobj] - Remove excessive `dynamic.test`
dynamic.test is a test that checks dumping of
dynamic tags. It uses precompiled objects as inputs
and it is completely excessive nowadays:
Now we have elf-dynamic-tags-machine-specific.test
and elf-dynamic-tags.test.
(https://github.com/llvm-mirror/llvm/blob/master/test/tools/llvm-readobj/elf-dynamic-tags-machine-specific.test)
(https://github.com/llvm-mirror/llvm/blob/master/test/tools/llvm-readobj/elf-dynamic-tags.test)
First is used to check target specific tags and second tests the common flags.
These tests use YAML, which is much better than using precompiled binaries.
Note that new reviews tend to update the YAML based
tests to add new tags, e.g. see D62596.
With this patch it became possible to remove
dynamic-table-so.aarch64 binary from the inputs folder.
(other binaries are still used in other tests).
Differential revision: https://reviews.llvm.org/D62728
llvm-svn: 362224
Nico Weber [Fri, 31 May 2019 12:07:05 +0000 (12:07 +0000)]
gn build: Merge r362160
llvm-svn: 362223
Nico Weber [Fri, 31 May 2019 11:52:59 +0000 (11:52 +0000)]
gn build: Merge r362196
llvm-svn: 362222
Nico Weber [Fri, 31 May 2019 11:51:42 +0000 (11:51 +0000)]
gn build: Merge r362190
llvm-svn: 362221
Fangrui Song [Fri, 31 May 2019 10:35:45 +0000 (10:35 +0000)]
[ELF] Delete GotEntrySize and GotPltEntrySize
GotEntrySize and GotPltEntrySize were added in D22288. Later, with
the introduction of wordsize() (then Config->Wordsize), they become
redundant, because there is no target that sets GotEntrySize or
GotPltEntrySize to a number different from Config->Wordsize.
Reviewed By: grimar, ruiu
Differential Revision: https://reviews.llvm.org/D62727
llvm-svn: 362220
Russell Gallop [Fri, 31 May 2019 10:14:04 +0000 (10:14 +0000)]
ftime-trace: Trace loop passes
These can take a significant amount of time in some builds.
Suggested by Andrea Di Biagio.
Differential Revision: https://reviews.llvm.org/D62666
llvm-svn: 362219
Fangrui Song [Fri, 31 May 2019 10:12:22 +0000 (10:12 +0000)]
[ELF] Replace a dead test in getSymVA() with assert()
Symbols relative to discarded comdat sections are Undefined instead of
Defined now (after D59649 and D61583). The `== &InputSection::Discarded`
test becomes dead. I cannot find a test related to this behavior.
Reviewed By: ruiu
Differential Revision: https://reviews.llvm.org/D62725
llvm-svn: 362218
Roman Lebedev [Fri, 31 May 2019 09:47:16 +0000 (09:47 +0000)]
[InstCombine] 'C-(C2-X) --> X+(C-C2)' constant-fold
It looks this fold was already partially happening, indirectly
via some other folds, but with one-use limitation.
No other fold here has that restriction.
https://rise4fun.com/Alive/ftR
llvm-svn: 362217
Roman Lebedev [Fri, 31 May 2019 09:47:04 +0000 (09:47 +0000)]
[InstCombine] 'add (sub C1, X), C2 --> sub (add C1, C2), X' constant-fold
https://rise4fun.com/Alive/qJQ
llvm-svn: 362216
Cullen Rhodes [Fri, 31 May 2019 09:13:55 +0000 (09:13 +0000)]
[AArch64][SVE2] Asm: support WHILE instructions
Summary:
Patch adds support for the following instructions:
* WHILEGE, WHILEGT, WHILEHS, WHILEHI, WHILEWR, WHILERW
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: chill
Differential Revision: https://reviews.llvm.org/D62601
llvm-svn: 362215
Cullen Rhodes [Fri, 31 May 2019 09:06:53 +0000 (09:06 +0000)]
[AArch64][SVE2] Asm: support TBL/TBX instructions
Summary:
A three sources variant of the TBL instruction is added to the existing
SVE instruction in SVE2. This is implemented with minor changes to the
existing TableGen class. TBX is a new instruction with its own
definition.
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: chill
Differential Revision: https://reviews.llvm.org/D62600
llvm-svn: 362214
Cullen Rhodes [Fri, 31 May 2019 08:59:40 +0000 (08:59 +0000)]
[AArch64][SVE2] Asm: support SVE2 store instructions
Summary:
Patch adds support for the following instructions:
* STNT1B, STNT1H, STNT1S, STNT1D
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: chill
Differential Revision: https://reviews.llvm.org/D62599
llvm-svn: 362213
Petar Avramovic [Fri, 31 May 2019 08:40:08 +0000 (08:40 +0000)]
[MIPS GlobalISel] Add detailed tests for lower call
Test different operand types of callee and their behavior whether
relocation model is pic or not.
Possible operand types are:
Register (function pointer),
External symbol (used for libcalls e.g. __udivdi3 or memcpy),
Global address.
Global address has different handling depending on relocation model
and linkage type. Register and external symbol do not.
Differential Revision: https://reviews.llvm.org/D62590
llvm-svn: 362212
Sjoerd Meijer [Fri, 31 May 2019 08:39:34 +0000 (08:39 +0000)]
Follow up and fix for rL362064
Fix the misleadingly indentation introduced in rL362064. This will get rid of
the compiler warning, and it was actually a bug. This change will be used and
tested in D62669.
llvm-svn: 362211
Petar Avramovic [Fri, 31 May 2019 08:27:06 +0000 (08:27 +0000)]
[MIPS GlobalISel] Handle position independent code
Handle position independent code for MIPS32.
When callee is global address, lower call will emit callee
as G_GLOBAL_VALUE and add target flag if needed.
Support $gp in getRegBankFromRegClass().
Select G_GLOBAL_VALUE, specially handle case when
there are target flags attached by lowerCall.
Differential Revision: https://reviews.llvm.org/D62589
llvm-svn: 362210
Roman Lebedev [Fri, 31 May 2019 08:24:07 +0000 (08:24 +0000)]
[NFC][InstCombine] Copy add/sub constant-folding tests from codegen
Last three patterns are missed.
llvm-svn: 362209
Roman Lebedev [Fri, 31 May 2019 08:23:48 +0000 (08:23 +0000)]
[NFC][Codegen] Add/sub constant-folding: add scalar tests too
Just for completeness.
llvm-svn: 362208
Fangrui Song [Fri, 31 May 2019 08:20:43 +0000 (08:20 +0000)]
[ELF][test] Restore linkerscript/symbol-location.s to test getLinkerScriptLocation()
The test (the only test that checks getLinkerScriptLocation()) deleted
by r358652 can be restored by replacing R_X86_64_PLT32 with
R_X86_64_PC32, and changing -pie to -shared (preemptable). Then, the
symbol will not be a link-time constant and a -fPIC error will be
issued.
llvm-svn: 362207
Petar Avramovic [Fri, 31 May 2019 08:15:28 +0000 (08:15 +0000)]
[mips] Move initGlobalBaseReg to MipsFunctionInfo. NFC
Move initGlobalBaseReg from MipsSEDAGToDAGISel to MipsFunctionInfo.
This way functions used for handling position independent code during
instruction selection, getGlobalBaseReg and initGlobalBaseReg,
end up in same class.
Differential Revision: https://reviews.llvm.org/D62586
llvm-svn: 362206
Craig Topper [Fri, 31 May 2019 08:10:23 +0000 (08:10 +0000)]
[InstructionSimplify] Add missing implementation of llvm::SimplifyUnOp. NFC
There are no callers currently, but the function is declared so we should at
least implement it.
llvm-svn: 362205
Petar Avramovic [Fri, 31 May 2019 08:06:17 +0000 (08:06 +0000)]
[MIPS GlobalISel] Lower call for callee that is register
Lower call for callee that is register for MIPS32.
Register should contain callee function address.
Differential Revision: https://reviews.llvm.org/D62585
llvm-svn: 362204
Craig Topper [Fri, 31 May 2019 07:38:26 +0000 (07:38 +0000)]
[X86] Remove patterns for X86VSintToFP/X86VUintToFP+loadv4f32 to v2f64.
These patterns can incorrectly narrow a volatile load from 128-bits to 64-bits.
Similar to PR42079.
Switch to using (v4i32 (bitcast (v2i64 (scalar_to_vector (loadi64))))) as the
load pattern used in the instructions.
This probably still has issues in 32-bit mode where loadi64 isn't legal. Maybe
we should use VZMOVL for widened loads even when we don't need the upper bits
as zeroes?
llvm-svn: 362203
Craig Topper [Fri, 31 May 2019 07:38:22 +0000 (07:38 +0000)]
[X86] Add test cases for failure to use 128-bit masked vcvtdq2pd when load starts as v2i32.
llvm-svn: 362202
Craig Topper [Fri, 31 May 2019 07:38:18 +0000 (07:38 +0000)]
[X86] Add test cases for a volatile load shrinking bug involving cvtdq2pd. NFC
Similar to PR42079
llvm-svn: 362201
Craig Topper [Fri, 31 May 2019 07:38:14 +0000 (07:38 +0000)]
[X86] Copy a test case from avx512-cvt.ll to avx512-cvt-widen.ll. NFC
llvm-svn: 362200
Craig Topper [Fri, 31 May 2019 06:21:53 +0000 (06:21 +0000)]
[X86] Remove avx512 isel patterns for fpextend+load. Prefer to only match fp extloads instead.
DAG combine will usually fold fpextend+load to an fp extload anyway. So the
256 and 512 patterns were probably unnecessary. The 128 bit pattern was special
in that it looked for a v4f32 load, but then used it in an instruction that
only loads 64-bits. This is bad if the load happens to be volatile. We could
probably make the patterns volatile aware, but that's more work for something
that's probably rare. The peephole pass might kick in and save us anyway. We
might also be able to fix this with some additional DAG combines.
This also adds patterns for vselect+extload to enabled masked vcvtps2pd to be
used. Previously we looked for the unlikely vselect+fpextend+load.
llvm-svn: 362199
Craig Topper [Fri, 31 May 2019 06:21:49 +0000 (06:21 +0000)]
[X86] Add test to show missed opportunity to use masked vcvtps2pd for vselect+extload.
llvm-svn: 362198