aco: fix fp16 *0.5 omod

We were testing for -0.5 instead.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: 1210e0bd620 ("aco: create 16-bit input and output modifiers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7605>

aco: disable omod if the sign of zeros should be preserved

The RDNA ISA doc says that omod doesn't preserve -0.0 in 6.2.2. LLVM
appears to always disable omod in this situation, but clamp is unaffected.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: df645fa369d ("aco: implement VK_KHR_shader_float_controls")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7605>

Revert "ci: Temporarily disable jobs on the Collabora lab"

Lab is back online now.

This reverts commit 902ac3d7c5ab75f2ff31bf23d1d5add7b5c377ed.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7630>

nir: don't consider txf_ms_mcs a query instruction

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6172>

util: fix unknown pragma warning on msvc

MSVC has no idea about these pragmas, and spews warnings about them,
making it hard to spot real problems. So let's only use these macros on
GCC.

Fixes: 2ec290cd92a ("util: Fix/silence variable shadowing warnings")
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7633>

aco: remove v_{add,sub,subrev}_u32 on GFX8

These opcodes are never used and they always write the carry-out
according to the GCN3 ISA documentation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7569>

microsoft/compiler: Fix reference to renamed intrinsic getter

Fixes: b9c61379 ("microsoft/compiler: translate nir to dxil")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7609>

util: Fix/silence variable shadowing warnings

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7552>

glsl: Fix -Wshadow warning

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7552>

ci: Temporarily disable jobs on the Collabora lab

There's a maintenance window of 4 hours to improve the lab
infrastructure.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7629>

iris: initialize shared screen->vtbl only once

Screen is shared among contexts, other context might be already using
vtbl while another initializes it again.

 ==45872== Possible data race during write of size 8 at 0x5DDAE78 by thread #549
 ==45872== Locks held: 1, at address 0x5D1B6F8
 ==45872==    at 0x6D66D91: gen9_init_state (iris_state.c:7816)
 ==45872==    by 0x6BA0A31: iris_create_context (iris_context.c:342)
 ==45872==    by 0x621F390: st_api_create_context (st_manager.c:917)
 ==45872==    by 0x620E6F9: dri_create_context (dri_context.c:163)
 ==45872==    by 0x6A40DB1: driCreateContextAttribs (dri_util.c:480)
 ==45872==    by 0x540B963: dri2_create_context (egl_dri2.c:1583)
 ==45872==    by 0x53FB84E: eglCreateContext (eglapi.c:821)
 ==45872==
 ==45872== This conflicts with a previous read of size 8 by thread #544
 ==45872== Locks held: 1, at address 0x5F6E0E0
 ==45872==    at 0x6CB779E: blorp_alloc_binding_table (iris_blorp.c:167)
 ==45872==    by 0x6CAEF70: blorp_emit_surface_states (blorp_genX_exec.h:1540)
 ==45872==    by 0x6CB67F9: blorp_exec (blorp_genX_exec.h:2016)
 ==45872==    by 0x6CB7AFE: iris_blorp_exec (iris_blorp.c:307)
 ==45872==    by 0x70F5916: try_blorp_blit (blorp_blit.c:2145)
 ==45872==    by 0x70F5FCA: do_blorp_blit (blorp_blit.c:2273)
 ==45872==    by 0x70F778F: blorp_copy (blorp_blit.c:2803)
 ==45872==    by 0x6BB9EB6: iris_copy_region (iris_blit.c:725)

v2: move as genX(init_screen_state) (Lionel)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7544>

egl/dri2: fix race between image create and egl_image_target_texture

All other functions calling _eglLookupImage hold the display lock.

 ==16659== Possible data race during write of size 8 at 0x5D1BCF0 by thread #2668
 ==16659== Locks held: 1, at address 0x5D1B6F8
 ==16659==    at 0x5405DDF: _eglLinkResource (egldisplay.c:454)
 ==16659==    by 0x53F9189: _eglLinkImage (eglimage.h:138)
 ==16659==    by 0x53FE2CA: _eglCreateImageCommon (eglapi.c:1740)
 ==16659==    by 0x53FE39A: eglCreateImageKHR (eglapi.c:1751)
 ==16659==
 ==16659== This conflicts with a previous read of size 8 by thread #2664
 ==16659== Locks held: 1, at address 0x5308D00
 ==16659==    at 0x5405C06: _eglCheckResource (egldisplay.c:387)
 ==16659==    by 0x5408C92: _eglLookupImage (eglimage.h:162)
 ==16659==    by 0x5409E96: dri2_lookup_egl_image (egl_dri2.c:688)
 ==16659==    by 0x6210AAF: dri2_lookup_egl_image (dri_helpers.c:250)
 ==16659==    by 0x6212843: dri_get_egl_image (dri_screen.c:470)
 ==16659==    by 0x625F7CC: st_get_egl_image (st_cb_eglimage.c:152)
 ==16659==    by 0x625FE7D: st_egl_image_target_texture_2d (st_cb_eglimage.c:354)
 ==16659==    by 0x6501C05: egl_image_target_texture (teximage.c:3446)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7544>

lima: define set_clip_state implementation

In applications using clip planes, set_clip_state is expected to be
implemented in the backend. If it is not defined, it may cause the
application to segfault.

glClipPlane it is not part of GLES 2, so it is not trivial to reverse
engineer if something needs to be done in lima.
Other drivers just define a placeholder implementation for
set_clip_state, so for now let's just define one for lima too.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7088>

gallivm: fix float atomic exchange.

for atomic exchange floats are valid.

Fixes CL CTS test_atomic fails

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7595>

gallivm: lower vector compares

This lowers the any/all stuff.

Fixes unknown opcode in
./relationals/test_relationals

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7595>

gallivm/nir: lower dot products.

The nir lowering should suffice

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7595>

gallivm/nir: add fsum support

This is needed for lowered dot products, this opcode just
sums all the vector elements.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7595>

gallivm: add float to 8/16 int

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7595>

draw: fix tess eval pipeline statistics.

The number of invocations wasn't getting incremented correctly.

Fixes: 202bc38ce9e3 ("draw: collect tessellation invocations statistics")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7597>

ci: update the list of expected failures for RADV

Against vulkan-cts-1.2.4.1.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7626>

ci: update the list of skipped tests for RAVEN

The list of default skipped tests should also be included.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7626>

radv: Use internal drm_fourcc.h

Fixes: 0833dd7d124 "amd/common: Add support for modifiers."
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3794
̀Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7619>

etnaviv: nir: do not run opt loop after nir_lower_bool_xxx(..)

Running the optimizations after bool to float/int lowering is not going
to work. Large portions of NIR are likely to blow up if they see
floats/ints in weird places. Most of the bool->float/int conversions
are direct instruction substitutions and it's not going to leave a lot
of garbage around to optimize.

Fixes nir.h:261: nir_const_value_as_bool: Assertion `i == 0 || i == -1' failed
dEQP-GLES2.functional.shaders.loops.while_constant_iterations.no_iterations_vertex

Here are shader-db results for GC2000:

instructions HURT:   shaders/tesseract/488.shader_test FRAG:           516 -> 524 (1.55%)
instructions HURT:   shaders/tesseract/491.shader_test FRAG:           248 -> 260 (4.84%)
instructions HURT:   shaders/tesseract/494.shader_test FRAG:           244 -> 256 (4.92%)
instructions HURT:   shaders/tesseract/238.shader_test FRAG:           232 -> 244 (5.17%)
instructions HURT:   shaders/tesseract/241.shader_test FRAG:           232 -> 244 (5.17%)
instructions HURT:   shaders/tesseract/127.shader_test FRAG:           76 -> 80 (5.26%)
instructions HURT:   shaders/tesseract/130.shader_test FRAG:           148 -> 156 (5.41%)
instructions HURT:   shaders/tesseract/226.shader_test FRAG:           192 -> 204 (6.25%)
instructions HURT:   shaders/tesseract/229.shader_test FRAG:           192 -> 204 (6.25%)
instructions HURT:   shaders/tesseract/217.shader_test FRAG:           152 -> 164 (7.89%)
instructions HURT:   shaders/tesseract/214.shader_test FRAG:           152 -> 164 (7.89%)
instructions HURT:   shaders/tesseract/205.shader_test FRAG:           112 -> 124 (10.71%)
instructions HURT:   shaders/tesseract/202.shader_test FRAG:           112 -> 124 (10.71%)
instructions HURT:   shaders/tesseract/169.shader_test FRAG:           32 -> 36 (12.50%)
instructions HURT:   shaders/tesseract/166.shader_test FRAG:           32 -> 36 (12.50%)
instructions HURT:   shaders/deqp_gles3/61312.shader_test FRAG:        448 -> 508 (13.39%)
instructions HURT:   shaders/deqp_gles3/61309.shader_test FRAG:        448 -> 508 (13.39%)
instructions HURT:   shaders/deqp_gles3/61324.shader_test FRAG:        448 -> 508 (13.39%)
instructions HURT:   shaders/tesseract/118.shader_test FRAG:           28 -> 32 (14.29%)
instructions HURT:   shaders/tesseract/181.shader_test FRAG:           52 -> 60 (15.38%)
instructions HURT:   shaders/tesseract/178.shader_test FRAG:           52 -> 60 (15.38%)
instructions HURT:   shaders/tesseract/121.shader_test FRAG:           52 -> 60 (15.38%)
instructions HURT:   shaders/tesseract/193.shader_test FRAG:           72 -> 84 (16.67%)
instructions HURT:   shaders/tesseract/190.shader_test FRAG:           72 -> 84 (16.67%)

total instructions in shared programs: 64220 -> 64572 (0.55%)
instructions in affected programs: 4924 -> 5276 (7.15%)
helped: 5
HURT: 24
helped stats (abs) min: 4 max: 8 x̄: 5.60 x̃: 4
helped stats (rel) min: 4.35% max: 5.41% x̄: 4.72% x̃: 4.35%
HURT stats (abs)   min: 4 max: 60 x̄: 15.83 x̃: 12
HURT stats (rel)   min: 1.55% max: 16.67% x̄: 10.04% x̃: 10.71%
95% mean confidence interval for instructions value: 5.39 18.89
95% mean confidence interval for instructions %-change: 4.81% 10.18%
Instructions are HURT.

total temps in shared programs: 2514 -> 2512 (-0.08%)
temps in affected programs: 9 -> 7 (-22.22%)
helped: 2
HURT: 0

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7624>

v3dv/pipeline: take into account precision for the output_type

By default we are using 32bit output type for texture operations,
16bit for shadow.

With this commit we also use the precision info from the sampler (that
is assigned if SPIR-V uses RelaxedPrecision decorator), in order to
use 16bit.

This is a first step as only take into account the precision of the
deref_vars used on the texture operation.

But the decoration can be also applied to other cases, like the result
of the operation. That means that there are ways to infer that the
texture operation can operate at relaxed precision. Those cases would
be handled on following patches.

v2:
    * Add directly the return_size on the descriptor_map, instead of
      shadow/relaxed_precision.
    * Check relaxed precision for images too (Iago)
    * Handle the return size for the default sampler

v3:
    * Handle different output size for the case of not having a sampler.
    * Comment fixes (Iago)

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7545>

v3dv: remove combined_idx support

Now that the v3d compiler has support for separated texture and
sampler indices, we can stop to combine them. Again, that's what
Vulkan allows after all.

As we are doing this we can't use anymore the texture format (coming
from the texture) to chose the return size (that is a sampling
parameter). We default for 32, and just go to 16 for shadow. We plan
to use SPIR-V RelaxedPrecision to use in more cases 16 bit. We would
do that on following patches.

v2 (from Iago feedback):
   * Fix typos/bad grammar on comments.
   * Move tex/sampler number assert to before the loop that fills
     tex/sampler info.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7545>

broadcom/compiler: separate texture/sampler info from v3d_key

So far the v3d compiler has them combined, as for OpenGL both are the
same. This change is intended to fit the v3d compiler better with
Vulkan, where they are separate concepts.

Note that NIR has them separate for a long time, both on nir_variable
and on some NIR lowerings.

v2: (from Iago feedback)
    * Use key->num_tex/sampler_used to iterate through the array
    * Fill up num_samplers_used on v3d, assert that is the same that
      num_tex_used if possible.

v3: (Iago)
    * Assert num_tex/samplers_used is smaller that tex/sampler array size.

v4: Update assert mentioned on v3 to use <= instead of < (detected by CI)

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
squash! broadcom/compiler: separate texture/sampler info from v3d_key

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7545>

v3dv: cleanup/remove support for pre-generated variants

In preparation to the changes that would allow to not need them.

It is worth to note that it is likely (we have some ideas in mind)
that we would need to bring back pre-generate variants on the
future. The approach is slightly different on v3dv_pipeline vs
v3dv_cmd_buffer:

  * v3dv_pipeline: even after the clean-up, we had code for all the
    functions they have, even if they were doing less things
    (specifically, a second shader variant), so they still make sense
    on their own, and serve as template for adding support of multiple
    pre-generated shader variants in the future.

  * v3dv_cmd_buffer: as we really don't need to fill up the key with
    some after-pipeline data, we would end with some functions empty
    (specifically cmd_buffer_populate_v3d_key). Even as a placeholder,
    that would be odd. Additionally the current code has a lot of
    boilerplate code (functions to fill up vs, cs and fs keys are
    basically the same), and we already have in mind refactor them. So
    it would be better to remove all of them, instead of keeping
    around some code we would not be happy with. If in the future we
    pregenerate more that one variant, hopefully the new code to chose
    between them would be better.

v2: clarify the commit message, and fix typos on the comments (Iago)

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7545>

nir/lower_tex: clarify nir_lower_tex_options indexing

This doesn't matter too much on OpenGL as texture id and sampler id
are the same, but become relevant if using the lowering for Vulkan.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7545>

drm/uapi: Fix modifier field mask for AMD modifiers.

The DCC_MAX_COMPRESSED_BLOCK has to contain one of
AMD_FMT_MOD_DCC_BLOCK_* and with 3 values this doesn't
fit in 1 bit.

Fix this cleanly while it is only in drm-next.

Fixes: 2cc2b456889 "drm-uapi: Add AMD modifiers."
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7607>

v3dv: Remove unsigned comparison to zero.

index is of type uint32_t.

Fix defects reported by Coverity Scan.

Macro compares unsigned to 0 (NO_EFFECT)
unsigned_compare: This greater-than-or-equal-to-zero comparison of
an unsigned value is always true. index >= 0U.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7518>

vdpau: Add missing printf format specifier.

Fix defect reported by Coverity Scan.

Extra argument to printf format specifier (PRINTF_ARGS)
extra_argument: This argument was not used by the format string: vmixer->max_layers.

Fixes: 89b986325227 ("vdpau: Add support for parameters")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7200>

nvir/gm107: Initialize SchedDataCalculatorGM107 member score.

Fix defect reported by Coverity Scan.

Uninitialized pointer field (UNINIT_CTOR)
uninit_member: Non-static class member score is not initialized in
this constructor nor in any functions that it calls.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7324>

freedreno/ir3: Fix crash in shader compile fail path

Fixes: 74140c2e859 ("freedreno/ir3: convert over to ralloc")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7612>

freedreno/ir3: Add pass to deal with load_uniform base offsets

With indirect load_uniform, we can only encode 10b of constant base
offset.  This pass detects problematic cases and peels out the high
bits of the base offset.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7612>

intel/blorp: Delete clear color conversions during copies

With the last commit, there are no more users of this code.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5388>

i965: Disable color fast-clears for miptree copy

During a blorp_copy between two color surfaces, the source and
destination formats are re-interpreted to UINT (if possible) to avoid
losing bits.

If either surface has CCS_E, then extra steps are taken to support
fast-cleared blocks with this format re-interpretation. Each clear value
is packed in the original format, then unpacked in the new UINT format.
This is then placed into the surface state object for some platforms.
There are couple problems here:

1. This is only being done for CCS_E, but MCS also supports fast-clears.

2. These steps aren't enough for fast-clears on gen11. On gen11, the
   clear color isn't part of the surface state object that BLORP
   creates. Instead it's stored in a separate BO, that the surface state
   object references. Since that BO doesn't get updated during
   blorp_copy, the incorrect/unconverted clear color is used for the copy
   operation.

I didn't measure any performance gain from this code, so this patch
simply disables the feature.

Makes i965 pass the nv_copy_image-simple piglit test on gen11.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5388>

iris: Disable color fast-clears in iris_copy_region

During a blorp_copy between two color surfaces, the source and
destination formats are re-interpreted to UINT (if possible) to avoid
losing bits.

If either surface has CCS_E, then extra steps are taken to support
fast-cleared blocks with this format re-interpretation. Each clear value
is packed in the original format, then unpacked in the new UINT format.
This is then placed into the surface state object for some platforms.
There are couple problems here:

1. This is only being done for CCS_E, but MCS also supports fast-clears.

2. These steps aren't enough for fast-clears on gen11+. On gen11+, the
   clear color isn't part of the surface state object that BLORP
   creates. Instead it's stored in a separate BO, that the surface state
   object references. Since that BO doesn't get updated during
   blorp_copy, the incorrect/unconverted clear color is used for the copy
   operation.

I didn't measure any performance gain from this code, so this patch
simply disables the feature.

Makes iris pass the nv_copy_image-simple piglit test on gen11+.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5388>

panfrost: Fix stack shift calculation

Fixes flickering in Neverwinter Nights.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3789
Fixes: e6152091ca9 ("panfrost: Use canonical characterization of tls_size")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7613>

panfrost: Fix out-of-bounds read on SFBD

Fixes glmark2 -bshadow, which uses a depth-only render target.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Robin Murphy <robin.murphy@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7557>

panfrost: Remove panfrost_can_linear

Always permit falling back to linear, now that linear Z/S is supported
on SFBD.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Robin Murphy <robin.murphy@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7557>

panfrost: Implement linear Z/S for SFBD

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Robin Murphy <robin.murphy@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7557>

iris: Use converted depth in clear_depth_stencil

Until recently, the depth value from glClearBufferfv wasn't clamped.

Before then, this patch enabled the driver to fail the clearbuffer-depth
piglit test with INTEL_DEBUG=nofc. This is because convert_depth_value
relies on the assumption that the depth value is clamped.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7410>

iris: Add and use convert_depth_value

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7410>

mesa: Clamp some depth values in glClearBufferfi

OpenGL 3.0 spec, section 4.2.3 "Clearing the Buffers":

   depth and stencil are the values to clear the depth and stencil
   buffers to, respectively. Clamping and type conversion for
   fixed-point depth buffers are performed in the same fashion as for
   ClearDepth.

Enables iris to pass the clearbuffer-depth-stencil piglit test.

Cc: mesa-stable
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7410>

mesa: Clamp some depth values in glClearBufferfv

OpenGL 3.0 spec, section 4.2.3 "Clearing the Buffers":

   If buffer is DEPTH, drawbuffer must be zero, and value points to the
   single depth value to clear the depth buffer to. Clamping and type
   conversion for fixed-point depth buffers are performed in the same
   fashion as for ClearDepth.

Enables iris to pass the clearbuffer-depth piglit test.

v2. Add spec citation. (Eric Anholt)
v3. Don't clamp floating point formats. (Eric Anholt)

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7410>

mesa: Add and use _mesa_has_depth_float_channel

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7410>

nir: allow reordering of loads from read-only modes

fossil-db (Navi):
Totals from 710 (0.51% of 138917) affected shaders:
SGPRs: 45007 -> 44791 (-0.48%)
VGPRs: 36116 -> 36284 (+0.47%); split: -0.03%, +0.50%
CodeSize: 3811540 -> 3795332 (-0.43%); split: -0.43%, +0.00%
MaxWaves: 8018 -> 8005 (-0.16%)
Instrs: 758383 -> 755084 (-0.44%); split: -0.44%, +0.01%
Cycles: 5786240 -> 5758848 (-0.47%); split: -0.48%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7600>

nir: add nir_var_mem_ubo to nir_var_read_only_modes

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7600>

nir: add strength reduction pattern for imod/irem with pow2 divisor.

Affected games are Detroit : Become Human and Doom : Eternal.

Totals from 6262 (4.54% of 138013) affected shaders (RAVEN):
SGPRs: 678472 -> 678640 (+0.02%)
VGPRs: 498288 -> 498360 (+0.01%)
CodeSize: 67064196 -> 65926000 (-1.70%)
MaxWaves: 19390 -> 19382 (-0.04%)
Instrs: 13175372 -> 12932517 (-1.84%)
Cycles: 1444043256 -> 1443022576 (-0.07%); split: -0.08%, +0.01%
VMEM: 929560 -> 908726 (-2.24%); split: +0.39%, -2.63%
SMEM: 406207 -> 400062 (-1.51%); split: +0.46%, -1.97%
VClause: 215168 -> 215031 (-0.06%)
SClause: 443312 -> 442324 (-0.22%); split: -0.25%, +0.03%
Copies: 1350793 -> 1344326 (-0.48%); split: -0.52%, +0.04%
Branches: 506432 -> 506370 (-0.01%); split: -0.02%, +0.01%
PreSGPRs: 619652 -> 619619 (-0.01%)
PreVGPRs: 473212 -> 473168 (-0.01%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/175>

zink: update shader modules in gfx program when flagged dirty

for shader keys to work right, these need to actually update the shader
module that's being used

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7193>

zink: put those shader keys to work fixing up fragment shaders

eliminate gl_SampleMask writes when necessary to mimic GL behavior

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7193>

zink: fill in params for fs shader keys and flag shader for rebuild

we need to check for rebuild any time fb samples becomes 0 in order to remove
any writes to gl_SampleMask

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7193>

zink: move shader key structs into their own header

this is going to get messy as we fill them out, so at least we can
keep things split up a bit for organizational sake

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7193>

zink: refcount the shader cache

we want to be able to reuse this between programs with matching slot
maps, and refcounting allows that without having to copy the table

also add some docs about all the different shader caching structs

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7193>

zink: initial implementation of shader keys

these are cached per-program for now since we have to ensure that the slot map
always matches up between shader states

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7193>

pan/bi: Add support for tex offsets

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

pan/bi: Allow lane selections on component 4 and above

The lane selection only cares about intra-32b swizzling. Add a modulo
on the test to allow selecting lanes when the swizzle is above 4 (needed
for MKVEC.v4i8 lane selection).

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

pan/bi: Allow vec16 in bi_print_swizzle()

Ideally we should choose "abcd" instead of "xyzw" when accessing a
vector that has more than 4 components, but bi_instruction does not
provide this information, so let's keep things simple for now.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

pan/bi: Add support for derivative instructions

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

pan/bi: Add support for the CLPER instructions

Those are needed to implement derivatives.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

pan/bi: Rename CLPER into CLPER_V7 and add CLPER_V6

The encoding is different between v6 and v7.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

pan/bi: Expose FAU slots

Instead of adding a BIR_INDEX_ per FAU index, let's group some of those
together.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

pan/bi: Store the architecture in the compiler context

Some instructions differ between v6 and v7 and we'll need to know which
architecture we're compiling for if we want to generate the right
instructions.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

panfrost: Get rid of the Pixel Format descriptor

We use opaque uint to encode formats everywhere else, so let's make
things consistent and convert the only user to an opaque int too.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

panfrost: Fix panfrost_format_to_bifrost_blend()

panfrost_format_to_bifrost_blend() shouldn't return a pipe_format, but
a mali_format.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

pan/bi: Force BLEND src0 to r0

Blend shaders expect the input color to be passed through r0-r3, let's
enforce that when we allocate registers.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

pan/bi: Extract shadowmap comparator

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

aco/tests: add some more clamp combining tests

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7045>

aco/tests: expand optimize.const_comparison_ordering tests

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7045>

aco/tests: initialize debug function

aco_log() will print the message to stderr.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7045>

aco: disallow various v_add_u32 opts if modifiers are used

Check for clamp, SDWA or DPP. The optimization isn't possible with SDWA
and DPP, so it would have been skipped anyway. Doing any of these with a
clamp modifier present would be incorrect.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7045>

aco: fix combine_constant_comparison_ordering() NaN check with 16/64-bit

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7045>

aco: don't combine precise max(min()) to med3

fossil-db (Navi):
Totals from 241 (0.18% of 137413) affected shaders:
CodeSize: 856280 -> 856308 (+0.00%); split: -0.00%, +0.00%
Instrs: 164220 -> 164514 (+0.18%); split: -0.00%, +0.18%
Cycles: 1031916 -> 1033092 (+0.11%); split: -0.00%, +0.11%
VMEM: 77855 -> 78514 (+0.85%); split: +0.85%, -0.01%
SMEM: 20501 -> 20593 (+0.45%); split: +0.46%, -0.01%
Copies: 9791 -> 9790 (-0.01%); split: -0.03%, +0.02%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7045>

radeonsi: remove AMD_DEBUG=zerovram flag

The same feature is available by using: radeonsi_zerovram=true

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7525>

radeonsi: remove unused NO_RB_PLUS flag

It's not used since https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1751.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7525>

radv: add img debug flag

This is similar to AMD_DEBUG=tex, but for radv.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5734>

radeonsi: use ac_surface_print_info in si_print_texture_info

Pieces of information not printed by ac_surface_print_info are still
printed in si_print_texture_info.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5734>

amd/common: introduce ac_surface_print_info

This is mostly copied from si_print_texture_info, with the si-specific
bits removed. Moving it into common code will allow to use it from both
radeonsi and radv.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5734>

meson: verify that d3d12.h exists when building the d3d12 driver

Without this header-file, we can't build the driver. So let's verify
that it exists, and can be used by the C++ compiler.

This should make it a bit more clear what's wrong if someone attempts to
build this using MinGW or on Linux.

Fixes: 2ea15cd661c ("d3d12: introduce d3d12 gallium driver")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7575>

microsoft/compiler: correct typo

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7578>

microsoft/compiler: inline some struct-declarations

We don't need to refer to these by name anywhere, so let's just inline
these for readability reasons.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7578>

microsoft/compiler: move c++ higher up

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7578>

microsoft/compiler: remove unused struct

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7578>

aco: optimize v_add(v_bcnt(a, 0), b) to v_bcnt(a, b)

The first operand of v_bcnt should always be a VGPR because if it's
a SGPR, isel selects s_bcnt1 but I added a sanity check to prevent
any problems.

fossils-db (Vega10):
Totals from 23 (0.02% of 139517) affected shaders:
CodeSize: 106828 -> 106664 (-0.15%)
Instrs: 20242 -> 20201 (-0.20%)
Cycles: 213112 -> 211352 (-0.83%)
VMEM: 3200 -> 3184 (-0.50%)
SMEM: 928 -> 927 (-0.11%)

Helps Control, Assassins Creeds Origins and Youngblood.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7568>

driconf: remove the redundant glx-extension-disabling options

Now that we introduced the generic glx_extension_override option,
we can remove the glx_disable_oml_sync_control,
glx_disable_sgi_video_sync, and glx_disable_ext_buffer_age ones.

It seems like the only user for them was the vmwgfx, and only for
Gnome and Compiz which are covered by the default mesa driconf. This
means that it is unlikely for a user to have these options set in
their local driconf file.

Suggested-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7252>

radeonsi: Add auxiliary plane support.

This adds support for multiple DRM planes for a single format plane
and uses that to enable DCC support with modifiers.

With the implicit flush patches we can also enable displayable DCC
both with and without DCC as the X server and compositors know not
to do frontbuffer rendering onto images with multiple DRM planes.

For now we require that the extra planes are essentially fixed though.
We require that the offset/stride are the same as ac_surface computes
and that all planes are in the same buffer. This is mainly for
simplicity and could be somewhat more relaxed in the future given
a strong usecase.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>

radeonsi: Do not try to disable displayable DCC with modifiers.

We do flushing on glFlush etc., so we don't need explicit flush,
but we still need to avoid frontbuffer rendering.

For modifiers there was logic put in apps that basically prevent
frontbuffer rendering if multipe planes are involved.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>

radeonsi: Do not disable DCC when we have it as a modifier.

Because other processes might be expecting DCC.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>

radeonsi: Add modifier support.

This adds basic modifier support in radeonsi.

Support for import/export of DCC comes in a later patch as that
needs support for multiple memory planes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>

radeonsi: Check pitch and offset for validity.

And lack of overflows, which should help for security.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>

amd/common: Add modifier tests.

This primarily tests that:
 - multiple GPUs with the same GPU modifier parameters result
   in the same tiling layout.
 - The size & alignment calculations don't change for a given
   modifier & image parameters.

It does this primarily based on addrlib. Radeonsi has used addrlib
for the retiling of displayable DCC for a while already, so the
DCC tiling should be pretty reliable.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>

amd/common: Add support for modifiers.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>

drm-uapi: Add AMD modifiers.

This adds modifiers for GFX9+ AMD GPUs.

As the modifiers need a lot of parameters I split things out in
getters and setters.
  - Advantage: simplifies the code a lot
  - Disadvantage: Makes it harder to check that you're setting all
                  the required fields.

The tiling modes seem to change every generatio, but the structure
of what each tiling mode is good for stays really similar. As such
the core of the modifier is
 - the tiling mode
 - a version. Not explicitly a GPU generation, but splitting out
   a new set of tiling equations.

Sometimes one or two tiling modes stay the same and for those we
specify a canonical version.

Then we have a bunch of parameters on how the compression works.
Different HW units have different requirements for these and we
actually have some conflicts here.

e.g. the render backends need a specific alignment but the display
unit only works with unaligned compression surfaces. To work around
that we have a DCC_RETILE option where both an aligned and unaligned
compression surface are allocated and a writer has to sync the
aligned surface to the unaligned surface on handoff.

Finally there are some GPU parameters that participate in the tiling
equations. These are constant for each GPU on the rendering/texturing
side. The display unit is very flexible however and supports all
of them :|

Some estimates:
 - Single GPU, render+texture: ~10 modifiers
 - All possible configs in a gen, display: ~1000 modifiers
 - Configs of actually existing GPUs in a gen: ~100 modifiers

For formats with a single plane everything gets put in a separate
DRM plane. However, this doesn't fit for some YUV formats, so if
the format has >1 plane, we let the driver pack the surfaces into
1 DRM plane per format plane.

This way we avoid X11 rendering onto the frontbuffer with DCC, but
still fit into 4 DRM planes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>

radeonsi: Add displayable DCC flushing without explicit flushes.

Flushes non-explicit shared textures that need retiling on

* glFlush
* glSync
* glSignalSemaphoreEXT
* DRI fences.
* The first time we create a non-explicit handle for it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>

amd/addrlib: Use signed char for INT_8.

Some architectures like aarch64 and ppc64el have char = unisgned char.
This breaks meta equation generation for DCC coords, as addrlib tries
to filter all the Z bits > -1 which ends up being all the Z bits > 255.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7593>

radv: Do the sample check for tiling earlier.

The LINEAR optimization is not allowed for MSAA images.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7594>

turnip: Fix file descriptor return.

Fix defect reported by Coverity Scan.

Logically dead code (DEADCODE)
dead_error_line: Execution cannot reach the expression -1 inside this statement: return ret ? -1 : handle.fd;

Fixes: cec0bc73e55 ("turnip: rework fences to use syncobjs")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7498>

radeonsi: enable GL_EXT_demote_to_helper_invocation

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7586>

ac/llvm: fix demote inside conditional branches

The big comment explains it.

v2: don't kill if subgroup ops are used

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7586>

nir: optimize nir_lower_discard_to_demote to lower discard/demote both ways

This is smarter and also lowers demote to discard if helper invocations are
not needed.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7586>