platform/kernel/linux-rpi.git
3 years agodrm/amdgpu: HW setup of 2-level vmid0 page table
Oak Zeng [Fri, 18 Sep 2020 04:12:56 +0000 (23:12 -0500)]
drm/amdgpu: HW setup of 2-level vmid0 page table

Set up HW for 2-level vmid0 page table: 1. Set up
PAGE_TABLE_START/END registers. Currently only plan
to do 2-level page table for ALDEBARAN, so only gfxhub1.0
and mmhub1.7 is changed. 2. Set page table base register.
For 2-level page table, the page table base should point
to PDB0. 3. Disable AGP and FB aperture as they are not
used.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Christian Konig <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Set up vmid0 PDB0
Oak Zeng [Fri, 18 Sep 2020 04:04:29 +0000 (23:04 -0500)]
drm/amdgpu: Set up vmid0 PDB0

If use gart for FB translation, allocate and fill
PDB0.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Christian Konig <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Add function to allocate and fill PDB0
Oak Zeng [Fri, 18 Sep 2020 03:53:54 +0000 (22:53 -0500)]
drm/amdgpu: Add function to allocate and fill PDB0

Add functions to allocate PDB0, map it for CPU access,
and fill it.

Those functions are only used for 2-level vmid0 page
table construction

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Use different gart table parameters for 2-level gart table
Oak Zeng [Fri, 18 Sep 2020 01:32:56 +0000 (20:32 -0500)]
drm/amdgpu: Use different gart table parameters for 2-level gart table

If use gart for FB translation, we will squeeze vram into
sysvm aperture. This requires 2 level gart table. Add
page table depth and page table block size parameters
to gmc. This is prepare work to 2-level gart table
construction

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Christian Konig <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Placement of gart and vram in sysvm aperture
Oak Zeng [Wed, 16 Sep 2020 02:08:50 +0000 (21:08 -0500)]
drm/amdgpu: Placement of gart and vram in sysvm aperture

If use GART for FB translation, place both vram and gart to sysvm
aperture. AGP aperture is not set up in this case because it
is not used

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Christian Konig <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Modify comments of vram_start/end
Oak Zeng [Tue, 15 Sep 2020 19:47:30 +0000 (14:47 -0500)]
drm/amdgpu: Modify comments of vram_start/end

Modify the comment to reflect the fact that, if
use GART for vram address translation for vmid0,
[vram_start, vram_end] will be placed inside SYSVM
aperture, together with GART.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Christian Konig <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Moved gart_size calculation to mc_init functions
Oak Zeng [Sat, 3 Oct 2020 01:03:11 +0000 (20:03 -0500)]
drm/amdgpu: Moved gart_size calculation to mc_init functions

In amdgpu_gmc_gart_location function, gart_size is adjusted
by a smu_prv_buffer_size. This logic shouldn't belong to
this function. Move the logic to the mc_init functions

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Christian Konig <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Use physical translation mode to access page table
Oak Zeng [Sat, 23 Jan 2021 17:34:45 +0000 (11:34 -0600)]
drm/amdgpu: Use physical translation mode to access page table

On A+A platform, CPU write page directory and page table in cached
mode. So it is necessary for page table walker to snoop CPU cache.
This setting is necessary for page walker to snoop page directory
and page table data out of CPU cache.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Acked-by: Christian Konig <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Don't reserve vram as WC for A+A
Oak Zeng [Fri, 22 Jan 2021 19:00:06 +0000 (13:00 -0600)]
drm/amdgpu: Don't reserve vram as WC for A+A

On A+A platform, vram can be mapped as WB. Not necessarily
to always map vram as WC on such platform.

Calling function arch_io_reserve_memtype_wc will mark the
whole vram region as WC. So don't call it for A+A platform.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian Konig <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/pm: Correct msg status check for powerlimit
Lijo Lazar [Fri, 29 Jan 2021 08:24:05 +0000 (16:24 +0800)]
drm/amd/pm: Correct msg status check for powerlimit

Status 0 indicates success, fix the check before using PPTable limit

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>`
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/pm: Enable performance determinism on aldebaran
Lijo Lazar [Fri, 5 Mar 2021 21:02:49 +0000 (16:02 -0500)]
drm/amd/pm: Enable performance determinism on aldebaran

Performance Determinism is a new mode in Aldebaran where PMFW tries to
maintain sustained performance level. It can be enabled on a per-die
basis on aldebaran. To guarantee that it remains within the power cap,
a max GFX frequency needs to be specified in this mode. A new
power_dpm_force_performance_level, "perf_determinism", is defined to enable
this mode in amdgpu. The max frequency (in MHz) can be specified through
pp_dpm_sclk. The mode will be disabled once any other performance level
is chosen.

Ex: To enable perf determinism at 900Mhz max gfx clock

echo perf_determinism > /sys/bus/pci/devices/.../power_dpm_force_performance_level
echo max 900 > /sys/bus/pci/devices/.../pp_dpm_sclk

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/pm: Add DCBTC support for aldebaran
Lijo Lazar [Thu, 28 Jan 2021 10:53:27 +0000 (18:53 +0800)]
drm/amd/pm: Add DCBTC support for aldebaran

On aldebaran DCBTC should be run after enabling DPM. DCBTC won't be run
if support is not enabled in PPTable. Without PPTable support the message
is dummy and will return success always.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/pm: Fix power limit query on aldebaran
Lijo Lazar [Thu, 28 Jan 2021 10:20:06 +0000 (18:20 +0800)]
drm/amd/pm: Fix power limit query on aldebaran

Aldebaran doesn't have AC/DC power limits. Separate the implementation
from SMU13. Max power limit is queried from PPTable.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: mask the xgmi number of hops reported from psp to kfd
Jonathan Kim [Wed, 27 Jan 2021 20:24:59 +0000 (15:24 -0500)]
drm/amdgpu: mask the xgmi number of hops reported from psp to kfd

The psp supplies the link type in the upper 2 bits of the psp xgmi node
information num_hops field.  With a new link type, Aldebaran has these
bits set to a non-zero value (1 = xGMI3) so the KFD topology will report
the incorrect IO link weights without proper masking.
The actual number of hops is located in the 3 least significant bits of
this field so mask if off accordingly before passing it to the KFD.

Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Reviewed-by: Amber Lin <amber.lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: enable 48-bit IH timestamp counter
Alex Sierra [Fri, 15 Jan 2021 23:03:18 +0000 (17:03 -0600)]
drm/amdgpu: enable 48-bit IH timestamp counter

By default this timestamp is 32 bit counter. It gets
overflowed in around 10 minutes.

Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: enable retry fault wptr overflow
Philip Yang [Tue, 22 Sep 2020 17:09:33 +0000 (13:09 -0400)]
drm/amdgpu: enable retry fault wptr overflow

If xnack is on, VM retry fault interrupt send to IH ring1, and ring1
will be full quickly. IH cannot receive other interrupts, this causes
deadlock if migrating buffer using sdma and waiting for sdma done while
handling retry fault.

Remove VMC from IH storm client, enable ring1 write pointer overflow,
then IH will drop retry fault interrupts and be able to receive other
interrupts while driver is handling retry fault.

IH ring1 write pointer doesn't writeback to memory by IH, and ring1
write pointer recorded by self-irq is not updated, so always read
the latest ring1 write pointer from register.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Use free system memory size for kfd memory accounting
Oak Zeng [Mon, 18 Jan 2021 20:55:34 +0000 (14:55 -0600)]
drm/amdgpu: Use free system memory size for kfd memory accounting

With the current kfd memory accounting scheme, kfd applications
can use up to 15/16 of total system memory. For system which
has small total system memory size it leaves small system memory
for OS. For example, if the system has totally 16GB of system
memory, this scheme leave OS and non-kfd applications only 1GB
of system memory. In many cases, this leads to OOM killer.

This patch changed the KFD system memory accounting scheme.
15/16 of free system memory when kfd driver load. This deduct
the system memory that OS already use.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Suggested-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: apply new pmfw loading sequence to arcturus and onwards
Hawking Zhang [Wed, 20 Jan 2021 11:49:05 +0000 (19:49 +0800)]
drm/amdgpu: apply new pmfw loading sequence to arcturus and onwards

Arcturus and onwards products should follow the same sequence
that have pmfw loading ahead of tmr setup

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Fix aldebaran MMHUB CG/LS logic
Lijo Lazar [Mon, 18 Jan 2021 14:44:16 +0000 (22:44 +0800)]
drm/amdgpu: Fix aldebaran MMHUB CG/LS logic

Aldebaran MMHUB CG/LS logic is controlled by VBIOS. Enable the state
change logic only if driver is used for control.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Enable CP idle interrupts
Lijo Lazar [Sat, 16 Jan 2021 05:57:55 +0000 (13:57 +0800)]
drm/amdgpu: Enable CP idle interrupts

v1: The interrupts need to be enabled to move to DS clocks.
v2: Don't enable GFX IDLE interrupts if there are no GFX rings.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/pm: Remove redundant generic message index
Lijo Lazar [Tue, 12 Jan 2021 11:21:04 +0000 (19:21 +0800)]
drm/amdgpu/pm: Remove redundant generic message index

Remove SMU_MSG_GfxDriverReset generic index.
Always use SMU_MSG_GfxDeviceDriverReset as the generic index for reset.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/pm: Fix reset message mapping on aldebaran
Lijo Lazar [Tue, 12 Jan 2021 11:19:52 +0000 (19:19 +0800)]
drm/amdgpu/pm: Fix reset message mapping on aldebaran

Use the correct mapping for mode-reset messages on aldebaran

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/pm: Remove unsupported MP1 messages from aldebaran
Lijo Lazar [Mon, 11 Jan 2021 05:51:52 +0000 (13:51 +0800)]
drm/amdgpu/pm: Remove unsupported MP1 messages from aldebaran

PrepareMp1Reset and SoftReset messages are not supported on aldebaran.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Add clock gating support for aldebaran
Lijo Lazar [Fri, 5 Mar 2021 20:58:04 +0000 (15:58 -0500)]
drm/amdgpu: Add clock gating support for aldebaran

Aldebaran clock gating support for GFX,SDMA,IH blocks
VCN/JPEG blocks are excluded in this patch, to be enabled later

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Acked-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add mmhub client ids for aldebaran
Alex Deucher [Tue, 5 Jan 2021 21:21:31 +0000 (16:21 -0500)]
drm/amdgpu: add mmhub client ids for aldebaran

Add the mmhub client id table for aldebaran.

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: enable dpg indirect sram mode on aldebaran
James Zhu [Thu, 17 Dec 2020 21:18:14 +0000 (16:18 -0500)]
drm/amdgpu: enable dpg indirect sram mode on aldebaran

Enable dpg indirect sram mode on aldebaran.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: enable vcn dpg mode on aldebaran
James Zhu [Thu, 17 Dec 2020 21:14:08 +0000 (16:14 -0500)]
drm/amdgpu: enable vcn dpg mode on aldebaran

Enable vcn dpg mode on aldebaran

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: enable vcn and jpeg on aldebaran
James Zhu [Thu, 17 Dec 2020 21:12:08 +0000 (16:12 -0500)]
drm/amdgpu: enable vcn and jpeg on aldebaran

Enable vcn and jpeg 2.6 on aldebaran.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Enable swsmu block on aldebaran
Lijo Lazar [Tue, 22 Dec 2020 13:43:49 +0000 (21:43 +0800)]
drm/amdgpu: Enable swsmu block on aldebaran

Enable smu13 block on aldebaran

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: switch to cached noretry setting for aldebaran
Hawking Zhang [Thu, 31 Dec 2020 04:50:56 +0000 (12:50 +0800)]
drm/amdgpu: switch to cached noretry setting for aldebaran

global noretry setting now is cached to gmc.noretry

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdkfd: Fix saving the ACC vgprs for Aldebaran
Laurent Morichetti [Tue, 22 Dec 2020 19:42:46 +0000 (11:42 -0800)]
drm/amdkfd: Fix saving the ACC vgprs for Aldebaran

get_num_acc_vgprs does not set status.scc if the number of acc vgprs
is 0, so use an and instruction to set the condition code.

The Aldebaran handler binary was not based on the latest version of
the sources, so this update to the binary is the minimal change only
adding two instructions to set the condition code.

A newer version of the handler should be generated and tested in
another commit.

Signed-off-by: Laurent Morichetti <laurent.morichetti@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/pm: Set no fan control flag as needed.
Lijo Lazar [Wed, 9 Dec 2020 13:06:16 +0000 (21:06 +0800)]
drm/amd/pm: Set no fan control flag as needed.

For GPUs that don't support fan control, set the no fan control flag so
that they don't appear in hwmon sensors.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: bypass hdp read cache invalidation for aldebaran (v2)
Hawking Zhang [Tue, 22 Dec 2020 07:55:35 +0000 (15:55 +0800)]
drm/amdgpu: bypass hdp read cache invalidation for aldebaran (v2)

hdp read cache is removed in aldebaran. don't issue
an mmio write or write data packet to hardware.

v2: rebase

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Aldebaran doesn't use semaphore
Amber Lin [Mon, 14 Dec 2020 20:21:23 +0000 (15:21 -0500)]
drm/amdgpu: Aldebaran doesn't use semaphore

Simplify all Aldebaran DIDs into one ASIC type.

Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: UTLC1 RB SDMA timeout on Aldebaran
Alex Sierra [Tue, 15 Dec 2020 00:15:42 +0000 (18:15 -0600)]
drm/amdgpu: UTLC1 RB SDMA timeout on Aldebaran

[Why]
This causes infinite retries on the UTCL1 RB, preventing
higher priority RB such as paging RB.

[How]
Set to one the SDMAx_UTLC1_TIMEOUT registers for all SDMAs.

Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdpgu: add ATOM_DGPU_VRAM_TYPE_HBM2E vram type
Feifei Xu [Wed, 16 Dec 2020 04:41:27 +0000 (12:41 +0800)]
drm/amdpgu: add ATOM_DGPU_VRAM_TYPE_HBM2E vram type

0x61 is assigned to HBM2E in atom_dgpu_vram_type.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: retire aldebaran gpu_info firmware
Hawking Zhang [Mon, 16 Nov 2020 08:15:30 +0000 (16:15 +0800)]
drm/amdgpu: retire aldebaran gpu_info firmware

driver should use the gfx_info atomfirmware interface

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: query aldebaran gfx_config through atomfirmware i/f
Hawking Zhang [Fri, 13 Nov 2020 06:35:39 +0000 (14:35 +0800)]
drm/amdgpu: query aldebaran gfx_config through atomfirmware i/f

For ASICs that don't support ip discovery feature, query
gfx configuration through atomfirmware interface, rather
than gpu_info firmware.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/pm: Remove CPU virtual address notification in aldebaran
Lijo Lazar [Sat, 28 Nov 2020 10:09:55 +0000 (18:09 +0800)]
drm/amd/pm: Remove CPU virtual address notification in aldebaran

PPSMC_MSG_SetSystemVirtualDramAddrHigh/Low messages are not handled by
PMFW in aldebaran

Signed-off-by: Lijo Lazar <Lijo.Lazar@amd.com>
Reviewed-by: Kenneth Feng <Kenneth.Feng@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/pm: Add support to override pptable id for aldebaran
Lijo Lazar [Sat, 28 Nov 2020 09:31:08 +0000 (17:31 +0800)]
drm/amd/pm: Add support to override pptable id for aldebaran

Temporarily force to use BU PPTable defined in VBIOS. Add support to
override PPTable defined by module parameter.Add FW reported version to
kernel log.

Signed-off-by: Lijo Lazar <Lijo.Lazar@amd.com>
Reviewed-by: Kenneth Feng <Kenneth.Feng@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/amdgpu: Add smu_pptable module parameter
Lijo Lazar [Sat, 28 Nov 2020 09:06:54 +0000 (17:06 +0800)]
drm/amd/amdgpu: Add smu_pptable module parameter

Temporarily add smu_pptable module parameter for aldebaran.This is used
to force soft PPTable use overriding any VBIOS PPTable.

Signed-off-by: Lijo Lazar <Lijo.Lazar@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/pm: Add atom_smc_dpm_info_v4_10 for aldebaran
Lijo Lazar [Sat, 28 Nov 2020 08:38:56 +0000 (16:38 +0800)]
drm/amd/pm: Add atom_smc_dpm_info_v4_10 for aldebaran

Add atom_smc_dpm_info_v4_10 that defines board parameters for aldebaran

Signed-off-by: Lijo Lazar <Lijo.Lazar@amd.com>
Reviewed-by: Kenneth Feng <Kenneth.Feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Don't do FB resize under A+A config
Oak Zeng [Sun, 22 Nov 2020 03:13:19 +0000 (21:13 -0600)]
drm/amdgpu: Don't do FB resize under A+A config

Disable PCIe BAR resizing on A+A config. It's not needed because we won't use the
PCIe BAR, but it breaks the PCI BAR configuration with the current SBIOS.

Error message of FB BAR resize failure under A+A:

[  154.913731] [drm:amdgpu_device_resize_fb_bar [amdgpu]] *ERROR* Problem resizing BAR0 (-22).

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Amber Lin <Amber.Lin@amd.com>
Reviewed-by: Felix Kuehling <Felix.kuehling@amd.com>
Reviewed-by: Christian Koenig <Christian.Koenig@amd.com>
Tested-by: Amber Lin <Amber.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: pre-map device buffer as cached for A+A config
Oak Zeng [Sat, 21 Nov 2020 04:18:10 +0000 (22:18 -0600)]
drm/amdgpu: pre-map device buffer as cached for A+A config

For A+A configuration, device memory is supposed to be mapped as
cachable from CPU side. For kernel pre-map gpu device memory using
ioremap_cache

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Christian Koenig <Christian.Koenig@amd.com>
Tested-by: Amber Lin <Amber.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: update atom_firmware_info_v3_4 (v2)
Feifei Xu [Tue, 8 Dec 2020 15:51:40 +0000 (23:51 +0800)]
drm/amdgpu: update atom_firmware_info_v3_4 (v2)

v1: Added some pspbl parameters
v2: fix fallthrough issue

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Lazar Lijo <Lijo.Lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/pm:add aldebaran support for getting bootup values
Feifei Xu [Thu, 26 Nov 2020 11:04:51 +0000 (19:04 +0800)]
drm/amd/pm:add aldebaran support for getting bootup values

for SMU config.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: disallow use semaphore on aldebaran
Hawking Zhang [Mon, 23 Nov 2020 21:23:36 +0000 (05:23 +0800)]
drm/amdgpu: disallow use semaphore on aldebaran

shall revisit the change later

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: switch to vega20 ih block for aldebaran
Hawking Zhang [Mon, 30 Nov 2020 16:20:35 +0000 (00:20 +0800)]
drm/amdgpu: switch to vega20 ih block for aldebaran

replace vega10 ih block with vega20 ih block for
aldebaran.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: correct IH_CHICKEN programming for aldebaran
Hawking Zhang [Tue, 1 Dec 2020 15:50:51 +0000 (23:50 +0800)]
drm/amdgpu: correct IH_CHICKEN programming for aldebaran

For aldebaran, psp firmware won't program IH_CHICKEN.
it now depends on driver to program it properly so
either bus address or gpu virtual address is just
working for ih ring.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add mmhub error status query callback for aldebaran
Hawking Zhang [Thu, 19 Nov 2020 08:44:55 +0000 (16:44 +0800)]
drm/amdgpu: add mmhub error status query callback for aldebaran

The callback will be invoked to query mmea error
status when needed.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li<Dennis.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add mmhub ras error reset callback for aldebaran
Hawking Zhang [Thu, 19 Nov 2020 08:40:16 +0000 (16:40 +0800)]
drm/amdgpu: add mmhub ras error reset callback for aldebaran

The callback will be invoked to reset mmhub ras error
counters when needed.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li<Dennis.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add mmhub ras error query callback for aldebaran
Hawking Zhang [Thu, 19 Nov 2020 08:35:51 +0000 (16:35 +0800)]
drm/amdgpu: add mmhub ras error query callback for aldebaran

The callback will be invoked to harvest all kinds
of mmhub ras error

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li<Dennis.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add sdma ras error reset callback for aldebaran
Hawking Zhang [Wed, 18 Nov 2020 16:25:09 +0000 (00:25 +0800)]
drm/amdgpu: add sdma ras error reset callback for aldebaran

The callback will be invoked to reset sdma ras error
counters when needed.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li<Dennis.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add sdma ras error query callback for aldebaran
Hawking Zhang [Wed, 18 Nov 2020 15:55:11 +0000 (23:55 +0800)]
drm/amdgpu: add sdma ras error query callback for aldebaran

The callback will be invoked to harvest all kinds
of sdma ras error

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li<Dennis.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add sdma v4_4 ras function
Hawking Zhang [Wed, 18 Nov 2020 13:14:59 +0000 (21:14 +0800)]
drm/amdgpu: add sdma v4_4 ras function

sdma ras function is the main structure to support
sdma ras on aldebaran. the patch initializes late_init
late_fini callbacks.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li<Dennis.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: apply sdma golden settings for aldebaran
Hawking Zhang [Wed, 18 Nov 2020 10:28:08 +0000 (18:28 +0800)]
drm/amdgpu: apply sdma golden settings for aldebaran

perform one-time initialization for sdma registers

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: use physical_node_id to calculate aper_base
Hawking Zhang [Tue, 17 Nov 2020 07:51:29 +0000 (15:51 +0800)]
drm/amdgpu: use physical_node_id to calculate aper_base

Similar as xgmi connected gpu nodes, physical_node_id
* segment_size should be used to calculate the offset
of aper_base.

The asic type check is redundant. once physical_node_id
and segment_size are initialized, it should be count
on.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: skip gds ras workaround for aldebaran
Hawking Zhang [Mon, 16 Nov 2020 08:00:59 +0000 (16:00 +0800)]
drm/amdgpu: skip gds ras workaround for aldebaran

there won't be any gds useage in either kernel or
pm4 anymore for aldebaran.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: init gds for aldebaran
Hawking Zhang [Mon, 16 Nov 2020 07:54:36 +0000 (15:54 +0800)]
drm/amdgpu: init gds for aldebaran

aldebaran removed gds internal memory for atomic usage.
it only supports gws opcode in kernel like barrier,
semaphore.etc. there won't be usage of gds in either
kernel or pm4 packet. max_wave_id should also be marked
as deprecated for aldebaran.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: correct vram_info for HBM2E
Feifei Xu [Mon, 30 Nov 2020 10:57:19 +0000 (18:57 +0800)]
drm/amdgpu: correct vram_info for HBM2E

correct atom_vram_info_header_v2_6 and its vram_module.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: support get_vram_info atomfirmware i/f for aldebaran
Hawking Zhang [Fri, 13 Nov 2020 10:03:07 +0000 (18:03 +0800)]
drm/amdgpu: support get_vram_info atomfirmware i/f for aldebaran

Query vram_type, channel_num, channel_width
information through atomfirmware i/f

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu:return true for mode1_reset_support on aldebaran
Feifei Xu [Thu, 19 Nov 2020 12:04:37 +0000 (20:04 +0800)]
drm/amdgpu:return true for mode1_reset_support on aldebaran

Will remove once validation finished.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu:add smu mode1/2 support for aldebaran
Feifei Xu [Thu, 19 Nov 2020 10:12:26 +0000 (18:12 +0800)]
drm/amdgpu:add smu mode1/2 support for aldebaran

Use MSG_GfxDriverReset for mode reset and retire MSG_Mode1Reset.
Centralize soc15_asic_mode1_reset() and nv_asic_mode1_reset()functions.
Add mode2_reset_is_support() for smu->ppt_funcs.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Add DID for aldebaran
Feifei Xu [Thu, 12 Nov 2020 06:24:51 +0000 (14:24 +0800)]
drm/amdgpu: Add DID for aldebaran

Add 0x7408,0x740C,0x740F in pciidlist.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: added support for register list loading (v2)
John Clements [Wed, 18 Nov 2020 06:25:40 +0000 (14:25 +0800)]
drm/amdgpu: added support for register list loading (v2)

call host to  psp cmd to load reg list

v2: update to latest interface (Alex)

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: added register list driver ctx (v2)
John Clements [Wed, 18 Nov 2020 06:24:52 +0000 (14:24 +0800)]
drm/amdgpu: added register list driver ctx (v2)

updated psp bin parsing and load register list

v2: update to latest interface (Alex)

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: updated host to psp mailbox cmd (v2)
John Clements [Wed, 18 Nov 2020 06:24:12 +0000 (14:24 +0800)]
drm/amdgpu: updated host to psp mailbox cmd (v2)

added host to psp cmd for register list

v2: update to new interface (Alex)

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: declare smuio v13_0 callbacks as static
Hawking Zhang [Mon, 7 Dec 2020 16:46:18 +0000 (00:46 +0800)]
drm/amdgpu: declare smuio v13_0 callbacks as static

fix -Wmissing-protoypes warning

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: initialize external rev_id for aldebaran
Hawking Zhang [Thu, 12 Nov 2020 02:34:58 +0000 (10:34 +0800)]
drm/amdgpu: initialize external rev_id for aldebaran

add exteranal rev_id for aldebaran

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: declare sdma firmware binary file for aldebaran
Kevin Wang [Wed, 9 Sep 2020 05:56:44 +0000 (13:56 +0800)]
drm/amdgpu: declare sdma firmware binary file for aldebaran

declare sdma firmware binary file for aldebaran

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/swsmu: add aldebaran smu13 ip support (v3)
Kevin Wang [Tue, 20 Oct 2020 16:09:36 +0000 (00:09 +0800)]
drm/amd/swsmu: add aldebaran smu13 ip support (v3)

Add initial swSMU support.

v1: add smu13 ip support for aldebaran asic (Kevin/Kenneth)
v2: switch to thm/mp v13_0 ip headers (Hawking)
v3: squash in updates (Alex)

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/swsmu: add aldebaran smu driver if header (v2)
Kevin Wang [Thu, 20 Aug 2020 02:05:25 +0000 (10:05 +0800)]
drm/amd/swsmu: add aldebaran smu driver if header (v2)

add aldebaran smu13 driver if header

v2: squash in updates

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Kenneth Feng <Kenneth.feng@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: comments out vcn/jpeg ip blocks for aldebaran
Hawking Zhang [Fri, 21 Aug 2020 14:12:50 +0000 (22:12 +0800)]
drm/amdgpu: comments out vcn/jpeg ip blocks for aldebaran

vcn fw front door loading is not functional. comments
out vcn/jpeg ip blocks so people can load amdgpu driver
without specify ip_mask module parameter.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: initialize ta firmware for aldebaran
Hawking Zhang [Fri, 21 Aug 2020 14:09:06 +0000 (22:09 +0800)]
drm/amdgpu: initialize ta firmware for aldebaran

only xgmi ta is supported at this stage

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: switch to use reg distance member for mmhub v1_7
Kevin Wang [Tue, 8 Sep 2020 08:45:59 +0000 (16:45 +0800)]
drm/amdgpu: switch to use reg distance member for mmhub v1_7

switch to use register distance member for mmhub v1_7
instead of hardcode

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Clean up mmhub functions for aldebaran
Oak Zeng [Tue, 11 Aug 2020 20:02:38 +0000 (15:02 -0500)]
drm/amdgpu: Clean up mmhub functions for aldebaran

Add more function pointers to amdgpu_mmhub_funcs. ASIC specific
implementation of most mmhub functions are called from a general
function pointer, instead of calling different function for
different ASIC.

V2: Split patch into upstreamable and aldebaran

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/jpeg: enable JPEG on aldebaran
James Zhu [Mon, 6 Jul 2020 13:55:24 +0000 (09:55 -0400)]
drm/amdgpu/jpeg: enable JPEG on aldebaran

enable JPEG on aldebaran

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/vcn: enable VCN on aldebaran
James Zhu [Mon, 6 Jul 2020 13:54:12 +0000 (09:54 -0400)]
drm/amdgpu/vcn: enable VCN on aldebaran

Enable VCN on aldebaran

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/nbio: add aldebaran support
James Zhu [Mon, 6 Jul 2020 13:52:10 +0000 (09:52 -0400)]
drm/amdgpu/nbio: add aldebaran support

Aldebaran has a new mmBIF_MMSCH1_DOORBELL_RANGE setting.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: skip MEC2_JT initialization for aldebaran
Hawking Zhang [Wed, 24 Feb 2021 21:38:22 +0000 (16:38 -0500)]
drm/amdgpu: skip MEC2_JT initialization for aldebaran

MEC2_JT is not supported

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdkfd: add new flag for uncached GPU mapping
Eric Huang [Tue, 12 May 2020 19:25:38 +0000 (15:25 -0400)]
drm/amdkfd: add new flag for uncached GPU mapping

The macro is for memory mapped by GPU as uncached.

Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Reviewed-by: Oak Zeng <Oak.Zeng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: new cache coherence change for Aldebaran
Eric Huang [Tue, 5 May 2020 18:56:05 +0000 (14:56 -0400)]
drm/amdgpu: new cache coherence change for Aldebaran

To support new cache coherence HW on A+A platform mainly in KFD.

Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Reviewed-by: Oak Zeng <Oak.Zeng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/jpeg2.6: Add jpeg2.6 support
James Zhu [Thu, 4 Jun 2020 17:06:29 +0000 (13:06 -0400)]
drm/amdgpu/jpeg2.6: Add jpeg2.6 support

Aldebaran is using jpeg2.6, and the main change is jpeg2.6 using
AMDGPU_MMHUB_0, and jpeg2.5 using AMDGPU_MMHUB_1.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Fix an omission when adding Aldebaran support
Yong Zhao [Wed, 27 May 2020 01:38:53 +0000 (21:38 -0400)]
drm/amdgpu: Fix an omission when adding Aldebaran support

Aldebaran should be the same as Arcturus in the PTE SNOOPED bit handling.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Fix IH client ID naming table
Oak Zeng [Wed, 20 May 2020 16:00:58 +0000 (11:00 -0500)]
drm/amdgpu: Fix IH client ID naming table

Client ID 26 is reserved. Add it to the table.

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/vcn2.6: Add vcn2.6 support
James Zhu [Wed, 3 Jun 2020 13:41:18 +0000 (09:41 -0400)]
drm/amdgpu/vcn2.6: Add vcn2.6 support

Aldebaran is using vcn2.6, and the main change is vcn2.6 using
AMDGPU_MMHUB_0, and vcn2.5 using AMDGPU_MMHUB_1

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add Aldebaran to the VCN family
James Zhu [Wed, 3 Jun 2020 13:17:18 +0000 (09:17 -0400)]
drm/amdgpu: add Aldebaran to the VCN family

including firmware support etc.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdkfd: expose host gpu link via sysfs (v2)
Rajneesh Bhardwaj [Tue, 21 Apr 2020 22:00:07 +0000 (18:00 -0400)]
drm/amdkfd: expose host gpu link via sysfs (v2)

Currently host-gpu io link is always reported as PCIe however, on some
A+A systems, there could be one xgmi link available. This change exposes
xgmi link via sysfs when it is present.

v2: fix includes (Alex)

Reviewed-by: Oak Zeng <oak.zeng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: support get xgmi information for Aldebaran
Rajneesh Bhardwaj [Thu, 30 Apr 2020 06:34:57 +0000 (02:34 -0400)]
drm/amdgpu: support get xgmi information for Aldebaran

Aldebaran uses registers defined in header gc_9_4_2 but much of the xgmi
related functionality can be obtained by reusing the exisitng definition
from gfxhub_v1_1_get_xgmi_info. While adding support for Aldebaran, also
refactored code to better handle the new scenario.

Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: define address map for host xgmi link (v3)
Rajneesh Bhardwaj [Wed, 21 Oct 2020 06:12:11 +0000 (14:12 +0800)]
drm/amdgpu: define address map for host xgmi link (v3)

This applies to AMD Accelerated Processing Platforms that support host
gpu interconnect throguh a special link (xgmi). Aldebaran systems will
support this special feature for utilizing the benefits of host-gpu
cache coherence. This change outlines the basic framework for mapping
the GPU VRAM (HBM) to system address space making it accesible to the
host but managed by the amdgpu driver since this region is marked as
reserved memory in host address space by the underlying system firmware.

v2: switch to smuio callback function to check the type
of host-gpu interface (Hawking)
v3: use hub callbacks rather than direct function calls (Alex)

Reviewed-by: Oak Zeng <oak.zeng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: enable xgmi support for Aldebaran
Rajneesh Bhardwaj [Sun, 5 Apr 2020 18:43:24 +0000 (14:43 -0400)]
drm/amdgpu: enable xgmi support for Aldebaran

Like its predecessors Aldebran also supports advanced high bandwidth
GPU-GPU communication interface known as xgmi. This enables the basic
xgmi support while refactoring the code slightly.

Detection of xgmi link between host cpu and gpu will be introduced in a
different patch.

Reviewed-by: Oak Zeng <oak.zeng@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: initialize smuio callbacks for aldebaran
Hawking Zhang [Fri, 16 Oct 2020 15:05:51 +0000 (23:05 +0800)]
drm/amdgpu: initialize smuio callbacks for aldebaran

initialize smuio v13_0 callbacks for aldebaran

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: implement smuio v13_0 callbacks
Hawking Zhang [Fri, 23 Oct 2020 13:46:20 +0000 (21:46 +0800)]
drm/amdgpu: implement smuio v13_0 callbacks

Aldebaran will use smuio v13_0 callbacks

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add new smuio callbacks for aldebaran
Hawking Zhang [Tue, 8 Dec 2020 12:57:22 +0000 (20:57 +0800)]
drm/amdgpu: add new smuio callbacks for aldebaran

is_host_gpu_xgmi_supported is used to query gpu and
cpu/host link type. get_die_id is used to query die
ids.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: enable psp v13 ip block for aldebaran
Hawking Zhang [Sun, 26 Apr 2020 14:43:15 +0000 (22:43 +0800)]
drm/amdgpu: enable psp v13 ip block for aldebaran

Add psp v13 ip block to soc ip init list for aldebaran

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: bypass gc_9_x_common golden settings
Hawking Zhang [Tue, 26 May 2020 07:21:43 +0000 (15:21 +0800)]
drm/amdgpu: bypass gc_9_x_common golden settings

ALDEBARAN doesn't need these golden settings.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: detect sriov capability for aldebaran
Hawking Zhang [Mon, 25 May 2020 08:20:35 +0000 (16:20 +0800)]
drm/amdgpu: detect sriov capability for aldebaran

SRIOV pf/vf function identifier regsiter in aldebaran
is the same as the one in arcturus

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: load pmfw prior to other non-psp fw for aldebaran
Hawking Zhang [Mon, 25 May 2020 07:27:18 +0000 (15:27 +0800)]
drm/amdgpu: load pmfw prior to other non-psp fw for aldebaran

PMFW should be loaded before any operation that
may toggling DF-Cstate. otherwsie, tOS has no
choice but to locally toggle DF Cstate (i.e.
disable DF-Cstate even it already enabled by VBIOS)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: fix incorrect EP_STRAP reg offset for aldebaran
Hawking Zhang [Mon, 25 May 2020 07:08:38 +0000 (15:08 +0800)]
drm/amdgpu: fix incorrect EP_STRAP reg offset for aldebaran

mmRCC_DEV0_EPF0_STRAP0 offset in aldebaran is changed
from arcturus

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: init psp v13 ip function
Hawking Zhang [Mon, 13 Apr 2020 07:07:54 +0000 (15:07 +0800)]
drm/amdgpu: init psp v13 ip function

Initialze psp ip function for aldebaran

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>