Jesse Natalie [Tue, 26 Apr 2022 19:36:09 +0000 (12:36 -0700)]
bin: Add a script for filtering/sorting refcount logs
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16182>
Jesse Natalie [Thu, 28 Apr 2022 22:48:45 +0000 (15:48 -0700)]
mesa: Ensure ARB programs end in a newline
If the last line of an ARB program has a comment, the program will
fail to parse, because the lexer only considers a comment valid if
it ends in a newline, not EOF. The parser then fails on the '#'.
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16230>
Jesse Natalie [Fri, 29 Apr 2022 20:14:34 +0000 (13:14 -0700)]
d3d12: Correctly key off of polygon stipple enable cap
Apparently we were only keying off the presence of a real stipple pattern
being set, and completely ignoring when the app does glDisable().
Add in the actual enable bit as an additional discriminator to determine
if we should be doing polygon stippling.
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16254>
Alyssa Rosenzweig [Mon, 2 May 2022 14:55:33 +0000 (10:55 -0400)]
pan/va: Add non-IDVS VAR_TEX instructions
Used in blit shaders.
Icecream95 supplied the test cases.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15588>
Alyssa Rosenzweig [Mon, 2 May 2022 14:58:43 +0000 (10:58 -0400)]
pan/va: Add VAR_TEX_BUF_GRADIENT instruction
Probably useful for ... something.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15588>
Icecream95 [Fri, 25 Mar 2022 21:37:56 +0000 (10:37 +1300)]
pan/va: Improve texture instructions
[Alyssa: Related improvements.]
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15588>
Icecream95 [Fri, 25 Mar 2022 21:40:17 +0000 (10:40 +1300)]
pan/va: Add absneg modifier to V2F32_TO_V2F16
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15588>
Icecream95 [Fri, 25 Mar 2022 21:35:48 +0000 (10:35 +1300)]
pan/va: Add SEG_ADD/SEG_SUB operation
[Alyssa: Fixes to the instruction.]
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15588>
Icecream95 [Fri, 25 Mar 2022 21:34:44 +0000 (10:34 +1300)]
pan/va: Add more transcendental operations
TODO: Make the secondary opcode field wider so that FATAN_ASSIST can
be split into two instructions
[Alyssa: Fixes to the hardware behaviour.]
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15588>
Icecream95 [Fri, 25 Mar 2022 21:32:13 +0000 (10:32 +1300)]
pan/va: Improvements to LEA_TEX instructions
[Alyssa: Fixes to match hardware.]
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15588>
Alyssa Rosenzweig [Wed, 30 Mar 2022 14:27:16 +0000 (10:27 -0400)]
pan/va: Mark NOT instructions as deprecated
The inverters on the bitwise ops should be used instead.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15588>
Alyssa Rosenzweig [Wed, 30 Mar 2022 14:13:14 +0000 (10:13 -0400)]
pan/va: Add missing TABLE (SFU) instructions
Equivalent to their Bifrost predecessors.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15588>
Alyssa Rosenzweig [Mon, 2 May 2022 15:10:37 +0000 (11:10 -0400)]
pan/va: Generalize message? check for asm
Allows passing more uniforms in more places. We'll use this in a test case in a
moment.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15588>
Alyssa Rosenzweig [Mon, 2 May 2022 13:19:41 +0000 (09:19 -0400)]
panfrost: Flip point coords in hardware
On Bifrost, this is very easy: there's an RSD bit to Y-flip gl_PointCoord. It
should map perfectly to the Gallium bit. With this change, we no longer use
lower_pntc_ytransform on Bifrost, saving a bit of ALU when reading point
coordinates.
On Valhall, this is quite hard: the bit is in the framebuffer descriptor now!
That means it can't be changed in a batch. This is expected to be ok: on GLES
and VK, the origin is controlled only by the framebuffer orientation. It's a
bigger problem on big GL, where GL_POINT_SPRITE_COORD_ORIGIN can be set freely.
To cope, a tri-state data structure is used for the state tracking. This has a
failure case on Valhall: every draw toggling the coord origin. However, the
intention of the ORIGIN state bit is smoothing over coordinate system
differences; it should never /actually/ change once set. Until we see an app
doing something so stupid, I don't think we should worry about.
We need all the Valhall tri-state infrastructure for handling provoking vertices
on big GL anyway.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16173>
Alyssa Rosenzweig [Tue, 26 Apr 2022 20:32:01 +0000 (16:32 -0400)]
panfrost: Lower user clip planes
Since we don't export the relevant CAP, the state tracker calls
nir_lower_clip_vs for us. However, for some reason we're still responsible for
calling nir_lower_clip_fs. Now that we have sane shader key infrastructure,
let's do so.
Fixes the floor rendering wrong in the title screen of Neverball.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16173>
Alyssa Rosenzweig [Tue, 26 Apr 2022 18:50:00 +0000 (14:50 -0400)]
panfrost: Lower point sprites on Bifrost
Use the common pass. This only should trigger when drawing points, so we need
some extra tracking to ensure this.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16173>
Alyssa Rosenzweig [Tue, 26 Apr 2022 19:46:00 +0000 (15:46 -0400)]
panfrost: Refactor variant rebind code
For point sprite lowering on Bifrost and Valhall.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16173>
Alyssa Rosenzweig [Tue, 26 Apr 2022 18:29:55 +0000 (14:29 -0400)]
panfrost: Refactor variant selection code
Extract the "compile a new variant" routine from the "select and bind a variant"
routine. This allows us to simplify the control flow, eliminating the `compiled`
boolean on the shader structure.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16173>
Alyssa Rosenzweig [Tue, 26 Apr 2022 16:37:59 +0000 (12:37 -0400)]
panfrost: Simplify shader key architecture
Rather than clever key compare/initialize code, let's make the shader keys plain
old data. This makes it easier both to extend and to optimize the shader keys.
Keys are compared with a simple memcmp(). I considered a hash table but I don't
think we have enough variants (or large enough keys) to justify the overhead.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16173>
Alyssa Rosenzweig [Tue, 26 Apr 2022 18:13:46 +0000 (14:13 -0400)]
panfrost: Use s->info.stage instead of tgsi stage
Now that we have the NIR handy.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16173>
Alyssa Rosenzweig [Tue, 26 Apr 2022 18:01:41 +0000 (14:01 -0400)]
panfrost: Don't subclass pipe_compute_state
Just copy the bit we need so the NIR doesn't hang around. This is simpler.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16173>
Alyssa Rosenzweig [Tue, 26 Apr 2022 17:58:19 +0000 (13:58 -0400)]
panfrost: Call tgsi_to_nir earlier
This ensures we always have NIR available in the shader state. It also saves a
(trivial) amount of recomputation if multiple TGSI variants are needed.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16173>
Alyssa Rosenzweig [Tue, 26 Apr 2022 16:17:02 +0000 (12:17 -0400)]
panfrost: Remove ancient unused code
Leftover scraps.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16173>
Alyssa Rosenzweig [Wed, 27 Apr 2022 22:57:04 +0000 (18:57 -0400)]
panvk: Emit fragment RSDs even with no shader
In Vulkan, it's possible to create a pipeline with no fragment shader that's
still expected to rasterize. This is useful for depth/stencil side effects, and
is closely related to the "fragment shader required" optimization we do in the
GLES driver. Refactor the RSD emit code to handle this case.
Fixes dEQP-VK.pipeline.stencil.nocolor.*
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16204>
Alyssa Rosenzweig [Wed, 27 Apr 2022 22:54:49 +0000 (18:54 -0400)]
panvk: Gate rasterization on !discard, not fs req
The "fragment shader required?" computed state is about fragment shader side
effects. There may be no fragment shader required but depth/stencil side effects
meaning that rasterization is nonoptional. What actually gates rasterization is
the rasterizer discard bit. Use that instead.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16204>
Alyssa Rosenzweig [Wed, 27 Apr 2022 22:56:36 +0000 (18:56 -0400)]
panvk: Streamline no shader RSD case
Noticed by inspection.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16204>
Alyssa Rosenzweig [Mon, 25 Apr 2022 19:11:34 +0000 (15:11 -0400)]
panfrost: Only flip point sprites for GL
Fixes dEQP-VK.glsl.builtin_var.simple.pointcoord
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16204>
Alyssa Rosenzweig [Mon, 25 Apr 2022 16:36:47 +0000 (12:36 -0400)]
panvk: Use correct point size limits
As determined by Icecream95. Fixes:
dEQP-VK.rasterization.primitive_size.points.point_size_*
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16204>
Alyssa Rosenzweig [Mon, 25 Apr 2022 16:24:04 +0000 (12:24 -0400)]
panvk: Ignore point size for !points
Otherwise wide lines break. The alternative approach is to eliminate the points
writes when not drawing points since we do have topology information at compile
time. I'm admittedly stuck in my GL mindset. That's the approach we'll need for
Valhall anyway.
Fixes dEQP-VK.rasterization.interpolation.basic.lines_wide
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16204>
Icecream95 [Fri, 29 Apr 2022 20:36:40 +0000 (08:36 +1200)]
pan/bi: Use texture index instead of sampler for message preloading
The VAR_TEX definition in ISA.xml only has a field for texture_index,
so trying to read sampler_index will return zero; read from
texture_index instead, and rename other fields for consistency.
The texture and sampler indices must be equal for VAR_TEX to be used,
so either name could be used for the field.
Fixes the wrong textures being used in Thief.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6219
Fixes:
eb1479bda22 ("pan/bi: Support message preloading")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16255>
Gert Wollny [Sun, 1 May 2022 20:49:01 +0000 (22:49 +0200)]
r600: Allow eight bit, three channel formats for vertex buffers
While using three component texture formats results in CTs failures,
three component vertex attributes are fine, and not allowing them
results in significant performance regressisons.
Fixes:
e41958e344cb4b15d01008140a1ee08817104334
r600: Disable eight bit three channel formats
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6399
v2: rename function to is_buffer_format_supported (Emma)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16267>
Lionel Landwerlin [Wed, 6 Apr 2022 19:56:00 +0000 (22:56 +0300)]
anv: limit clflush usage
Discrete platforms don't have LLC, but on those, we mmap our buffers
with WC. So we shouldn't need to clflush there.
Anv already had a boolean field on the physical device to know whether
we need to use clflush(), based off the memory heaps available. So use
that instead.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15780>
Lionel Landwerlin [Thu, 7 Apr 2022 08:20:52 +0000 (11:20 +0300)]
anv: fix clflush usage on utrace copy batch
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
cc5843a573bd ("anv: implement u_trace support")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15780>
Pierre-Eric Pelloux-Prayer [Fri, 29 Apr 2022 15:51:11 +0000 (17:51 +0200)]
radeonsi: fix VS kill_outputs handling
981bd8cbe2d moved outputs removing handling to NIR, but instead of
applying it only to the last stage before the FS this now applies
it to both the GS and the VS.
This commit fixes this by clearing the kill_outputs field for
the VS when using a ES-GS shader.
Fixes:
981bd8cbe2d ("radeonsi: apply key.ge.opt.kill_{outputs,pointsize,clipdistance} in NIR")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16249>
Rhys Perry [Wed, 27 Apr 2022 14:29:34 +0000 (15:29 +0100)]
radv: consider radix sort shaders to be internal/meta
Cleans up RADV_DEBUG=shaders
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16198>
Iago Toral Quiroga [Tue, 26 Apr 2022 07:28:59 +0000 (09:28 +0200)]
v3dv: ignore barriers for image layout transitions from undefined layouts
Layout transitions are not relevant to us, we only care about barriers
that involve a sync point between read/write actions on the image across
GPU jobs.
Image transitions from undefined layout can only happen before the image
is ever used by the GPU, which means they are never relevant to our
implementation.
This improves performance in vkQuake.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16235>
Iago Toral Quiroga [Tue, 26 Apr 2022 07:07:54 +0000 (09:07 +0200)]
v3dv: document Vulkan requirements for signaling operations
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16235>
Iago Toral Quiroga [Thu, 21 Apr 2022 09:08:48 +0000 (11:08 +0200)]
v3dv: don't emit final noop job if we don't have anything to signal
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16235>
Iago Toral Quiroga [Tue, 19 Apr 2022 06:45:22 +0000 (08:45 +0200)]
v3dv: drop obsolete comment
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16235>
Iago Toral Quiroga [Wed, 13 Apr 2022 08:40:54 +0000 (10:40 +0200)]
v3dv: ignore no-op barriers
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16235>
Alyssa Rosenzweig [Sun, 1 May 2022 22:27:56 +0000 (18:27 -0400)]
agx: Lower mediump flat shading
This isn't supported by the hardware. Fixes
dEQP-GLES2.functional.shaders.constants.float_uniform_vertex
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Sun, 1 May 2022 21:51:09 +0000 (17:51 -0400)]
agx: Remove nir_register support
We don't use it anymore, now that we can handle SSA form. Gets rid of
the most gross hack in the compiler.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Sun, 1 May 2022 21:47:22 +0000 (17:47 -0400)]
agx: Remove has_liveness
Given we do no metadata tracking, this is an accident waiting to happen.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Sun, 1 May 2022 21:12:17 +0000 (17:12 -0400)]
agx: Update RA comment
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 19 Apr 2022 01:32:50 +0000 (21:32 -0400)]
agx: Add validation pass
For now, just check that we didn't botch the structure of the block,
since this just bit me.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Mon, 18 Apr 2022 22:34:14 +0000 (18:34 -0400)]
agx: Remove identity moves
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Thu, 14 Apr 2022 03:09:29 +0000 (23:09 -0400)]
agx: Unit test parallel copy lowering
It's pretty tricky.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Thu, 14 Apr 2022 02:15:06 +0000 (22:15 -0400)]
agx: Always use hash table for extracts
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Thu, 14 Apr 2022 01:05:02 +0000 (21:05 -0400)]
agx: Split up RA from post-RA lowering
This allows us to validate results in the middle.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 03:11:23 +0000 (23:11 -0400)]
agx: Lower phi nodes to parallel copies
Now we have an SSA RA :-)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 01:40:35 +0000 (21:40 -0400)]
agx: Don't lower phis in NIR
We're ready for them now! Just scalarize.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Mon, 18 Apr 2022 22:55:38 +0000 (18:55 -0400)]
agx: Copy prop into phi nodes
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 01:40:23 +0000 (21:40 -0400)]
agx: Translate phi nodes
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 22:34:50 +0000 (18:34 -0400)]
agx: Make DCE dumber
The current DCE pass hits issue around phi nodes. These need to be
solved properly eventually, but for now workaround them by doing
something obviously correct (but suboptimal compile time).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Thu, 14 Apr 2022 01:04:36 +0000 (21:04 -0400)]
agx: Adapt liveness analysis for SSA
Lifted from nir_liveness.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Sun, 1 May 2022 19:53:35 +0000 (15:53 -0400)]
agx: Introduce worklist infrastructure
Using the common NIR stuff.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 03:33:09 +0000 (23:33 -0400)]
agx: Add agx_after_block_logical helper
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 03:32:18 +0000 (23:32 -0400)]
agx: Mark the logical ends of blocks
We need to insert parallel copies at the logical end of blocks, before branches.
Add a pseudo instruction signaling that. Cribbed from ACO.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 03:10:47 +0000 (23:10 -0400)]
agx: Add predecessor index helper
To order phi sources.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 02:06:06 +0000 (22:06 -0400)]
agx: Use a dynarray for predecessors
This imposes a fixed ordering, allowing phi sources to be implicitly ordered.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 03:18:03 +0000 (23:18 -0400)]
agx: Remove else optimization
It will conflict with SSA-based RA and needs to be rewritten to happen
late.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Sun, 1 May 2022 20:24:18 +0000 (16:24 -0400)]
agx: Use extract helper for tex internally
Allows better optimization.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 23:46:13 +0000 (19:46 -0400)]
agx: Emit splits for intrinsics
This allows optimizing the extracts.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 00:58:49 +0000 (20:58 -0400)]
agx: Optimize p_split(kill) specially
Let's make sure these are allocated optimally.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 00:43:32 +0000 (20:43 -0400)]
agx: Lower p_split after RA
Using existing regalloc infrastructure.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Sun, 17 Apr 2022 20:47:37 +0000 (16:47 -0400)]
agx: Use a transfer graph for parallel copies
Lifted from ir3. Algorithm is the same; the data structures and interface are
lightly modified to decouple from ir3's IR.
Sequentializing parallel copies after RA is tricky. ir3's implementation works
well enough, so I use that one.
Original implementation by Connor Abbott.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 23:45:34 +0000 (19:45 -0400)]
agx: Add helper to emit splits
This should be used for vector destinations, to facilitate the extraction
optimization.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 00:44:20 +0000 (20:44 -0400)]
agx: Add helper to emit combines
...in such a way that subsequent extracts will be optimized.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 23:43:46 +0000 (19:43 -0400)]
agx: Add a hash table for vector extracts
This will allow us to introduce splits gradually, giving a graceful fallback.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 01:41:34 +0000 (21:41 -0400)]
agx: Add phi pseudo instruction
For SSA.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 00:43:56 +0000 (20:43 -0400)]
agx: Add p_split pseudoinstruction
Easier on RA for extracts.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Wed, 13 Apr 2022 01:29:18 +0000 (21:29 -0400)]
agx: Dynamically allocate agx_instr->src
Required for phi nodes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 23:27:00 +0000 (19:27 -0400)]
agx: Implement simple copyprop
Cleans up some of the mess.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 22:06:16 +0000 (18:06 -0400)]
agx: Use pseudo ops for mov/not/and/xor/or
Rather than using builder magic (implicitly lowered on emit), add actual pseudo
operations (explicitly lowered before encoding). In theory this is slower, I
doubt it matters. This makes the instruction aliases first-class for IR prining
and machine inspection, which will make optimization passes easier to write.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 22:06:13 +0000 (18:06 -0400)]
agx: Add unit test infrastructure
Lifted from Bifrost. Add some basic optimizer tests (they pass!) to show the
compiler is ready to be unit tested. Given we can't have hardware CI for Asahi
yet -- and dEQP is still pretty janky -- unit testing should prove quite useful.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 22:06:12 +0000 (18:06 -0400)]
agx: Wrap compiler header in extern "C"
So we can use it from GTest.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 22:06:10 +0000 (18:06 -0400)]
agx: Use correct types for some IR enums
Otherwise there are implicit int->enum casts which prevent us from building as
C++ (with -fpermissive).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 22:06:08 +0000 (18:06 -0400)]
agx: Match order for designated initializers
Required to compile our headers with C++, to allow us to use GTest unit tests.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 22:06:03 +0000 (18:06 -0400)]
agx: Track write registers more accurately
We may not write a full 32-bit vec4, don't be so pessimistic.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 22:06:01 +0000 (18:06 -0400)]
agx: Note that RA proceeds in dominance-order
This is an important invariant for SSA-based RA to work.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Tue, 12 Apr 2022 22:05:59 +0000 (18:05 -0400)]
agx: Implement some shader-db stats
Instructions, bytes, and registers -- this should hold us over until we
can reverse the underlying uarch and get proper cycle estimations.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Alyssa Rosenzweig [Mon, 18 Apr 2022 00:25:23 +0000 (20:25 -0400)]
asahi: Workaround broken GLSL compiler
https://gitlab.freedesktop.org/mesa/mesa/-/issues/6075 still hasn't been
fixed (despite the bug being known for a year now..)
Workaround the brokenness.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>
Rob Clark [Sat, 30 Apr 2022 17:24:08 +0000 (10:24 -0700)]
freedreno/drm: Fix bos_on_stack calculation
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16263>
Konstantin Seurer [Sat, 30 Apr 2022 21:53:43 +0000 (23:53 +0200)]
radv: Use the entire morton code as sort key
Fixes: be57b08 <"radv: Build accaleration structures using LBVH">
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16264>
Konstantin Seurer [Sat, 30 Apr 2022 09:25:37 +0000 (11:25 +0200)]
radv/radix_sort: Make variable names consistent
We usually use pdevice for "physical device" and not "device pointer".
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16259>
Konstantin Seurer [Sat, 30 Apr 2022 09:19:49 +0000 (11:19 +0200)]
radv/radix_sort: Add missing entry points
Fixes: 5d9ef0e ("radv: Add the fuchsia radix sort")
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16259>
Yiwei Zhang [Sat, 9 Apr 2022 02:48:42 +0000 (02:48 +0000)]
venus: enable ANB shared presentable image prop
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15868>
Yiwei Zhang [Sat, 9 Apr 2022 02:46:00 +0000 (02:46 +0000)]
venus: update vn_GetSwapchainGrallocUsage2ANDROID for shared present
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15868>
Yiwei Zhang [Sat, 9 Apr 2022 00:21:53 +0000 (00:21 +0000)]
venus: cache front_rendering_usage bit at gralloc init
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15868>
Yiwei Zhang [Fri, 8 Apr 2022 23:13:35 +0000 (23:13 +0000)]
venus: refactor android gralloc pieces
There's no functional change.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15868>
Francisco Jerez [Wed, 27 Oct 2021 00:18:58 +0000 (17:18 -0700)]
intel/dev: Compute pixel pipe information based on geometry topology DRM query.
This changes the intel_device_info calculation to call an additional
DRM query requesting the geometry topology from the kernel, which may
differ from the result of the current topology query on XeHP+
platforms with compute-only and 3D-only DSSes. This seems more
reliable than the current guesswork done in intel_device_info.c trying
to figure out which DSSes are available for the render CS.
Cc: 22.1 <mesa-stable>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14143>
Emma Anholt [Thu, 14 Apr 2022 03:25:59 +0000 (20:25 -0700)]
nouveau: Enable the NIR backend by default.
The glsl-to-tgsi code generation and GLSL IR linker is is going away
(!8044), so we need to make the call on whether to use nir-to-tgsi (See
!15932 and !15541), or switch over to the NIR code generator. The NIR
backend should reduce the compile time regression while providing more
direct control over the IR we receive than going through NTT, while still
providing the optimization that NIR-to-TGSI was bringing us.
nv92 shader-db:
total local in shared programs: 2048 -> 1988 (-2.93%)
local in affected programs: 2048 -> 1988 (-2.93%)
total gpr in shared programs: 688468 -> 724705 (5.26%)
gpr in affected programs: 437159 -> 473396 (8.29%)
total instructions in shared programs: 6115978 -> 5874401 (-3.95%)
instructions in affected programs: 5038041 -> 4796464 (-4.80%)
total loops in shared programs: 1361 -> 835 (-38.65%)
loops in affected programs: 538 -> 12 (-97.77%)
total bytes in shared programs:
42389752 ->
40480416 (-4.50%)
bytes in affected programs:
36311616 ->
34402280 (-5.26%)
LOST: 0
GAINED: 1 (pixmark-piano)
nv120 shader-db:
total local in shared programs: 4416 -> 1988 (-54.98%)
local in affected programs: 4416 -> 1988 (-54.98%)
total gpr in shared programs: 870534 -> 893490 (2.64%)
gpr in affected programs: 564210 -> 587166 (4.07%)
total instructions in shared programs: 6379402 -> 6243210 (-2.13%)
instructions in affected programs: 5430790 -> 5294598 (-2.51%)
total bytes in shared programs:
68184224 ->
66729672 (-2.13%)
bytes in affected programs:
58013544 ->
56558992 (-2.51%)
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15949>
Emma Anholt [Mon, 25 Apr 2022 23:32:39 +0000 (16:32 -0700)]
nouveau/nir: Put the UBO offset indirect into the address reg.
Fixes indirect UBO addressing pre-nvc0.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15949>
Karol Herbst [Mon, 25 Apr 2022 20:21:16 +0000 (22:21 +0200)]
nv50/nir: align tlsspace to 0x10
nvc0 aligns to 0x10 in setting up its rogram header, but nv50 TLS
allocation expects the incoming value to be aligned already (like TGSI
always did). Avoids regression in
KHR-GL33.shaders.arrays.declaration.dynamic_expression_array_access_* with
the nir backend.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15949>
Emma Anholt [Sun, 24 Apr 2022 19:44:23 +0000 (12:44 -0700)]
nouveau/nir: Add support for pre-GF100 images and ssbos.
We have to allocate them slots in the global file.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15949>
Emma Anholt [Sun, 24 Apr 2022 17:19:34 +0000 (10:19 -0700)]
ci/nouveau: Add MESA_GLES_VERSION_OVERRIDE=3.1 baseline state.
imirkin requested that I test the GLES31 codepaths on nv50, and this is
the best I can do with the hardware I have.
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15949>
Emma Anholt [Wed, 20 Apr 2022 23:30:37 +0000 (16:30 -0700)]
nouveau/nir: Move FS output stores to the end of the last block.
The nir_move/sink caused instructions to sink interleaved into the output
stores at the end of the shader. nouveau's RA doesn't track liveness of
FS outputs in registers after the export instruction, so they could end up
overwritten. To work around it, after normal NIR move/sink, move the
output stores back to the end of the shader.
Fixes:
b1fa2068b8e8 ("nouveau/nir: Enable nir_opt_move/sink.")
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15949>
Chia-I Wu [Tue, 26 Apr 2022 04:45:50 +0000 (21:45 -0700)]
turnip: fix drm modifier support with planar formats
We need to advertise the results of tu6_plane_count and handle
VK_IMAGE_ASPECT_MEMORY_PLANE_*_BIT.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6374
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16169>
Erik Faye-Lund [Thu, 28 Apr 2022 09:47:37 +0000 (11:47 +0200)]
mesa: add missing error-path
The ARB_shader_objects spec says the following:
> The error INVALID_VALUE is generated by any command that takes one or
> more handles as input, and one or more of these handles are not an
> object handle generated by OpenGL.
And a long, long time ago, we used do to just that for
glDeleteObjectARB... Until
9ac9605de15, all the way back in February 2006,
where the error condition was removed without explanation.
Let's restore it, because it should really be there.
This was noticed by running the tests that are in the mesa-demos
repository, that actually tested this condition.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16211>
Erik Faye-Lund [Fri, 29 Apr 2022 07:20:33 +0000 (09:20 +0200)]
gallium/xlib: fix stale comment
We haven't been doing what the comment says for about a decade, it's
about time to update the comment!
Fixes:
5f60a00743f ("st/glx: remove STENCIL_BITS, DEFAULT_SOFTWARE_DEPTH_BITS")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16213>
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