Simon Zeni [Mon, 16 Aug 2021 14:44:25 +0000 (10:44 -0400)]
i915: remove use of backtrace and backtrace_symbols
The function `debug_backtrace` relied on glibc specific functions, and is
unused unless someone manually patches the source to set DEBUG_BACKTRACE_SIZE
Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12108>
Nanley Chery [Wed, 21 Jul 2021 19:06:28 +0000 (12:06 -0700)]
anv/image: Don't assert that HiZ can be added
HiZ isn't yet enabled for Tile4/64.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Nanley Chery [Tue, 6 Apr 2021 18:45:22 +0000 (11:45 -0700)]
iris: Disable tiled memcpy for Tile4
ISL's tiled memcpy functions don't support it yet.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Jordan Justen [Wed, 17 Jun 2020 04:53:48 +0000 (21:53 -0700)]
iris: Disable the Y-tiled modifiers on XeHP+
I915_FORMAT_MOD_Y_TILED_CCS was already disabled for Xe+ due to a change
in the CCS layout. Disable the remaining Y-tiled modifiers since XeHP
lacks support for Y-tiling.
Rework:
* Nanley: Include Anuj's fix for the non-CCS modifiers.
* Nanley: Split out Anuj's fix into a separate if statement.
* Nanley: Rewrite commit message.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Nanley Chery [Fri, 23 Jul 2021 23:37:47 +0000 (16:37 -0700)]
intel/isl: Disable I915_FORMAT_MOD_Y_TILED on XeHP+
XeHP lacks support for Y-tiling.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Nanley Chery [Mon, 28 Jun 2021 22:32:16 +0000 (15:32 -0700)]
intel: Add underscores to HALIGN and VALIGN enums
The HALIGN enums for XeHP already have underscores. Make the other
HALIGN and VALIGN enums conform.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Nanley Chery [Mon, 12 Nov 2018 21:59:06 +0000 (13:59 -0800)]
intel: Update surface states for XeHP alignments
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Nanley Chery [Thu, 29 Jul 2021 23:25:06 +0000 (16:25 -0700)]
intel/isl: Use a switch for HALIGN/VALIGN encoding
Avoid using a sparse and relatively large array for HALIGN encoding.
Additionally, this provides validation of the input alignment values.
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Nanley Chery [Fri, 30 Jul 2021 17:50:59 +0000 (10:50 -0700)]
intel/isl: Fix halign/valign of uncompressed views
We're going to start asserting for valid halign/valign values during
surface state emission. Pre-SKL, isl_surf_get_uncompressed_surf creates
uncompressed surfaces with invalid halign/valign values - 1x1. Fix this
by replacing the call to isl_surf_get_image_surf with isl_surf_init,
passing in the uncompressed format up-front.
As we're no longer using isl_surf_get_image_surf, we also need to get
the x and y offset of the image ourselves. Instead of getting a
sample-based offset, then converting to elements later on, we use
isl_surf_get_image_offset_B_tile_el to get the offset in elements
up-front.
With the above two changes, the generic code after the else-block is no
longer needed for the single-layer-view code path. We move it and
specialize it to the if-block (which is executed SKL+ and handles
multi-layer views).
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Nanley Chery [Fri, 30 Jul 2021 21:31:05 +0000 (14:31 -0700)]
intel/blorp: Fix Gfx7 stencil surface state valign
Stencil on Gfx7 has a vertical alignment element of 8, but the largest
its surface state can express is 4. Apply the Gfx6 solution of changing
the alignment in blorp_surf_retile_w_to_y.
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Nanley Chery [Fri, 23 Jul 2021 16:02:06 +0000 (09:02 -0700)]
intel/blorp: Fix faked RGB image alignment on XeHP
On XeHP, NPOT and POT formatted surfaces will use different image
alignment units when emitting surface states. When BLORP fakes an RGB
image as RED, update the image alignment to prevent assert failures when
emitting surface states.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Nanley Chery [Mon, 12 Nov 2018 21:59:06 +0000 (13:59 -0800)]
intel: Support Tile4/64 in surface states
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Nanley Chery [Fri, 2 Nov 2018 21:47:37 +0000 (14:47 -0700)]
intel: Support Tile4/64 in depth/stencil state
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Nanley Chery [Fri, 2 Nov 2018 20:01:58 +0000 (13:01 -0700)]
intel/isl: Update tiling filter functions for XeHP
Enable the XeHP-specific tilings and restrict them to that platform.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Nanley Chery [Fri, 30 Jul 2021 00:04:14 +0000 (17:04 -0700)]
intel/isl: Use an allow-list in gfx6_filter_tiling
Try to avoid having to update isl_gfx6_filter_tiling when new tilings
are added for new platforms. Note that the allow-list uses
ISL_TILING_ANY_Y_MASK and thus assumes that no new Y-tilings will be
added in the future.
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Nanley Chery [Fri, 30 Jul 2021 00:16:44 +0000 (17:16 -0700)]
intel/isl: Drop ISL_SURF_USAGE_DISPLAY_*_BIT
We haven't used these since their introduction.
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Nanley Chery [Thu, 22 Jul 2021 22:11:01 +0000 (15:11 -0700)]
intel/isl: Drop extra assert on array_pitch_el_rows
ISL already asserts that the variable is a multiple of the tile height
via isl_assert_div.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Nanley Chery [Fri, 2 Nov 2018 20:01:58 +0000 (13:01 -0700)]
intel/isl: Size Tile64 surfaces with 4 dimensions
In order to size Tile64 surfaces correctly, make sure that the total
physical extent is arrayed. The code should handle 3D surfaces as well,
but is untested for now.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Nanley Chery [Mon, 12 Nov 2018 21:59:06 +0000 (13:59 -0800)]
intel/isl: Update image alignments on XeHP
Implement the new XeHP alignment rules for surface layout.
RENDER_SURFACE_STATE objects still need updating, but that's left for a
separate commit.
Rework:
* Nanley: Include Sagar's VALIGN fix for D16_UNORM.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Nanley Chery [Fri, 2 Nov 2018 20:01:58 +0000 (13:01 -0700)]
intel/isl: Define ISL_TILING_4/64 for XeHP
XeHP defines new tiling formats, Tile4 and Tile64. They are needed in
order to support depth/stencil surfaces and multisampling. Create new
ISL enums and define some initial tiling information in order to enable
them later on.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Nanley Chery [Tue, 23 Mar 2021 18:01:16 +0000 (11:01 -0700)]
intel/isl: Add msaa_layout param to isl_tiling_get_info
The additional parameter will be used by Tile64.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Jason Ekstrand [Wed, 21 Feb 2018 22:57:46 +0000 (14:57 -0800)]
intel/isl: Add more parameters to isl_tiling_get_info
They are not used yet but the layout of Yf and Ys tiles are dependent on
these parameters. While we're here, better document the function.
Rework:
* Nanley: Update crocus.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
Mike Blumenkrantz [Thu, 10 Jun 2021 10:34:10 +0000 (06:34 -0400)]
zink: only remove programs from hash tables on shader deletion if needed
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
Mike Blumenkrantz [Thu, 10 Jun 2021 10:31:42 +0000 (06:31 -0400)]
zink: set inlinable_uniforms_mask first when binding a shader
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
Mike Blumenkrantz [Thu, 10 Jun 2021 10:31:22 +0000 (06:31 -0400)]
zink: add some null checks for shader variant key generation
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
Mike Blumenkrantz [Thu, 10 Jun 2021 10:27:40 +0000 (06:27 -0400)]
zink: stop using dirty_shader_stages for shader binds
by only using this mask for variant updates, we can begin to do some
neat things
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
Mike Blumenkrantz [Thu, 10 Jun 2021 10:20:35 +0000 (06:20 -0400)]
zink: simplify a bitmask init
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
Mike Blumenkrantz [Thu, 10 Jun 2021 10:17:03 +0000 (06:17 -0400)]
zink: create compute programs on bind
this simplifies the launch_grid codepath and gets shader binds out
the shader update bitmask
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
Mike Blumenkrantz [Wed, 9 Jun 2021 23:38:27 +0000 (19:38 -0400)]
zink: avoid hashing shader stages multiple times for new gfx programs
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
Mike Blumenkrantz [Wed, 9 Jun 2021 23:14:35 +0000 (19:14 -0400)]
zink: split gfx shader cache based on stages present
this makes the pool of progs in a given hash smaller and also minimizes
the hashing required for a given program
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
Mike Blumenkrantz [Wed, 9 Jun 2021 23:14:26 +0000 (19:14 -0400)]
zink: track mask of bound gfx shader stages
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
Mike Blumenkrantz [Wed, 9 Jun 2021 22:42:26 +0000 (18:42 -0400)]
zink: inline program cache structs
derefs--
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12532>
Mike Blumenkrantz [Wed, 25 Aug 2021 01:56:25 +0000 (21:56 -0400)]
zink: return early when getting resource modifer if no modifier is used
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12534>
Mike Blumenkrantz [Wed, 25 Aug 2021 20:13:10 +0000 (16:13 -0400)]
zink: verify program key sizes before checking for default variant
currently keys for shaders are always the same size, but this will change
in the future, at which point the keysize becomes relevant
Reviewed-by: Hoe Hao Cheng <haochengho12907@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12547>
Michael Tang [Tue, 24 Aug 2021 02:00:55 +0000 (19:00 -0700)]
microsoft/compiler: Miscellaneous fixes from running clang-format
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12513>
Michael Tang [Tue, 24 Aug 2021 23:53:33 +0000 (16:53 -0700)]
microsoft/compiler: Emit a flat interpolation method for SV_SampleIndex
We do not want to set an interpolation method for vertex shader inputs.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12513>
Michael Tang [Tue, 24 Aug 2021 01:53:28 +0000 (18:53 -0700)]
microsoft/compiler: Set the SampleFrequency runtime metadata
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12513>
Michael Tang [Tue, 24 Aug 2021 01:48:50 +0000 (18:48 -0700)]
microsoft/compiler: More robustly handle setting Register=-1
This is the 'N/A mask' case in the DXIL disassembly.
This logic is taken from: https://github.com/microsoft/DirectXShaderCompiler/blob/
7c9e487afd17b7726229d8ceb3242a412134afe7/tools/clang/tools/dxcompiler/dxcdisassembler.cpp#L106
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12513>
Michael Tang [Tue, 24 Aug 2021 02:08:08 +0000 (19:08 -0700)]
microsoft/compiler: Add support for SV_SampleIndex intrinsic
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12513>
Alyssa Rosenzweig [Tue, 24 Aug 2021 20:44:28 +0000 (16:44 -0400)]
pan/bi: Fix format specifiers in disassembler
Flagged by cppcheck.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
Alyssa Rosenzweig [Tue, 24 Aug 2021 20:41:27 +0000 (16:41 -0400)]
pan/bi: Remove unused clause_start field
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
Alyssa Rosenzweig [Tue, 24 Aug 2021 20:40:54 +0000 (16:40 -0400)]
pan/bi: Assert l != NULL in bi_ra
Confuses cppcheck; indeed, the proof is confusing.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
Alyssa Rosenzweig [Tue, 24 Aug 2021 20:40:35 +0000 (16:40 -0400)]
pan/bi: Simplify condition
Flagged by cppcheck.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
Alyssa Rosenzweig [Tue, 24 Aug 2021 20:37:15 +0000 (16:37 -0400)]
panfrost: Remove unused functions
Flagged by cppcheck.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
Alyssa Rosenzweig [Tue, 24 Aug 2021 18:41:14 +0000 (14:41 -0400)]
panfrost: Remove stale TODOs and XXXs
These don't meaningfully apply but their comments never got updated.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
Alyssa Rosenzweig [Tue, 24 Aug 2021 18:40:24 +0000 (14:40 -0400)]
panfrost: Remove CACHE_LINE_SIZE #define
Not only is it unused, it's totally wrong. Not even a little right.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12530>
Erik Faye-Lund [Mon, 23 Aug 2021 12:37:42 +0000 (14:37 +0200)]
llvmpipe: rip out cylindrical wrap support
Acked-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12505>
Erik Faye-Lund [Mon, 23 Aug 2021 12:29:21 +0000 (14:29 +0200)]
softpipe: rip out cylindrical wrap support
This is never used, so let's just remove it.
Acked-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12505>
Erik Faye-Lund [Mon, 23 Aug 2021 12:25:07 +0000 (14:25 +0200)]
gallium/tgsi: rip out cylindrical wrap support
We never enable this feature, so let's rip it out completely.
Acked-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12505>
Erik Faye-Lund [Mon, 23 Aug 2021 12:11:52 +0000 (14:11 +0200)]
gallium/tgsi: rip out cylindrical wrap from ureg
We always pass zero to these arguments, so this feature isn't in use.
Acked-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12505>
Erik Faye-Lund [Mon, 23 Aug 2021 12:06:24 +0000 (14:06 +0200)]
gallium/tgsi: remove unused helper
Acked-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12505>
Erik Faye-Lund [Wed, 18 Aug 2021 09:40:51 +0000 (11:40 +0200)]
draw/llvmpipe: correct exponent calculation for negative z
If the z components here contain negative values, we'll end up with the
wrong maximum value.
This updated equation is taken from the D3D11 functional spec (section
15.10 Depth Bias), which is a bit more clear than the OpenGL spec.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12443>
Samuel Pitoiset [Tue, 17 Aug 2021 08:52:21 +0000 (10:52 +0200)]
radv: allow storage images with VK_FORMAT_E5B9G9R9_UFLOAT_PACK32 on GFX10.3+
It should be supported.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12543>
Rob Clark [Sat, 21 Aug 2021 17:58:58 +0000 (10:58 -0700)]
freedreno/a6xx: Fix a6xx gen4 compute shaders
I believe the addition of these new regs is related to the changes made
for LPAC ring, so let's key off of that.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12497>
Rob Clark [Sat, 21 Aug 2021 18:55:19 +0000 (11:55 -0700)]
freedreno/a6xx: Register updates for a6xx gen4
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12497>
Rob Clark [Sat, 21 Aug 2021 17:14:16 +0000 (10:14 -0700)]
freedreno/a6xx: Updates for tess_use_shared
The formula for calculating these two values seems to depend on
tess_use_shared, ie. a6xx_gen3 and a6xx_gen4 match. The existing
calculation matches a6xx_gen1 and a6xx_gen2.
The new formula is based on traces varying # of output (from VS)
varyings from (1..31)*vec4 and vertices from (1..31) and coming up
with something that matches the blob. Once hs_input_size*4 divided
by tcs_vertices_out goes above 64, this deviates a bit from the
blob, but AFAICT it is safe to pick a larger values.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12497>
Rob Clark [Wed, 18 Aug 2021 22:28:00 +0000 (15:28 -0700)]
freedreno/a6xx: Fix streamout with tess_use_shared
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12497>
Rob Clark [Sat, 21 Aug 2021 18:00:22 +0000 (11:00 -0700)]
freedreno/a6xx: Rast updates for a6xx gen3
Not really sure what these new regs are, but blob emits them as part of
rasterizer state starting with a650.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12497>
Rob Clark [Sat, 21 Aug 2021 18:54:30 +0000 (11:54 -0700)]
freedreno/a6xx: Register updates for a6xx gen3
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12497>
Rob Clark [Sat, 21 Aug 2021 17:27:02 +0000 (10:27 -0700)]
freedreno/a6xx: Set type for PC_HS_INPUT_SIZE
It is an unsigned integer.. display it as such.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12497>
Rob Clark [Fri, 20 Aug 2021 20:47:41 +0000 (13:47 -0700)]
freedreno/common: Fix comment typo
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12497>
Alyssa Rosenzweig [Tue, 10 Aug 2021 17:41:28 +0000 (13:41 -0400)]
panfrost: Raise maximum texture size
The hardware can handle much larger textures than we allowed. The game
"Cathedral" requires larger textures for some bizarre reason. Raise the
limit so the game runs, syncing MAX_MIP_LEVELS, the comments, and the CAPs.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Closes: #5203
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12312>
Daniel Schürmann [Wed, 23 Jun 2021 15:11:09 +0000 (17:11 +0200)]
aco: remove redundant s_and exec after nir_op_inot
Totals from 22585 (15.04% of 150170) affected shaders: (GFX10.3)
VGPRs: 1474048 -> 1473904 (-0.01%)
CodeSize:
155238876 ->
155187688 (-0.03%); split: -0.06%, +0.03%
MaxWaves: 385086 -> 385122 (+0.01%)
Instrs:
29297735 ->
29284442 (-0.05%); split: -0.08%, +0.04%
Latency:
675841742 ->
675764151 (-0.01%); split: -0.02%, +0.01%
InvThroughput:
174859037 ->
174854796 (-0.00%); split: -0.01%, +0.01%
VClause: 479790 -> 479781 (-0.00%); split: -0.01%, +0.00%
SClause: 1106900 -> 1106615 (-0.03%); split: -0.03%, +0.01%
Copies: 1829037 -> 1828042 (-0.05%); split: -0.09%, +0.03%
Branches: 859971 -> 859967 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 1341850 -> 1342356 (+0.04%); split: -0.01%, +0.04%
PreVGPRs: 1327322 -> 1327034 (-0.02%)
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11573>
Timur Kristóf [Wed, 25 Aug 2021 10:13:39 +0000 (12:13 +0200)]
aco: Fix to_uniform_bool_instr when operands are not suitable.
Don't attempt to transform uniform boolean instructions when
their operands are unsuitable. This can happen eg. due to other
optimizations that combine SALU instructions which clear out
the uniform instruction labels.
Cc: mesa-stable
Fixes:
8a32f57fff56b3b94f1b5589feba38016f39427c
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11573>
Lionel Landwerlin [Mon, 23 Aug 2021 13:45:20 +0000 (16:45 +0300)]
nir: prevent peephole from generating invalid NIR
We can't append instructions following a return/halt instruction
because the control flow helpers will modify the successor of the
block containing the return/halt. And the NIR validator enforces that
the return/halt must have the end of the function as successor.
This tends to happen following lower_shader_calls lowering which
inserts halts. This probably doesn't prevent the optimization, it'll
just happen in one of the return shaders after the halt has been
removed.
v2: Move prev block ending check earlier in the function (Daniel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12506>
Samuel Pitoiset [Wed, 25 Aug 2021 10:06:16 +0000 (12:06 +0200)]
ci: update the list of expected failures/skips for RADV
Against CTS 1.2.7.0.
Tested chips are Pitcairn, Polaris10, Navi14 and Sienna Cichlid.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12539>
Tomeu Vizoso [Fri, 6 Aug 2021 09:10:02 +0000 (11:10 +0200)]
iris/ci: Add manual jobs for tracking performance
Use Piglit's replay profile to measure and store the time that frames
take to render in the GPU.
This job won't run automatically in regular pipelines, but will be
triggered automatically by a script for every successful pre-merge
pipeline.
This is because we want to generate performance data for every relevant
commit merged in main, but we don't want to keep a device busy during
the pre-merge run.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12236>
Samuel Pitoiset [Tue, 24 Aug 2021 06:35:59 +0000 (08:35 +0200)]
nir/opt_algebraic: optimize fmax(-fmin(b, a), b) -> fmax(fabs(b), -a)
and fmin(-fmax(b, a)) to fmin(-fabs(b), -a).
fossils-db (Sienna Cichlid):
Totals from 34 (0.02% of 150170) affected shaders:
CodeSize: 388540 -> 387748 (-0.20%)
Instrs: 74621 -> 74423 (-0.27%)
Latency: 1039407 -> 1039011 (-0.04%)
InvThroughput: 208364 -> 208150 (-0.10%)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12519>
Dave Airlie [Wed, 25 Aug 2021 02:31:54 +0000 (22:31 -0400)]
crocus: add missing fs dirty on reduced prim change.
the reduced prim is used to decide some line antialiasing settings.
this fixes mesa-demos antialias
Fixes:
f3630548f1da ("crocus: initial gallium driver for Intel gfx 4-7")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12536>
Dave Airlie [Wed, 25 Aug 2021 02:00:47 +0000 (22:00 -0400)]
crocus: add missing line smooth bits.
Just noticed this in passing.
Fixes:
f3630548f1da ("crocus: initial gallium driver for Intel gfx 4-7")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12536>
Mike Blumenkrantz [Tue, 24 Aug 2021 22:32:17 +0000 (18:32 -0400)]
zink: fix pipeline caching
this was apparently always broken, but in a very, very subtle way
where the hash table would compare the current pipeline state against
itself instead of using the cache entry's state
Cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12535>
Mike Blumenkrantz [Tue, 24 Aug 2021 21:59:44 +0000 (17:59 -0400)]
zink: fix program init flag
this was accidentally !! instead of ! as intended
Fixes:
c4702204bc3 ("zink: optimize shader recalc")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12535>
Michael Tang [Fri, 20 Aug 2021 21:53:02 +0000 (14:53 -0700)]
spirv_to_dxil: Run nir_lower_tex during compilation
We need this to get e.g. a default lod for some instructions when it is
not provided.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12462>
Dave Airlie [Tue, 24 Aug 2021 21:28:54 +0000 (07:28 +1000)]
crocus: drop u_primconvert header.
This is just leftover.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12531>
Mike Blumenkrantz [Tue, 6 Apr 2021 14:29:28 +0000 (10:29 -0400)]
zink: add better TODO note for surface swizzles
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12529>
Mike Blumenkrantz [Tue, 6 Apr 2021 14:22:03 +0000 (10:22 -0400)]
zink: make void swizzle clamping util public
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12529>
Mike Blumenkrantz [Tue, 6 Apr 2021 14:20:27 +0000 (10:20 -0400)]
zink: make component mapping function a static inline
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12529>
Mike Blumenkrantz [Tue, 6 Apr 2021 14:18:41 +0000 (10:18 -0400)]
zink: move void format detection function to zink_format
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12529>
Mike Blumenkrantz [Mon, 23 Aug 2021 14:43:22 +0000 (10:43 -0400)]
nine: replace unnecessary dynamic-sized array with bitfield
PIPE_MAX_VERTEX_STREAMS is 4, so this can be simplified to reduce cpu usage
Reviewed-by: <Axel Davy davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12523>
Alyssa Rosenzweig [Tue, 17 Aug 2021 17:22:42 +0000 (17:22 +0000)]
panfrost: Take a ctx when submitting/destroying
This reduces the number of batch->ctx shenanigans we do, and in turn
should reduce raciness.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12366>
Ian Romanick [Mon, 14 Jun 2021 21:12:36 +0000 (14:12 -0700)]
spirv: Add support for SPV_KHR_integer_dot_product
v2 (Ivan): Add missing capability enum handling.
v3 (idr): Properly handle cases where dest_size != 32.
v4 (idr): Rewrite most of the error checking to use vtn_fail_if. Use
nir_ssa_def with vtn_push_nir_ssa instead of vtn_ssa_value with
vtn_push_ssa_value. All suggested by Jason. Massive rewrite of the
handling of packed 4x8 saturating opcodes. Based on some observations
made by Jason.
v5 (idr): Remove some debugging cruft accidentally added in v4. Noticed
by Jason.
v6: Emit packed versions of vectored instructions when possible.
Suggested by Jason.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12142>
Ian Romanick [Mon, 14 Jun 2021 21:11:08 +0000 (14:11 -0700)]
spirv: Update headers and metadata from latest Khronos commit
This corresponds to e7b49d7 ("Implement SPV_INTEL_optnone extension
(#230)") in https://github.com/KhronosGroup/SPIRV-Headers.
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12142>
Ian Romanick [Fri, 20 Aug 2021 00:52:54 +0000 (17:52 -0700)]
nir/algebraic: Add some extract optimizations
These help quite a bit when vectored versions of SpvOpSDotKHR and
friends are emitted as packed versions and then lowered.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12142>
Ian Romanick [Wed, 9 Jun 2021 21:53:49 +0000 (14:53 -0700)]
nir/algebraic: Add lowering for dot_4x8 instructions
v2: Fix copy-and-paste bugs in lowering patterns.
v3: Add has_sudot_4x8 flag. Requested by Rhys.
v4: Since the names of the opcodes changed from dp4 to dot_4x8, also
change the names of the lowering helpers. Suggested by Jason.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12142>
Ian Romanick [Wed, 24 Feb 2021 02:46:53 +0000 (18:46 -0800)]
intel/compiler: Basic support for DP4A instruction
v2: Very significant rebase on changes to previous commits.
Specifically, brw_fs_nir.cpp changes were pretty much rewritten from
scratch after changing the NIR opcode names and types.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12142>
Ian Romanick [Wed, 24 Feb 2021 03:12:49 +0000 (19:12 -0800)]
nir/algebraic: Basic patterns for dot_4x8
v2: Add and modify patterns to let constant folding do better.
v3: Remove '(is_not_zero)' from the patterns that try to combine
addends. I honestly don't know why I had it there in the first place,
and nothing in my deep git logs could help clue me in. Noticed by
Alyssa. Remover patterns that detect open-coded udot_4x8. Suggested by
Alyssa and Jason. Add missing sudot_4x8 patterns.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12142>
Ian Romanick [Wed, 24 Feb 2021 01:33:04 +0000 (17:33 -0800)]
nir/opcodes: Add integer dot-product opcodes
Six opcodes are added: sdot_4x8_iadd, udot_4x8_uadd, sudot_4x8_iadd,
sdot_4x8_iadd_sat, udot_4x8_uadd_sate, and sudot_4x8_iadd_sat. These
represent the combinations of integer dot-product and add that operate
on packed source vectors. That is, the four 8-bit values for each
vector is stored in a single 32-bit integer.
Some hardware may prefer to operate on unpacked byte vectors. When such
hardware comes to Mesa, we'll have to figure out how to name things.
v2: Add nir_op_iudp4a and nir_op_iudp4a_sat instructions. These opcodes
are not 2-source commutative.
v3: Rename all opcodes to be more like some existing 4x8 opcodes.
Suggested by Timur. Change type of packed vector sources to uint32,
change types of constant folding variables to have explicit size, and
delete some extra casts. All suggested by Jason.
v4: Fix typo previously noticed by Alyssa but missed in v2.
v5: Add has_sudot_4x8 flag. Requested by Rhys.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12142>
Ian Romanick [Thu, 29 Jul 2021 01:16:24 +0000 (18:16 -0700)]
nir/lower_bit_size: Support add_sat and sub_sat
Without this, lowered saturating ALU instructions would only clamp to
the range of the new type instead of the range of the old type.
v2: Use nir_iclamp. Suggested by Jason. Use new
u_{int,uint}N_{min,max}() helpers.
Fixes:
090e2824079 ("nir: Add a saturated unsigned integer add opcode")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12142>
Alyssa Rosenzweig [Tue, 17 Aug 2021 17:16:54 +0000 (17:16 +0000)]
panfrost: Replace writers pointer with hash table
This ensures each context can have a separate batch writing a resource
and we don't race trying to flush each other's batches. Unfortunately
the extra hash table operations regress draw-overhead numbers by about
8% but I'd rather eat the overhead and have an obviously correct
implementation than leave known buggy code in tree.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12528>
Alyssa Rosenzweig [Tue, 17 Aug 2021 17:06:56 +0000 (17:06 +0000)]
panfrost: Remove writer = NULL assignments
These already happened.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12528>
Alyssa Rosenzweig [Tue, 17 Aug 2021 16:46:46 +0000 (16:46 +0000)]
panfrost: Remove rsrc->track.users
No longer needed.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12528>
Alyssa Rosenzweig [Tue, 17 Aug 2021 16:45:17 +0000 (16:45 +0000)]
panfrost: Prefer batch->resources to rsrc->users
This expresses the semantic of the flush only applying to batches within
the context, not globally, in line with OpenGL's multithreading rules.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12528>
Alyssa Rosenzweig [Tue, 17 Aug 2021 16:40:53 +0000 (16:40 +0000)]
panfrost: Add foreach_batch iterator
Using the active mask.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12528>
Alyssa Rosenzweig [Tue, 17 Aug 2021 16:39:40 +0000 (16:39 +0000)]
panfrost: Maintain a bitmap of active batches
This is on the context, so no concurrency issues. This will allow us to
efficiently iterate active batches.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12528>
Alyssa Rosenzweig [Tue, 17 Aug 2021 16:05:07 +0000 (16:05 +0000)]
panfrost: Cache number of users of a resource
This can be tracked efficiently with atomics, and reduces the places we
use the rsrc->track.users bitmap which has concurrency issues.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12528>
Alyssa Rosenzweig [Tue, 17 Aug 2021 15:59:07 +0000 (15:59 +0000)]
panfrost: Switch resources from an array to a set
This will help us reduce shared state and simplify multithreading, at
the expense of additional CPU overhead.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12528>
Mike Blumenkrantz [Wed, 9 Jun 2021 21:11:42 +0000 (17:11 -0400)]
zink: stop referencing framebuffers
this is a waste of cycles now that surfaces are accurately tracked;
no-attachment fbs are still deferred to avoid premature deletion
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12429>
Mike Blumenkrantz [Tue, 24 Aug 2021 15:28:22 +0000 (11:28 -0400)]
zink: defer deletion of no-attachment framebuffers
the ref on these is owned by the context, so defer deletion to avoid
premature destruction if the fb might be in use
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12429>
Alyssa Rosenzweig [Mon, 16 Aug 2021 23:55:50 +0000 (23:55 +0000)]
panfrost: Inline add_fbo_bos
Only used once, it's just complicating the batch cache interface.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12525>
Alyssa Rosenzweig [Mon, 16 Aug 2021 23:53:07 +0000 (23:53 +0000)]
panfrost: Remove get_fresh_batch
Unused, and of dubious value.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12525>
projects / platform / upstream / mesa.git / log