Emil Velikov [Thu, 11 Jun 2015 10:31:40 +0000 (11:31 +0100)]
egl/haiku: remove commented out code
It serves little to no purpose. As the driver gets updated, one can
look at the existing implementation (dri2) for reference rather than
letting the commented functions bitrot.
Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Thu, 11 Jun 2015 10:24:17 +0000 (11:24 +0100)]
egl/haiku: use correct version variable
Earlier commit folded the two separate variables into one, but forgot to
update the haiku driver.
Fixes:
0e4b564ef28(egl: combine VersionMajor and VersionMinor into one
variable)
Cc: Marek Olšák <marek.olsak@amd.com>>
Cc: Alexander von Gluck IV <kallisti5@unixzen.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Jose Fonseca [Fri, 12 Jun 2015 11:13:41 +0000 (12:13 +0100)]
trace: Add missing p_compiler.h include.
For boolean.
Trivial.
Francisco Jerez [Wed, 10 Jun 2015 11:40:33 +0000 (14:40 +0300)]
i965/fs: Remove one more fixed brw_null_reg() from the visitor.
Instead use fs_builder::null_reg_f() which has the correct register
width. Avoids the assertion failure in fs_builder::emit() hit by the
"ES3-CTS.shaders.loops.for_dynamic_iterations.unconditional_break_fragment"
GLES3 conformance test introduced by
4af4cfba9ee1014baa4a777660fc9d53d57e4c82.
Reported-and-reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Tue, 9 Jun 2015 16:20:58 +0000 (09:20 -0700)]
Revert "i965: Advertise a line width of 40.0 on Cherryview and Skylake."
This reverts commit
f3b709c0ac073cd0ec90a3a0d91d1ee94668e043.
The "dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_4.
interpolation.lines_wide" test appears to be broken on Cherryview when
we expose line widths greater than 12.0. I'm not sure why.
For now, just go back to the limits we used on older platforms.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90902
Acked-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Wed, 10 Jun 2015 08:46:13 +0000 (01:46 -0700)]
i965: Re-index SSA definitions before printing NIR code.
This makes the SSA definitions use sequential numbers (0, 1, 2, ...)
instead of seemingly random ones. There's not much point normally,
but it makes debug output much easier to read.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Brian Paul [Wed, 10 Jun 2015 16:59:37 +0000 (10:59 -0600)]
gallium: remove explicit values from PIPE_CAP_ enums
The other PIPE_CAPF_ and PIPE_SHADER_CAP_ enums don't have explicit values.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Jose Fonseca [Thu, 11 Jun 2015 12:32:21 +0000 (13:32 +0100)]
mesa/main: Don't use ONCE_FLAG_INIT as a r-value.
It should only be used as an initializer expression.
Trivial, and fixes Windows builds.
Nevertheless, overwriting an once_flag like this seems dangerous and
should be revised.
Iago Toral Quiroga [Thu, 11 Jun 2015 06:49:46 +0000 (08:49 +0200)]
i965/gen8: Fix antialiased line rendering with width < 1.5
The same fix Marius implemented for gen6 (commit
a9b04d8a) and
gen7 (commit
24ecf37a).
Also, we need the same code to handle special cases of line width
in gen6, gen7 and now gen8, so put that in the helper function
we use to compute the line width.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Martin Peres [Tue, 26 May 2015 12:32:21 +0000 (15:32 +0300)]
glsl: fix constructing a vector from a matrix
Without this patch, the following constructs (not an extensive list)
would crash mesa:
- mat2 foo = mat2(1); vec4 bar = vec4(foo);
- mat3 foo = mat3(1); vec4 bar = vec4(foo);
- mat3 foo = mat3(1); ivec4 bar = ivec4(foo);
The first case is explicitely allowed by the GLSL spec, as seen on
page 101 of the GLSL 4.40 spec:
"vec4(mat2) // the vec4 is column 0 followed by column 1"
The other cases are implicitely allowed also.
The actual changes are quite minimal. We first split each column of
the matrix to a list of vectors and then use them to initialize the
vector. An additional check to make sure that we are not trying to
copy 0 elements of a vector fix the (i)vec4(mat3) case as the last
vector (3rd column) is not needed at all.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Martin Peres <martin.peres@linux.intel.com>
Tapani Pälli [Wed, 6 May 2015 10:43:54 +0000 (13:43 +0300)]
mesa/es3.1: enable DRAW_INDIRECT_BUFFER_BINDING for gles3.1
(increases ES31-CTS.draw_indirect.basic.* passing tests)
v2: only expose DRAW_INDIRECT_BUFFER_BINDING for GL core + ES3.1
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Juha-Pekka Heikkila [Fri, 20 Mar 2015 13:40:26 +0000 (15:40 +0200)]
mesa/main: avoid null access in format_array_table_init()
If _mesa_hash_table_create failed we'd get null pointer. Report
error and go away.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Juha-Pekka Heikkila [Fri, 20 Mar 2015 13:13:14 +0000 (15:13 +0200)]
mesa/main: Remove _mesa_HashClone()
I didn't find this being used anywhere.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Alexander Monakov [Tue, 9 Jun 2015 17:58:22 +0000 (20:58 +0300)]
i965: do_blit_drawpixels: decode array formats
Correct a regression introduced by commit
922c0c9fd526 by converting "array
format", if received from _mesa_format_from_format_and_type, to mesa_format.
References: https://bugs.freedesktop.org/show_bug.cgi?id=90839
Signed-off-by: Alexander Monakov <amonakov@gmail.com>
Tested-by: AnAkkk <anakin.cs@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
Iago Toral Quiroga [Wed, 10 Jun 2015 07:07:32 +0000 (09:07 +0200)]
i965: do not round line width when multisampling or antialiaing are enabled
In commit
fe74fee8fa721a we rounded the line width to the nearest integer to
match the GLES3 spec requirements stated in section 13.4.2.1, but that seems
to break a dEQP test that renders wide lines in some multisampling scenarios.
Ian noted that the Open 4.4 spec has the following similar text:
"The actual width of non-antialiased lines is determined by rounding the
supplied width to the nearest integer, then clamping it to the
implementation-dependent maximum non-antialiased line width."
and suggested that when ES removed antialiased lines, they removed
"non-antialised" from that paragraph but probably should not have.
Going by that note, this patch restricts the quantization implemented in
fe74fee8fa721a only to regular aliased lines. This seems to keep the
tests fixed with that commit passing while fixing the broken test.
v2:
- Drop one of the clamps (Ken, Marius)
- Add a rule to prevent advertising line widths that when rounded go beyond
the limits allowed by the hardware (Ken)
- Update comments in the code accordingly (Ian)
- Put the code in a utility function (Ian)
Fixes:
dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_max.primitives.lines_wide
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90749
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Kenneth Graunke [Tue, 9 Jun 2015 21:33:47 +0000 (14:33 -0700)]
i965: Momentarily pretend to support ARB_texture_stencil8 for blits.
Broadwell's stencil blitting code attempts to bind a renderbuffer as a
texture, using dd->BindRenderbufferTexImage().
This calls _mesa_init_teximage_fields(), which then attempts to set
img->_BaseFormat = _mesa_base_tex_format(ctx, internalFormat), which
assert fails if internalFormat is GL_STENCIL_INDEX8 but
ARB_texture_stencil8 is unsupported.
To work around this, just pretend to support the extension momentarily,
during the blit. Meta has already munged a variety of other things in
the context (including the API!), so it's not that much worse than what
we're already doing.
Fixes regressions since commit
f7aad9da20b13c98f77d6a690b327716f39c0a47
(mesa/teximage: use correct extension for accept stencil texture.).
v2: Add an XXX comment explaining the situation (requested by Jason
Ekstrand and Martin Peres), and an assert that we don't support
the extension so we remember to remove this hack (requested by
Neil Roberts).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Brian Paul [Wed, 10 Jun 2015 13:28:40 +0000 (07:28 -0600)]
llvmpipe: simplify lp_resource_copy()
Just implement it in terms of util_resource_copy_region(). Both the
original code and util_resource_copy_region() boil down to mapping,
calling util_copy_box() and unmapping.
No piglit regressions. This will also help to implement GL_ARB_copy_image.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Tapani Pälli [Tue, 9 Jun 2015 09:26:48 +0000 (12:26 +0300)]
mesa: add GL_RED, GL_RG support for floating point textures
Mesa supports EXT_texture_rg and OES_texture_float. This patch adds
support for using unsized enums GL_RED and GL_RG for floating point
targets and writes proper checks for internalformat when format is
GL_RED or GL_RG and type is of GL_FLOAT or GL_HALF_FLOAT.
Later, internalformat will get adjusted by adjust_for_oes_float_texture
after these checks.
v2: simplify to check vs supported enums
v3: follow the style and break out if internalFormat ok (Kenneth)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90748
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tapani Pälli [Mon, 8 Jun 2015 11:53:26 +0000 (14:53 +0300)]
mesa: allow unsized formats GL_RG, GL_RED for GLES 3.0 with half float
v2: && -> ||, we enable on gles3 or if ARB_texture_rg is enabled
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90748
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Tue, 9 Jun 2015 06:53:55 +0000 (16:53 +1000)]
glsl: remove restriction on unsized arrays in GLSL ES 3.10
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Dave Airlie [Wed, 10 Jun 2015 03:51:59 +0000 (13:51 +1000)]
st/dri: check pscreen is valid before querying param
we don't check the validity of pscreen until dri_init_screen_helper
hit this trying to init glamor on a device with no driver (udl).
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 10 Jun 2015 03:26:56 +0000 (13:26 +1000)]
nouveau: set imported buffers to what the kernel gives us
When we import a dma-buf fd from another driver the kernel
gives us the right info, and this trashes it.
Convert the kernel bo flags into the domain flags.
This helps getting reverse prime and glamor working.
Cc: mesa-stable@lists.freedesktop.org
Acked-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Eric Anholt [Sun, 7 Jun 2015 19:02:02 +0000 (12:02 -0700)]
vc4: Drop qir include from vc4_screen.h
We didn't need any of it except for the list header, and qir.h pulls in
nir.h, which is not really interesting to winsys.
Eric Anholt [Wed, 3 Jun 2015 17:18:04 +0000 (10:18 -0700)]
vc4: Drop subdirectory in vc4 build.
Just because we put the source in a subdir, doesn't mean we need helper
libraries in the build. This will also simplify the Android build setup.
Eric Anholt [Mon, 1 Jun 2015 19:50:49 +0000 (12:50 -0700)]
vc4: Update to current kernel validation code.
After profiling on real hardware, I found a few ways to cut down the
kernel overhead.
Chih-Wei Huang [Wed, 20 May 2015 03:25:39 +0000 (11:25 +0800)]
android: build with libcxx on android lollipop
On Lollipop, apparently stlport is gone and libcxx must be used instead.
We still support stlport when building on earlier android releases.
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Reviewed-by: Eric Anholt <eric@anholt.net>
Chih-Wei Huang [Wed, 20 May 2015 03:25:34 +0000 (11:25 +0800)]
android: enable the radeonsi driver
Based on the nice work of Paulo Sergio Travaglia <pstglia@gmail.com>.
The main modifications are:
- Include paths for LLVM header files and shared/static libraries
- Set C++ flag "c++11" to avoid compiling errors on LLVM header files
- Set defines for LLVM
- Add GALLIVM source files
- Changes path of libelf library for lollipop
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Acked-by: Eric Anholt <eric@anholt.net>
Chih-Wei Huang [Wed, 20 May 2015 03:25:33 +0000 (11:25 +0800)]
android: generate files by $(call es-gen)
Use the pre-defined macro es-gen to generate new added files
instead of writing new rules manually. The handmade rules
that may generate the files before the directory is created
result in such an error:
/bin/bash: out/target/product/x86/gen/STATIC_LIBRARIES/libmesa_st_mesa_intermediates/main/format_pack.c: No such file or directory
make: *** [out/target/product/x86/gen/STATIC_LIBRARIES/libmesa_st_mesa_intermediates/main/format_pack.c] Error 1
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Reviewed-by: Eric Anholt <eric@anholt.net>
Chih-Wei Huang [Wed, 20 May 2015 03:25:30 +0000 (11:25 +0800)]
android: try to load gallium_dri.so directly
This avoids needing hardlinks between all of the DRI driver .so names,
since we're the only loader on the system.
v2: Add early exit on success (like previous block) and log message on
failure.
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Reviewed-by: Eric Anholt <eric@anholt.net>
Chih-Wei Huang [Wed, 20 May 2015 03:25:29 +0000 (11:25 +0800)]
android: Depend on gallium_dri from EGL, instead of linking in gallium.
The Android gallium build used to use gallium_egl, which was removed back
in March. Instead, we will now use a normal Mesa libEGL loader with
dlopen()ing of a DRI module.
v2: add a clean step to rebuild all dri modules properly.
v3: Squish the 2 patches doing this together (change by anholt).
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Reviewed-by: Eric Anholt <eric@anholt.net>
Chih-Wei Huang [Wed, 20 May 2015 03:25:28 +0000 (11:25 +0800)]
android: add rules to build a gallium_dri.so
This single .so includes all of the enabled gallium drivers.
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Reviewed-by: Eric Anholt <eric@anholt.net>
Chih-Wei Huang [Wed, 20 May 2015 03:25:27 +0000 (11:25 +0800)]
android: add rules to build gallium/state_trackers/dri
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Reviewed-by: Eric Anholt <eric@anholt.net>
Chih-Wei Huang [Wed, 20 May 2015 03:25:26 +0000 (11:25 +0800)]
android: export more dirs from libmesa_dri_common
The include paths of libmesa_dri_common are also used by modules
that need libmesa_dri_common.
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Reviewed-by: Eric Anholt <eric@anholt.net>
Chih-Wei Huang [Wed, 20 May 2015 03:25:25 +0000 (11:25 +0800)]
android: loader: export the path to be included
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Reviewed-by: Eric Anholt <eric@anholt.net>
Ben Widawsky [Mon, 8 Jun 2015 21:52:07 +0000 (14:52 -0700)]
i965/gen9: Use raw PS invocation count for queries
Previously the number needed to be divided by 4 to get the proper results. Now
the hardware does the right thing. Through experimentation it seems Braswell
(CHV) does also need the division by 4.
Fixes piglit test:
arb_pipeline_statistics_query-frag
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Brian Paul [Tue, 9 Jun 2015 15:14:17 +0000 (09:14 -0600)]
glsl: fix comment typo: s/accpet/accept/
Brian Paul [Fri, 5 Jun 2015 14:00:09 +0000 (08:00 -0600)]
mesa: remove some MAX_NV_FRAGMENT_PROGRAM_* macros
GL_NV_fragment_program support was removed a while ago. This is just
some clean-up.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Sat, 6 Jun 2015 19:08:00 +0000 (12:08 -0700)]
fs/reg_allocate: Remove the MRF hack helpers from fs_visitor
These are helpers that only exist in this one file. No reason to put them
in the visitor.
Reviewed-by: Neil Roberts <neil@linux.intel.com>
Jason Ekstrand [Sat, 6 Jun 2015 19:15:30 +0000 (12:15 -0700)]
i965/fs: Don't let the EOT send message interfere with the MRF hack
Previously, we just put the message for the EOT send as high in the file as
it would go. This is because the register pre-filling hardware will stop
all over the early registers in the file in preparation for the next thread
while you're still sending the last message. However, if something happens
to spill, then the MRF hack interferes with the EOT send message and, if
things aren't scheduled nicely, will stomp on it.
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90520
Reviewed-by: Neil Roberts <neil@linux.intel.com>
Jose Fonseca [Tue, 9 Jun 2015 13:43:21 +0000 (14:43 +0100)]
rtasm: Generalize executable memory allocator to all Unices.
We're only using fairly portable standard Unix calls here, so might as
well save ourselves future trouble by enabling on all Unices by default.
https://bugs.freedesktop.org/show_bug.cgi?id=90904
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Francisco Jerez [Wed, 3 Jun 2015 15:17:50 +0000 (18:17 +0300)]
i965/fs: Drop fs_inst::force_uncompressed.
This is now unused. Saves a whole bit of memory per instruction.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Mon, 8 Jun 2015 16:32:18 +0000 (19:32 +0300)]
i965/fs: Remove dead IR construction code from the visitor.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 15:16:30 +0000 (18:16 +0300)]
i965/fs: Migrate test_fs_cmod_propagation to the IR builder.
v2: Use set_predicate/condmod. Use fs_builder::OPCODE instead of
::emit.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 15:15:22 +0000 (18:15 +0300)]
i965/fs: Migrate test_fs_saturate_propagation to the IR builder.
v2: Use set_saturate. Use fs_builder::OPCODE instead of ::emit.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 18:02:57 +0000 (21:02 +0300)]
i965/fs: Migrate translation of NIR texturing instructions to the IR builder.
v2: Don't remove assignments of base_ir just yet.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 18:01:32 +0000 (21:01 +0300)]
i965/fs: Migrate translation of NIR intrinsics to the IR builder.
v2: Use fs_builder::SEL instead of ::emit. Use set_condmod().
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 17:59:26 +0000 (20:59 +0300)]
i965/fs: Migrate translation of NIR ALU instructions to the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 17:57:12 +0000 (20:57 +0300)]
i965/fs: Migrate translation of NIR control flow to the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 18:17:36 +0000 (21:17 +0300)]
i965/fs: Migrate NIR variable handling to the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 18:12:49 +0000 (21:12 +0300)]
i965/fs: Migrate NIR emit_percomp() to the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 18:08:43 +0000 (21:08 +0300)]
i965/fs: Migrate CS terminate message to the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 19:43:00 +0000 (22:43 +0300)]
i965/fs: Migrate VS output writes to the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 18:07:52 +0000 (21:07 +0300)]
i965/fs: Migrate FS framebuffer writes to the IR builder.
The explicit call to fs_builder::group() in emit_single_fb_write() is
required by the builder (otherwise the assertion in fs_builder::emit()
would fail) because the subsequent LOAD_PAYLOAD and FB_WRITE
instructions are in some cases emitted with a non-native execution
width. The previous code would always use the channel enables for the
first quarter, which is dubious but probably worked in practice
because FB writes are never emitted inside non-uniform control flow
and we don't pass the kill-pixel mask via predication in the cases
where we have to fall-back to SIMD8 writes.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 18:07:34 +0000 (21:07 +0300)]
i965/fs: Migrate FS alpha test to the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 17:45:54 +0000 (20:45 +0300)]
i965/fs: Migrate FS discard handling to the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 18:56:20 +0000 (21:56 +0300)]
i965/fs: Migrate FS gl_SamplePosition/ID computation code to the IR builder.
v2: Use fs_builder::AND/SHR/MOV instead of ::emit.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 18:54:54 +0000 (21:54 +0300)]
i965/fs: Migrate FS interpolation code to the IR builder.
v2: Fix some preexisting trivial codestyle issues.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 17:43:09 +0000 (20:43 +0300)]
i965/fs: Migrate shader time to the IR builder.
v2: Change null register destination type to UD so it can be compacted.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 18:06:13 +0000 (21:06 +0300)]
i965/fs: Migrate untyped surface read and atomic to the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 18:05:28 +0000 (21:05 +0300)]
i965/fs: Migrate texturing implementation to the IR builder.
v2: Remove tabs from modified lines.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 19:22:39 +0000 (22:22 +0300)]
i965/fs: Migrate pull constant loads to the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 19:22:10 +0000 (22:22 +0300)]
i965/fs: Migrate Gen4 send dependency workarounds to the IR builder.
v2: Change brw_null_reg() to bld.null_reg_f().
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 17:49:32 +0000 (20:49 +0300)]
i965/fs: Migrate lower_integer_multiplication to the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 17:36:47 +0000 (20:36 +0300)]
i965/fs: Migrate lower_load_payload to the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 16:05:54 +0000 (19:05 +0300)]
i965/fs: Migrate register spills and fills to the IR builder.
Yes, it's incorrect to use the 0-th channel enable group
unconditionally without considering the execution and regioning
controls of the instruction that uses the spilled value, but it
matches the previous behaviour exactly, the builder just makes the
preexisting problem more obvious because emitting an instruction of
non-native SIMD width without having called .group() or .exec_all()
explicitly would have led to an assertion failure.
I'll fix the problem in a follow-up series, as the solution is going
to be non-trivial.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 18:05:45 +0000 (21:05 +0300)]
i965/fs: Migrate try_replace_with_sel to the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 17:46:31 +0000 (20:46 +0300)]
i965/fs: Migrate opt_sampler_eot to the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 16:51:47 +0000 (19:51 +0300)]
i965/fs: Migrate opt_peephole_sel to the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 16:33:44 +0000 (19:33 +0300)]
i965/fs: Create and emit instructions in one step in opt_peephole_sel.
This simplifies opt_peephole_sel() slightly by emitting the SEL
instructions immediately after they are created, what makes the
sel_inst and mov_imm_inst arrays unnecessary and will make it possible
to get rid of the explicit inserts when the pass is migrated to the IR
builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Thu, 4 Jun 2015 13:13:35 +0000 (16:13 +0300)]
i965/fs: Migrate opt_cse to the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Thu, 4 Jun 2015 13:09:47 +0000 (16:09 +0300)]
i965/fs: Don't drop force_writemask_all and _sechalf when copying a CSE temporary.
LOAD_PAYLOAD instructions need the same treatment as any other
generator instructions, at least FB writes and typed surface messages
will need a payload built with non-zero execution controls.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Thu, 4 Jun 2015 13:05:33 +0000 (16:05 +0300)]
i965/vec4: Take into account all instruction fields in CSE instructions_match().
Most of these fields affect the behaviour of the instruction, but
apparently we currently don't CSE the kind of instructions for which
these fields could make a difference in the VEC4 back-end. That's
likely to change soon though when we start using send-from-GRF for
texture sampling and surface access messages.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Thu, 4 Jun 2015 12:09:10 +0000 (15:09 +0300)]
i965/fs: Take into account all instruction fields in CSE instructions_match().
Most of these fields affect the behaviour of the instruction so it
could actually break the program if we CSE a pair of otherwise
matching instructions with different values of these fields.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 15:22:17 +0000 (18:22 +0300)]
i965/fs: Migrate opt_peephole_predicated_break to the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 15:20:50 +0000 (18:20 +0300)]
i965/fs: Migrate opt_combine_constants to the IR builder.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 16:59:44 +0000 (19:59 +0300)]
i965/fs: Allocate a common IR builder object in fs_visitor.
v2: Call fs_builder::at_end() to point the builder at the end of the
program explicitly.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 22 Apr 2015 11:02:47 +0000 (14:02 +0300)]
i965/fs: Introduce FS IR builder.
The purpose of this change is threefold: First, it improves the
modularity of the compiler back-end by separating the functionality
required to construct an i965 IR program from the rest of the visitor
god-object, what in turn will reduce the coupling between other
components and the visitor allowing a more modular design. This patch
doesn't yet remove the equivalent functionality from the visitor
classes, as it involves major back-end surgery.
Second, it improves consistency between the scalar and vector
back-ends. The FS and VEC4 builders can both be used to generate
scalar code with a compatible interface or they can be used to
generate natural vector width code -- 1 or 4 components respectively.
Third, the approach to IR construction is somewhat different to what
the visitor classes currently do. All parameters affecting code
generation (execution size, half control, point in the program where
new instructions are inserted, etc.) are encapsulated in a stand-alone
object rather than being quasi-global state (yes, anything defined in
one of the visitor classes is effectively global due to the tight
coupling with virtually everything else in the compiler back-end).
This object is lightweight and can be copied, mutated and passed
around, making helper IR-building functions more flexible because they
can now simply take a builder object as argument and will inherit its
IR generation properties in exactly the same way that a discrete
instruction would from the same builder object.
The emit_typed_write() function from my image-load-store branch is an
example that illustrates the usefulness of the latter point: Due to
hardware limitations the function may have to split the untyped
surface message in 8-wide chunks. That means that the several
functions called to help with the construction of the message payload
are themselves required to set the execution width and half control
correctly on the instructions they emit, and to allocate all registers
with half the default width. With the previous approach this would
require the used helper functions to be aware of the parameters that
might differ from the default state and explicitly set the instruction
bits accordingly. With the new approach they would get a modified
builder object as argument that would influence all instructions
emitted by the helper function as if it were the default state.
Another example is the fs_visitor::VARYING_PULL_CONSTANT_LOAD()
method. It doesn't actually emit any instructions, they are simply
created and inserted into an exec_list which is returned for the
caller to emit at some location of the program. This sort of two-step
emission becomes unnecessary with the builder interface because the
insertion point is one more of the code generation parameters which
are part of the builder object. The caller can simply pass
VARYING_PULL_CONSTANT_LOAD() a modified builder object pointing at the
location of the program where the effect of the constant load is
desired. This two-step emission (which pervades the compiler back-end
and is in most cases redundant) goes away: E.g. ADD() now actually
adds two registers rather than just creating an ADD instruction in
memory, emit(ADD()) is no longer necessary.
v2: Drop scalarizing VEC4 builder.
v3: Take a backend_shader as constructor argument. Improve handling
of debug annotations and execution control flags.
v4: Drop Gen6 IF with inline comparison. Rename "instr" variable.
Initialize cursor to NULL by default and add method to explicitly
point the builder at the end of the program.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 3 Jun 2015 18:24:50 +0000 (21:24 +0300)]
i965: Define consistent interface to enable instruction result saturation.
v2: Use set_ prefix.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Wed, 3 Jun 2015 18:24:18 +0000 (21:24 +0300)]
i965: Define consistent interface to enable instruction conditional modifiers.
v2: Use set_ prefix.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Wed, 3 Jun 2015 18:23:46 +0000 (21:23 +0300)]
i965: Define consistent interface to predicate an instruction.
v2: Use set_ prefix.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Mon, 8 Jun 2015 11:49:31 +0000 (14:49 +0300)]
mesa: Drop include of simple_list.h from mtypes.h.
simple_list.h defines a number of macros with short non-namespaced
names that can easily collide with other declarations (first_elem,
last_elem, next_elem, prev_elem, at_end), and according to the comment
it was only being included because of struct simple_node, which is no
longer used in this file.
Reviewed-by: Brian Paul <brianp@vmware.com>
Francisco Jerez [Mon, 8 Jun 2015 11:48:29 +0000 (14:48 +0300)]
dri/nouveau: Include simple_list.h explicitly in nv*_state_tnl.c.
Reviewed-by: Brian Paul <brianp@vmware.com>
Francisco Jerez [Mon, 8 Jun 2015 11:47:17 +0000 (14:47 +0300)]
tnl: Include simple_list.h explicitly in t_context.c.
Reviewed-by: Brian Paul <brianp@vmware.com>
Francisco Jerez [Mon, 8 Jun 2015 11:46:58 +0000 (14:46 +0300)]
mesa: Include simple_list.h explicitly in errors.c.
This seems to be the only user of simple_list in core mesa not
including the header explicitly.
Reviewed-by: Brian Paul <brianp@vmware.com>
Dave Airlie [Sun, 5 Apr 2015 06:48:47 +0000 (16:48 +1000)]
mesa/teximage: use correct extension for accept stencil texture.
This was using the wrong extension, ARB_stencil_texturing
doesn't mention any changes in this area.
Fixes "dEQP-GLES3.functional.fbo.completeness.renderable.texture.
stencil.stencil_index8."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90751
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Wed, 15 Apr 2015 05:06:47 +0000 (22:06 -0700)]
i965: Make a helper function intel_miptree_set_total_width_height()
and some more code refactoring. No functional changes in this patch.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Anuj Phogat [Wed, 15 Apr 2015 05:06:48 +0000 (22:06 -0700)]
i965/gen9: Set vertical alignment for the miptree
v3: Use ffs() and a switch loop in
tr_mode_horizontal_texture_alignment() (Ben)
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Anuj Phogat [Wed, 15 Apr 2015 05:06:48 +0000 (22:06 -0700)]
i965/gen9: Set horizontal alignment for the miptree
v3: Use ffs() and a switch loop in
tr_mode_vertical_texture_alignment() (Ben)
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Anuj Phogat [Wed, 15 Apr 2015 05:06:47 +0000 (22:06 -0700)]
i965/gen9: Set tiled resource mode for the miptree
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Anuj Phogat [Wed, 15 Apr 2015 05:06:47 +0000 (22:06 -0700)]
i965: Pass miptree pointer as function parameter in intel_vertical_texture_alignment_unit
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Anuj Phogat [Wed, 15 Apr 2015 05:06:47 +0000 (22:06 -0700)]
i965: Move intel_miptree_choose_tiling() to brw_tex_layout.c
and change the name to brw_miptree_choose_tiling().
V3: Remove redundant function parameters. (Topi)
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Anuj Phogat [Wed, 15 Apr 2015 05:06:47 +0000 (22:06 -0700)]
i965: Choose tiling in brw_miptree_layout() function
This refactoring is required by later patches in this series.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Ben Widawsky [Tue, 23 Dec 2014 03:29:24 +0000 (19:29 -0800)]
i965: Disallow saturation for MACH operations.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Chris Wilson [Fri, 5 Jun 2015 13:45:18 +0000 (14:45 +0100)]
i965: Export format comparison for blitting between miptrees
Since the introduction of
commit
536003c11e4cb1172c540932ce3cce06f03bf44e
Author: Boyan Ding <boyan.j.ding@gmail.com>
Date: Wed Mar 25 19:36:54 2015 +0800
i965: Add XRGB8888 format to intel_screen_make_configs
winsys buffers no longer have an alpha channel. This causes
_mesa_format_matches_format_and_type() to reject previously working BGRA
uploads from using the BLT fast path. Instead of using the generic
routine for matching formats exactly, export the slightly more relaxed
check from intel_miptree_blit() which importantly allows the blitter
routine to apply a small number of format conversions.
References: https://bugs.freedesktop.org/show_bug.cgi?id=90839
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Alexander Monakov <amonakov@gmail.com>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
Chris Wilson [Fri, 5 Jun 2015 13:33:36 +0000 (14:33 +0100)]
i915: Blit RGBX<->RGBA drawpixels
The blitter already has code to accommodate filling in the alpha channel
for BGRX destination formats, so expand this to also allow filling the
alpha channgel in RGBX formats.
More importantly for the next patch is moving the test into its own
function for the purpose of exporting the check to the callers.
v2: Fix alpha expansion as spotted by Alexander with the fix suggested by
Kenneth
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Alexander Monakov <amonakov@gmail.com>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
Chris Wilson [Fri, 5 Jun 2015 12:49:08 +0000 (13:49 +0100)]
i965: Fix HW blitter pitch limits
The BLT pitch is specified in bytes for linear surfaces and in dwords
for tiled surfaces. In both cases the programmable limit is 32,767, so
adjust the check to compensate for the effect of tiling.
v2: Tweak whitespace for functions (Kenneth)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kristian Høgsberg <krh@bitplanet.net>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
Martin Peres [Fri, 5 Jun 2015 12:19:01 +0000 (15:19 +0300)]
softpipe/query: force parenthesis around a logical not
This makes GCC5 happy.
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Martin Peres <martin.peres@linux.intel.com>
Martin Peres [Fri, 5 Jun 2015 12:03:19 +0000 (15:03 +0300)]
main/version: make sure all the output variables get set in get_gl_override
This fixes 2 warnings in gcc 5.1.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Martin Peres <martin.peres@linux.intel.com>
Michel Dänzer [Tue, 26 May 2015 07:27:15 +0000 (16:27 +0900)]
radeonsi: Add CIK SDMA support
Based on the corresponding SI support. Same as that, this is currently
only enabled for one-dimensional buffer copies due to issues with
multi-dimensional SDMA copies.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Michel Dänzer [Wed, 19 Nov 2014 06:31:24 +0000 (15:31 +0900)]
r600g,radeonsi: Assert that there's enough space after flushing
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>