Simon Pilgrim [Mon, 24 Sep 2018 20:11:50 +0000 (20:11 +0000)]
[X86] Remove shift/rotate by CL memory (RMW) overrides
The uops are slightly different to the register variant, so requires a +1uop tweak
llvm-svn: 342916
Alexander Polyakov [Mon, 24 Sep 2018 19:10:48 +0000 (19:10 +0000)]
[lldb-mi] Fix hanging of target-select-so-path.test
Summary:
The target-select-so-path test might hang on
some platforms. The reason of that behavior
was in incorrect usage of Filecheck and lldb-mi
processes. Instead of redirecting lldb-mi's output
to Filecheck, we should run lldb-mi session,
finish the session, collect its output and then pass
it to Filecheck.
Also, this patch adds a timer to the test to prevent
it from hanging in the future.
Reviewers: tatyana-krasnukha, aprantl, teemperor
Reviewed By: tatyana-krasnukha, teemperor
Subscribers: apolyakov, aprantl, teemperor, ki.stfu, abidh, lldb-commits
Differential Revision: https://reviews.llvm.org/D52139
llvm-svn: 342915
Craig Topper [Mon, 24 Sep 2018 18:55:41 +0000 (18:55 +0000)]
[X86] Infer 64bit feature support from the CPUID results in getHostCPUFeatures.
After r341022, we more strictly check the 64bit feature in X86Subtargets constructor when a 64-bit triple is used. If we don't infer this feature for autodetected CPUs we might incorrectly report an error if the CPU name wasn't autodetected to a CPU that supports 64-bit.
llvm-svn: 342914
Calixte Denizet [Mon, 24 Sep 2018 18:24:29 +0000 (18:24 +0000)]
[profile] Revert commit https://reviews.llvm.org/rL342718
llvm-svn: 342913
Calixte Denizet [Mon, 24 Sep 2018 18:24:18 +0000 (18:24 +0000)]
[CodeGen] Revert commit https://reviews.llvm.org/rL342717
llvm-svn: 342912
Stefan Pintilie [Mon, 24 Sep 2018 18:14:50 +0000 (18:14 +0000)]
[Power9] [CLANG] Add __float128 exponent GET and SET builtins
Added
__builtin_vsx_scalar_extract_expq
__builtin_vsx_scalar_insert_exp_qp
Builtins should behave the same way as in GCC.
Differential Revision: https://reviews.llvm.org/D48184
llvm-svn: 342911
Stefan Pintilie [Mon, 24 Sep 2018 18:14:13 +0000 (18:14 +0000)]
[Power9] [LLVM] Add __float128 exponent GET and SET builtins
Added
__builtin_vsx_scalar_extract_expq
__builtin_vsx_scalar_insert_exp_qp
Builtins should behave the same way as in GCC.
Differential Revision: https://reviews.llvm.org/D48185
llvm-svn: 342910
Benjamin Kramer [Mon, 24 Sep 2018 17:51:15 +0000 (17:51 +0000)]
Fix the type of 1<<31 integer constants.
Shifting into the sign bit is technically undefined behavior. No known
compiler exploits it though.
llvm-svn: 342909
Simon Pilgrim [Mon, 24 Sep 2018 17:26:31 +0000 (17:26 +0000)]
[X86][AVX] Add truncation as shuffle test for PR31451
llvm-svn: 342908
Christy Lee [Mon, 24 Sep 2018 17:26:30 +0000 (17:26 +0000)]
Reland r342494 after fixing LIT checks.
llvm-svn: 342907
Sanjay Patel [Mon, 24 Sep 2018 17:18:32 +0000 (17:18 +0000)]
[Analysis] add comment to generalize finding a scalar op from vector; NFC
llvm-svn: 342906
Sanjay Patel [Mon, 24 Sep 2018 17:17:16 +0000 (17:17 +0000)]
[InstCombine] add/move tests for extractelement; NFC
llvm-svn: 342905
Simon Pilgrim [Mon, 24 Sep 2018 16:58:26 +0000 (16:58 +0000)]
[X86] Remove WriteDiv/WriteIDiv schedule overrides - use classes directly. NFCI.
We're missing quite a bit of data for these instruction, removing the overrides makes this obvious - inconsistent reg/mem variants is a concern as well.
Also, we have Divider resources (HWDivider etc.) but they aren't actually used consistently.
llvm-svn: 342904
Sam McCall [Mon, 24 Sep 2018 16:52:48 +0000 (16:52 +0000)]
[clangd] Fix uninit bool in r342888
llvm-svn: 342903
Sanjay Patel [Mon, 24 Sep 2018 16:39:03 +0000 (16:39 +0000)]
[InstCombine] improve variable name and use 'match'; NFC
'width' of a vector usually refers to the bit-width.
https://bugs.llvm.org/show_bug.cgi?id=39016
shows a case where we could extend this fold to handle
a case where the number of elements in the bitcasted
vector is not equal to the resulting value.
llvm-svn: 342902
Luke Cheeseman [Mon, 24 Sep 2018 16:36:33 +0000 (16:36 +0000)]
Reverting r342895
- The used builtins do not compile for pre arm v8.3a targets with gcc
llvm-svn: 342901
Evandro Menezes [Mon, 24 Sep 2018 16:35:14 +0000 (16:35 +0000)]
[ARM] Adjust the cost model for Exynos
Tune `MaxInterleaveFactor` and `LdStMultipleTiming`and remove
`PartialUpdateClearance` for the Exynos processors.
llvm-svn: 342900
Evandro Menezes [Mon, 24 Sep 2018 16:35:09 +0000 (16:35 +0000)]
[ARM] Adjust the feature set for Exynos
Enable crypto and literals fusion for the Exynos processors.
llvm-svn: 342899
Zhaoshi Zheng [Mon, 24 Sep 2018 16:15:23 +0000 (16:15 +0000)]
[Thumb1] Any imm8 should have cost of 1
A simple MOVS rd, imm8 can materialize [-128, 127] in signed i8 type or
[0, 255] in unsigned i8 type on Thumb1.
Differential Revision: https://reviews.llvm.org/D52257
llvm-svn: 342898
Michal Gorny [Mon, 24 Sep 2018 16:10:25 +0000 (16:10 +0000)]
[python] [tests] Update test_code_completion
Update expected completions to match output generated by clang-7.0.
Differential Revision: https://reviews.llvm.org/D50171
llvm-svn: 342897
Fedor Sergeev [Mon, 24 Sep 2018 16:08:15 +0000 (16:08 +0000)]
[New PM][PassInstrumentation] IR printing support for New Pass Manager
Implementing -print-before-all/-print-after-all/-filter-print-func support
through PassInstrumentation callbacks.
- PrintIR routines implement printing callbacks.
- StandardInstrumentations class provides a central place to manage all
the "standard" in-tree pass instrumentations. Currently it registers
PrintIR callbacks.
Reviewers: chandlerc, paquette, philip.pfaffe
Differential Revision: https://reviews.llvm.org/D50923
llvm-svn: 342896
Luke Cheeseman [Mon, 24 Sep 2018 15:55:35 +0000 (15:55 +0000)]
[AArch64] Unwinding support for return address signing
- When return address signing is enabled, the LR may be signed on function entry
- When an exception is thrown the return address is inspected used to unwind the call stack
- Before this happens, the return address must be correctly authenticated to avoid causing an abort by dereferencing the signed pointer
Differential Revision: https://reviews.llvm.org/D51432
llvm-svn: 342895
Will Wilson [Mon, 24 Sep 2018 15:28:03 +0000 (15:28 +0000)]
[lld-link] Generalize handling of /debug and /debug:{none,full,fastlink,ghash,symtab}
Implement final argument precedence if multiple /debug arguments are passed on the command-line to match expected link.exe behavior.
Support /debug:none and emit warning for /debug:fastlink with automatic fallback to /debug:full.
Emit error if last /debug:option is unknown.
Emit warning if last /debugtype:option is unknown.
https://reviews.llvm.org/D50404
llvm-svn: 342894
Kristina Brooks [Mon, 24 Sep 2018 15:26:08 +0000 (15:26 +0000)]
Revert "rL342883: [Clang][CodeGen][ObjC]: Fix CoreFoundation on ELF with `-fconstant-cfstrings`."
Seems to be causing buildbot failures, need to look into it.
llvm-svn: 342893
Simon Pilgrim [Mon, 24 Sep 2018 15:21:57 +0000 (15:21 +0000)]
[X86] Split WriteIMul into 8/16/32/64 implementations (PR36931)
Split WriteIMul by size and also by IMUL multiply-by-imm and multiply-by-reg cases.
This removes all the scheduler overrides for gpr multiplies and stops WriteMULH being ignored for BMI2 MULX instructions.
llvm-svn: 342892
Luke Cheeseman [Mon, 24 Sep 2018 15:13:48 +0000 (15:13 +0000)]
[Arm][AsmParser] Restrict register list size for VSTM/VLDM
- The assembler accepts VSTM/VLDM with register lists (specifically double registers lists) with more than 16 registers specified
- The Arm architecture reference manual says this instruction must not contain more than 16 registers when the registers are doubleword registers
- This addresses one of the concerns in https://bugs.llvm.org/show_bug.cgi?id=38389
Differential Revision: https://reviews.llvm.org/D52082
llvm-svn: 342891
Kristina Brooks [Mon, 24 Sep 2018 14:52:48 +0000 (14:52 +0000)]
[CFString][ELF] Fix a missed test causing buildbot failures from 342883.
Accidetanlly forgot to update it, big sorry.
llvm-svn: 342890
Eric Liu [Mon, 24 Sep 2018 14:52:11 +0000 (14:52 +0000)]
[VFS] Use llvm::StringMap instead of std::map. NFC
llvm-svn: 342889
Sam McCall [Mon, 24 Sep 2018 14:51:15 +0000 (14:51 +0000)]
[clangd] Do bounds checks while reading data, otherwise var-length records are too painful. NFC
llvm-svn: 342888
Ed Maste [Mon, 24 Sep 2018 14:47:56 +0000 (14:47 +0000)]
Correct RISC-V link in release notes
llvm-svn: 342887
Sanjay Patel [Mon, 24 Sep 2018 14:47:15 +0000 (14:47 +0000)]
[DAGCombiner] use UADDO to optimize saturated unsigned add
This is a preliminary step towards solving PR14613:
https://bugs.llvm.org/show_bug.cgi?id=14613
If we have an 'add' instruction that sets flags, we can use that to eliminate an
explicit compare instruction or some other instruction (cmn) that sets flags for
use in the later select.
As shown in the unchanged tests that use 'icmp ugt %x, %a', we're effectively
reversing an IR icmp canonicalization that replaces a variable operand with a
constant:
https://rise4fun.com/Alive/V1Q
But we're not using 'uaddo' in those cases via DAG transforms. This happens in
CGP after D8889 without checking target lowering to see if the op is supported.
So AArch already shows 'uaddo' codegen for the i8/i16/i32/i64 test variants with
"using_cmp_sum" in the title. That's the pattern that CGP matches as an unsigned
saturated add and converts to uaddo without checking target capabilities.
This patch is gated by isOperationLegalOrCustom(ISD::UADDO, VT), so we see only
see AArch diffs for i32/i64 in the tests with "using_cmp_notval" in the title
(unlike x86 which sees improvements for all sizes because all sizes are 'custom').
But the AArch code (like x86) looks better when translated to 'uaddo' in all cases.
So someone that is involved with AArch may want to set i8/i16 to 'custom' for UADDO,
so this patch will fire on those tests.
Another possibility given the existing behavior: we could remove the legal-or-custom
check altogether because we're assuming that a UADDO sequence is canonical/optimal
before we ever reach here. But that seems like a bug to me. If the target doesn't
have an add-with-flags op, then it's not likely that we'll get optimal DAG combining
using a UADDO node. This is similar justification for why we don't canonicalize IR to
the overflow math intrinsic sibling (llvm.uadd.with.overflow) for UADDO in the first
place.
Differential Revision: https://reviews.llvm.org/D51929
llvm-svn: 342886
Anastasia Stulova [Mon, 24 Sep 2018 14:21:56 +0000 (14:21 +0000)]
Revert "We allow implicit function declarations as an extension in all C dialects. Remove OpenCL special case."
Discussed on cfe-commits (Week-of-Mon-
20180820), this change leads to
the generation of invalid IR for OpenCL without giving an error.
Therefore, the conclusion was to revert.
llvm-svn: 342885
Petar Jovanovic [Mon, 24 Sep 2018 14:14:19 +0000 (14:14 +0000)]
[Mips][FastISel] Fix selectBranch on icmp i1
The r337288 tried to fix result of icmp i1 when its input is not sanitized
by falling back to DagISel. While it now produces the correct result for
bit 0, the other bits can still hold arbitrary value which is not supported
by MipsFastISel branch lowering. This patch fixes the issue by falling back
to DagISel in this case.
Patch by Dragan Mladjenovic.
Differential Revision: https://reviews.llvm.org/D52045
llvm-svn: 342884
Kristina Brooks [Mon, 24 Sep 2018 14:06:47 +0000 (14:06 +0000)]
[Clang][CodeGen][ObjC]: Fix CoreFoundation on ELF with `-fconstant-cfstrings`.
[Clang][CodeGen][ObjC]: Fix non-bridged CoreFoundation builds on ELF targets
that use `-fconstant-cfstrings`. The original changes from differential
for a similar patch to PE/COFF (https://reviews.llvm.org/D44491) did not
check for an edge case where the global could be a constant which surfaced
as an issue when building for ELF because of different linkage semantics.
This patch addresses several issues with crashes related to CF builds on ELF
as well as improves data layout by ensuring string literals that back
the actual CFConstStrings end up in .rodata in line with Mach-O.
Change itself tested with CoreFoundation on Linux x86_64 but should be valid
for BSD-like systems as well that use ELF as the native object format.
Differential Revision: https://reviews.llvm.org/D52344
llvm-svn: 342883
Zaara Syeda [Mon, 24 Sep 2018 14:01:16 +0000 (14:01 +0000)]
[PowerPC] Support operand modifier 'x' in inline asm
gcc uses operand modifier 'x' in inline asm for VSX registers.
Without this modifier, instructions which use VSX numbering for their
operands are printed as VMX registers. This patch adds support for the
operand modifier 'x'.
Differential Revision: https://reviews.llvm.org/D52244
llvm-svn: 342882
Jonas Devlieghere [Mon, 24 Sep 2018 13:56:36 +0000 (13:56 +0000)]
[dsymutil] Set LSan blacklist whenever sanitizers are enabled.
LSan can be enabled by itself or as part of the address sanitizer.
Rather than checking the enabled sanitizers for both, just set the LSan
env options whenever a sanitizer is enabled.
llvm-svn: 342881
Roman Lebedev [Mon, 24 Sep 2018 13:24:20 +0000 (13:24 +0000)]
[NFC][CodeGen][X86][AArch64] More tests for 'bit field extract' w/ constants
It would be best to introduce ISD::BitFieldExtract,
because clearly more than one backend faces the same problem.
But for now let's solve this in the x86-specific DAG combine.
https://bugs.llvm.org/show_bug.cgi?id=38938
llvm-svn: 342880
Matt Arsenault [Mon, 24 Sep 2018 13:18:15 +0000 (13:18 +0000)]
AMDGPU: Fix private handling for allowsMisalignedMemoryAccesses
If the alignment is at least 4, this should report true.
Something still seems off with how < 4-byte types are
handled here though.
Fixing this seems to change how some combines get
to where they get, but somehow isn't changing the net
result.
llvm-svn: 342879
Matt Arsenault [Mon, 24 Sep 2018 12:47:17 +0000 (12:47 +0000)]
Fix some missing opcodes in bcanalyzer
llvm-svn: 342878
Andrea Di Biagio [Mon, 24 Sep 2018 12:45:26 +0000 (12:45 +0000)]
[llvm-mca] Improve code comments in LSUnit.{h, cpp}. NFC
llvm-svn: 342877
Sven van Haastregt [Mon, 24 Sep 2018 12:12:03 +0000 (12:12 +0000)]
Fix Wundef NDEBUG warning; NFC
Check for definedness of the NDEBUG macro rather than its value,
to be consistent with other uses.
llvm-svn: 342876
Pavel Labath [Mon, 24 Sep 2018 12:11:04 +0000 (12:11 +0000)]
Add NativeProcessProtocol unit tests
Summary:
NativeProcessProtocol is an abstract class, but it still contains a
significant amount of code. Some of that code is tested via tests of
specific derived classes, but these tests don't run everywhere, as they
are OS and arch-specific. They are also relatively high-level, which
means some functionalities (particularly the failure cases) are
hard/impossible to test.
In this approach, I replace the abstract methods with mocks, which
allows me to inject failures into the lowest levels of breakpoint
setting code and test the class behavior in this situation.
Reviewers: zturner, teemperor
Subscribers: mgorny, lldb-commits
Differential Revision: https://reviews.llvm.org/D52152
llvm-svn: 342875
Sjoerd Meijer [Mon, 24 Sep 2018 12:02:50 +0000 (12:02 +0000)]
[ARM] Do not fuse VADD and VMUL on the Cortex-M4 and Cortex-M33
A sequence of VMUL and VADD instructions always give the same or better
performance than a fused VMLA instruction on the Cortex-M4 and Cortex-M33.
Executing the VMUL and VADD back-to-back requires the same cycles, but
having separate instructions allows scheduling to avoid the hazard between
these 2 instructions.
Differential Revision: https://reviews.llvm.org/D52289
llvm-svn: 342874
Hans Wennborg [Mon, 24 Sep 2018 11:40:07 +0000 (11:40 +0000)]
Revert r341932 "[ARM] Enable ARMCodeGenPrepare by default"
This caused miscompilation of WebRTC for Android: PR39060.
> We've had the pass enabled downstream for a couple of weeks and it
> seems to be okay, so enable it by default.
>
> Differential Revision: https://reviews.llvm.org/D51920
llvm-svn: 342873
Luke Cheeseman [Mon, 24 Sep 2018 10:42:22 +0000 (10:42 +0000)]
[ARM][ARMLoadStoreOptimizer]
- The load store optimizer is currently merging multiple loads/stores into VLDM/VSTM with more than 16 doubleword registers
- This is an UNPREDICTABLE instruction and shouldn't be done
- It looks like the Limit for how many registers included in a merge got dropped at some point so I am reintroducing it in this patch
- This fixes https://bugs.llvm.org/show_bug.cgi?id=38389
Differential Revision: https://reviews.llvm.org/D52085
llvm-svn: 342872
Petar Jovanovic [Mon, 24 Sep 2018 10:01:24 +0000 (10:01 +0000)]
[deadargelim] Update dbg.value of 'unused' parameters
DeadArgElim pass marks unused function arguments as ‘undef’ without updating
existing dbg.values referring to it. As a consequence the debug info
metadata in the final executable was wrong.
Patch by Djordje Todorovic.
Differential Revision: https://reviews.llvm.org/D51968
llvm-svn: 342871
Sam Parker [Mon, 24 Sep 2018 09:34:06 +0000 (09:34 +0000)]
[ARM] bottom-top mul support ARMParallelDSP
Originally committed in rL342210 but was reverted in rL342260 because
it was causing issues in vectorized code, because I had forgotten to
ensure that we're operating on scalar values.
Original commit message:
On failing to find sequences that can be converted into dual macs,
try to find sequential 16-bit loads that are used by muls which we
can then use smultb, smulbt, smultt with a wide load.
Differential Revision: https://reviews.llvm.org/D51983
llvm-svn: 342870
Dan Liew [Mon, 24 Sep 2018 09:30:33 +0000 (09:30 +0000)]
When running the ios/iossim prepare script show the script output when it returns with a non-zero exit code.
Summary:
Previously we'd just show the exception and not the output from the
executed script. This is unhelpful in the case that the script actually
reports some useful information on the failure.
Now we print the output and re-raise the exception.
Reviewers: kubamracek, george.karpenkov
Subscribers: #sanitizers, llvm-commits
Differential Revision: https://reviews.llvm.org/D52350
llvm-svn: 342869
Dan Liew [Mon, 24 Sep 2018 09:28:35 +0000 (09:28 +0000)]
Fix the configuration of the Primary allocator for Darwin ARM64 by
changing the value of `SANITIZER_MMAP_RANGE_SIZE` to something more
sensible. The available VMA is at most 64GiB and not 256TiB that
was previously being used.
This change gives us several wins:
* Drastically improves LeakSanitizer performance on
Darwin ARM64 devices. On a simple synthentic benchmark
this took leak detection time from ~30 seconds to 0.5 seconds
due to the `ForEachChunk(...)` method enumerating a much smaller
number of regions. Previously we would pointlessly iterate
over a large portion of the SizeClassAllocator32's ByteMap
that would could never be set due it being configured for a much
larger VM space than is actually availble.
* Decreases the memory required for the Primary allocator.
Previously the ByteMap inside the the allocator used
an array of pointers that took 512KiB of space. Now the required
space for the array is 128 bytes.
rdar://problem/
43509428
Differential Revision: https://reviews.llvm.org/D51173
llvm-svn: 342868
Kirill Bobyrev [Mon, 24 Sep 2018 08:45:18 +0000 (08:45 +0000)]
[clangd] Force Dex to respect symbol collector flags
`Dex` should utilize `FuzzyFindRequest.RestrictForCodeCompletion` flags
and omit symbols not meant for code completion when asked for it.
The measurements below were conducted with setting
`FuzzyFindRequest.RestrictForCodeCompletion` to `true` (so that it's
more realistic). Sadly, the average latency goes down, I suspect that is
mostly because of the empty queries where the number of posting lists is
critical.
| Metrics | Before | After | Relative difference
| ----- | ----- | ----- | -----
| Cumulative query latency (7000 `FuzzyFindRequest`s over LLVM static index) |
6182735043 ns |
7202442053 ns | +16%
| Whole Index size | 81.24 MB | 81.79 MB | +0.6%
Out of 292252 symbols collected from LLVM codebase 136926 appear to be
restricted for code completion.
Reviewers: ioeric
Differential Revision: https://reviews.llvm.org/D52357
llvm-svn: 342866
Clement Courbet [Mon, 24 Sep 2018 08:39:48 +0000 (08:39 +0000)]
[llvm-exegesis] Fix PR39021.
Summary:
The `set` statements was incorrectly reading the value of the local variable and
setting the value of the parent variable.
Reviewers: tycho, gchatelet, john.brawn
Subscribers: mgorny, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D52343
llvm-svn: 342865
Hans Wennborg [Mon, 24 Sep 2018 08:34:17 +0000 (08:34 +0000)]
Fix llvm-diff anon-func.ll test
llvm-svn: 342864
Hans Wennborg [Mon, 24 Sep 2018 08:18:47 +0000 (08:18 +0000)]
Remove debug printf leftover from r342397
llvm-svn: 342863
Sjoerd Meijer [Mon, 24 Sep 2018 07:55:20 +0000 (07:55 +0000)]
[ARM][AArch64] Add feature +fp16fml
Armv8.4-A adds a few FP16 instructions that can optionally be implemented
in CPUs of Armv8.2-A and above.
This patch adds a feature to clang to permit selection of these
instructions. This interacts with the +fp16 option as follows:
Prior to Armv8.4-A:
*) +fp16fml implies +fp16
*) +nofp16 implies +nofp16fml
From Armv8.4-A:
*) The above conditions apply, additionally: +fp16 implies +fp16fml
Patch by Bernard Ogden.
Differential Revision: https://reviews.llvm.org/D50229
llvm-svn: 342862
Michael Kruse [Mon, 24 Sep 2018 06:31:37 +0000 (06:31 +0000)]
Add inherited attributes before parsed attributes.
Currently, attributes from previous declarations ('inherited attributes')
are added to the end of a declaration's list of attributes. Before
r338800, the attribute list was in reverse. r338800 changed the order
of non-inherited (parsed from the current declaration) attributes, but
inherited attributes are still appended to the end of the list.
This patch appends inherited attributes after other inherited
attributes, but before any non-inherited attribute. This is to make the
order of attributes in the AST correspond to the order in the source
code.
Differential Revision: https://reviews.llvm.org/D50214
llvm-svn: 342861
Craig Topper [Mon, 24 Sep 2018 05:46:01 +0000 (05:46 +0000)]
[X86] Add 512-bit test cases to setcc-wide-types.ll. NFC
llvm-svn: 342860
Dean Michael Berris [Mon, 24 Sep 2018 05:28:01 +0000 (05:28 +0000)]
[XRay] Clean up XRay build configuration
Summary:
This change spans both LLVM and compiler-rt, where we do the following:
- Add XRay to the LLVMBuild system, to allow for distributing the XRay
trace loading library along with the LLVM distributions.
- Use `llvm-config` better in the compiler-rt XRay implementation, to
depend on the potentially already-distributed LLVM XRay library.
While this is tested with the standalone compiler-rt build, it does
require that the LLVMXRay library (and LLVMSupport as well) are
available during the build. In case the static libraries are available,
the unit tests will build and work fine. We're still having issues with
attempting to use a shared library version of the LLVMXRay library since
the shared library might not be accessible from the standard shared
library lookup paths.
The larger change here is the inclusion of the LLVMXRay library in the
distribution, which allows for building tools around the XRay traces and
profiles that the XRay runtime already generates.
Reviewers: echristo, beanz
Subscribers: mgorny, hiraditya, mboerger, llvm-commits
Differential Revision: https://reviews.llvm.org/D52349
llvm-svn: 342859
Matt Arsenault [Mon, 24 Sep 2018 04:42:14 +0000 (04:42 +0000)]
Fix asserts when linking wrong address space declarations
llvm-svn: 342858
Matt Arsenault [Mon, 24 Sep 2018 04:42:13 +0000 (04:42 +0000)]
llvm-diff: Fix crash on anonymous functions
Not sure what the correct behavior is for this.
Skip them and report how many there were.
llvm-svn: 342857
Craig Topper [Mon, 24 Sep 2018 02:03:11 +0000 (02:03 +0000)]
[DAGCombiner] Remove some dead code from ConstantFoldBITCASTofBUILD_VECTOR
This code handled SCALAR_TO_VECTOR being returned by the recursion, but the code that used to return SCALAR_TO_VECTOR was removed in 2015.
llvm-svn: 342856
Louis Dionne [Sun, 23 Sep 2018 23:17:48 +0000 (23:17 +0000)]
[libcxx] Fix the binder deprecation tests on Clang 5.
Tested on Docker containers with Clang 4, 5 and 6.
llvm-svn: 342855
Louis Dionne [Sun, 23 Sep 2018 22:16:35 +0000 (22:16 +0000)]
[libcxx] Fix buildbots on Debian
Debian build bots are running Clang 4, which apparently does not support
the "deprecated" attribute properly. Clang pretends to support the attribute,
but the attribute doesn't do anything.
(live example: https://wandbox.org/permlink/0De69aXns0t1D59r)
On a separate note, I'm not sure I understand why we're even running the
libc++ tests under Clang-4. Is this a configuration we support? I can
understand that libc++ should _build_ with Clang 4, but it's not clear
to me that new libc++ headers should be usable under older compilers
like that.
llvm-svn: 342854
Lang Hames [Sun, 23 Sep 2018 21:30:05 +0000 (21:30 +0000)]
[ORC] Add some debugging output to Core.h/Core.cpp
Core now logs when materialization units are dispatched or return to JITDylibs.
llvm-svn: 342853
Simon Pilgrim [Sun, 23 Sep 2018 21:19:15 +0000 (21:19 +0000)]
[X86] Split WriteShift/WriteRotate schedule classes by CL usage.
Variable Shifts/Rotates using the CL register have different behaviours to the immediate instructions - split accordingly to help remove yet more repeated overrides from the schedule models.
llvm-svn: 342852
Craig Topper [Sun, 23 Sep 2018 21:17:56 +0000 (21:17 +0000)]
[DAGCombiner] Clarify a comment. NFC
This comment was misleading about why we were restricting to before legalize types. The reason given would only apply to before legalize ops. But there is a before legalize types reason that should also be listed.
llvm-svn: 342851
Craig Topper [Sun, 23 Sep 2018 21:17:55 +0000 (21:17 +0000)]
[LegalizeTypes] Fix bad indentation. NFC
llvm-svn: 342850
Louis Dionne [Sun, 23 Sep 2018 21:10:06 +0000 (21:10 +0000)]
[libcxx] Document new symbols __u64toa and __u32toa on Darwin
Summary:
This is the counterpart for https://reviews.llvm.org/D50130 and
https://reviews.llvm.org/D52391 on Darwin.
Reviewers: EricWF
Subscribers: christof, dexonsmith, cfe-commits, libcxx-commits, lichray
Differential Revision: https://reviews.llvm.org/D52396
llvm-svn: 342849
Simon Pilgrim [Sun, 23 Sep 2018 19:33:58 +0000 (19:33 +0000)]
[X86] Remove unnecessary WriteRotate override. NFCI.
SNB was the last override for ROT(L|R)r(1|i) - they now all use WriteRotate correctly.
llvm-svn: 342848
Simon Pilgrim [Sun, 23 Sep 2018 19:16:32 +0000 (19:16 +0000)]
Fix line ending mismatches. NFCI.
llvm-svn: 342847
Simon Pilgrim [Sun, 23 Sep 2018 19:16:01 +0000 (19:16 +0000)]
[X86] ROR*mCL instruction models should match ROL*mCL etc.
Confirmed with Craig Topper - fix a typo that was missing a Port4 uop for ROR*mCL instructions on some Intel models.
Yet another step on the scheduler model cleanup marathon......
llvm-svn: 342846
Benjamin Kramer [Sun, 23 Sep 2018 18:43:28 +0000 (18:43 +0000)]
[Aarch64] Fix memcpy that was copying 4x too many bytes
Found by asan.
llvm-svn: 342845
Sanjay Patel [Sun, 23 Sep 2018 18:41:38 +0000 (18:41 +0000)]
[DAGCombiner][x86] extend decompose of integer multiply into shift/add with negation
This is an alternative to https://reviews.llvm.org/D37896. We can't decompose
multiplies generically without a target hook to tell us when it's profitable.
ARM and AArch64 may be able to remove some existing code that overlaps with
this transform.
This extends D52195 and may resolve PR34474:
https://bugs.llvm.org/show_bug.cgi?id=34474
(still an open question about transforming legal vector multiplies, but we
could open another bug report for those)
llvm-svn: 342844
Louis Dionne [Sun, 23 Sep 2018 18:35:00 +0000 (18:35 +0000)]
[libc++] Add deprecated attributes to many deprecated components
Summary:
These deprecation warnings are opt-in: they are only enabled when the
_LIBCXX_DEPRECATION_WARNINGS macro is defined, which is not the case
by default. Note that this is a first step in the right direction, but
I wasn't able to get an exhaustive list of all deprecated components
per standard, so there's certainly stuff that's missing. The list of
components this commit marks as deprecated is:
in C++11:
- auto_ptr, auto_ptr_ref
- binder1st, binder2nd, bind1st(), bind2nd()
- pointer_to_unary_function, pointer_to_binary_function, ptr_fun()
- mem_fun_t, mem_fun1_t, const_mem_fun_t, const_mem_fun1_t, mem_fun()
- mem_fun_ref_t, mem_fun1_ref_t, const_mem_fun_ref_t, const_mem_fun1_ref_t, mem_fun_ref()
in C++14:
- random_shuffle()
in C++17:
- unary_negate, binary_negate, not1(), not2()
<rdar://problem/
18168350>
Reviewers: mclow.lists, EricWF
Subscribers: christof, dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D48912
llvm-svn: 342843
Simon Pilgrim [Sun, 23 Sep 2018 17:40:24 +0000 (17:40 +0000)]
[X86] Added missing RCL/RCR schedule overrides to the generic SNB model
The SandyBridge model was missing schedule values for the RCL/RCR values - instead using the (incredibly optimistic) WriteShift (now WriteRotate) defaults.
I've added overrides with more realistic (slow) values, based on a mixture of Agner/instlatx64 numbers and what later Intel models do as well.
This is necessary to allow WriteRotate to be updated to remove other rotate overrides.
It'd probably be a good idea to investigate a WriteRotateCarry class at some point but its not high priority given the unusualness of these instructions.
llvm-svn: 342842
Simon Pilgrim [Sun, 23 Sep 2018 16:53:02 +0000 (16:53 +0000)]
[X86] Remove unnecessary WriteRotate overrides. NFCI.
llvm-svn: 342841
Louis Dionne [Sun, 23 Sep 2018 16:44:50 +0000 (16:44 +0000)]
[NFC][libcxx] Rename helpers with 4 underscores to something more reasonable
llvm-svn: 342840
Simon Pilgrim [Sun, 23 Sep 2018 16:17:13 +0000 (16:17 +0000)]
[X86] Move RORX instructions back to WriteShift schedule class
Despite being rotates, these more modern instructions avoid many of the quirks of the regular x86 rotate instructions and consistently have a schedule closer to shifts.
llvm-svn: 342839
Sanjay Patel [Sun, 23 Sep 2018 16:07:46 +0000 (16:07 +0000)]
[x86] add tests for mul decomposition with negative constant; NFC
llvm-svn: 342838
Simon Pilgrim [Sun, 23 Sep 2018 15:12:10 +0000 (15:12 +0000)]
[X86] Add WriteRotate schedule class, splitting off from WriteShift.
NFCI for now, but it should make it easier to remove a lot of unnecessary overrides in a future commit.
Now that funnel shift intrinsics are coming online we need to get this cleaned up to make vectorization costs from scalar rotate patterns more straightforward.
llvm-svn: 342837
Eugene Leviant [Sun, 23 Sep 2018 13:27:47 +0000 (13:27 +0000)]
[WholeProgramDevirt] Don't process declarations when building type id map
Differential revision: https://reviews.llvm.org/D52175
llvm-svn: 342836
Simon Pilgrim [Sun, 23 Sep 2018 11:28:47 +0000 (11:28 +0000)]
Build PassBuilder.cpp with /bigobj to try and appease MSVC EXPENSIVE_CHECKS buildbot
llvm-svn: 342835
Kristof Umann [Sun, 23 Sep 2018 09:16:27 +0000 (09:16 +0000)]
[analyzer][UninitializedObjectChecker] Using the new const methods of ImmutableList
Differential Revision: https://reviews.llvm.org/D51886
llvm-svn: 342834
Petr Hosek [Sun, 23 Sep 2018 08:46:31 +0000 (08:46 +0000)]
[CMake] Use internal_linkage rather than always_inline for libc++
This is a workaround for PR39053 which was uncovered by D50652 when
the default attribute has been changed from internal_linkage to
always_inline.
Differential Revision: https://reviews.llvm.org/D52402
llvm-svn: 342833
David Carlier [Sun, 23 Sep 2018 08:30:17 +0000 (08:30 +0000)]
[CStringSyntaxChecker] Check strlcat sizeof check
Assuming strlcat is used with strlcpy we check as we can if the last argument does not equal os not larger than the buffer.
Advising the proper usual pattern.
Reviewers: george.karpenkov, NoQ, MaskRay
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D49722
llvm-svn: 342832
Fangrui Song [Sun, 23 Sep 2018 08:23:48 +0000 (08:23 +0000)]
[Index] Report specialization bases as references when IndexImplicitInstantiation is true
Summary:
template <typename T> struct B {};
template <typename T> struct D : B<T> {}; // `B` was not reported as a reference
This patch fixes this.
Reviewers: akyrtzi, arphaman, devnexen
Reviewed By: devnexen
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D52331
llvm-svn: 342831
Craig Topper [Sun, 23 Sep 2018 06:49:48 +0000 (06:49 +0000)]
[X86] Add isel pattern for (v8i16 (sext (v8i1))) with DQI and no BWI.
Our lowering that tries to avoid this sign extend can be defeated by the DAG combine folding it with a truncate.
The pattern needs to extend to an v8i32 then truncate back down to v8i16.
llvm-svn: 342830
Craig Topper [Sun, 23 Sep 2018 06:49:47 +0000 (06:49 +0000)]
[X86] Fix a few typos in comments.
llvm-svn: 342829
Lang Hames [Sun, 23 Sep 2018 02:09:18 +0000 (02:09 +0000)]
[ORC] Update ORC C bindings to use the new llvm::Error C API.
This replaces instances of the LLVMOrcErrorCode type with LLVMErrorRef,
simplifying the implementation of the OrcCBindingsStack class and ORC
C API bindings and making it possible to return arbitrary (wrapped)
llvm::Errors.
llvm-svn: 342828
Eric Fiselier [Sun, 23 Sep 2018 00:48:05 +0000 (00:48 +0000)]
Fix modules build with shared library.
r341994 caused clangAnalysis to pull all of the AST matchers
library into clang. Due to inline key functions in the headers,
importing the AST matchers library gives a link dependency on the
AST matchers (and thus the AST), which clang should not
have.
This patch works around the issues by excluding the offending
libclangAnalysis header in the modulemap.
llvm-svn: 342827
Craig Topper [Sat, 22 Sep 2018 23:12:34 +0000 (23:12 +0000)]
[DAGCombiner] Simplify some code in visitBITCAST. NFCI
llvm-svn: 342826
Fangrui Song [Sat, 22 Sep 2018 22:49:38 +0000 (22:49 +0000)]
[Index] Fix header guard naming
llvm-svn: 342825
Tri Vo [Sat, 22 Sep 2018 22:17:50 +0000 (22:17 +0000)]
[AArch64] Support adding X[8-15,18] registers as CSRs.
Summary:
Specifying X[8-15,18] registers as callee-saved is used to support
CONFIG_ARM64_LSE_ATOMICS in Linux kernel. As part of this patch we:
- use custom CSR list/mask when user specifies custom CSRs
- update Machine Register Info's list of CSRs with additional custom CSRs in
LowerCall and LowerFormalArguments.
Reviewers: srhines, nickdesaulniers, efriedma, javed.absar
Reviewed By: nickdesaulniers
Subscribers: kristof.beyls, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D52216
llvm-svn: 342824
Aaron Puchert [Sat, 22 Sep 2018 21:56:16 +0000 (21:56 +0000)]
Eliminate some unneeded signed/unsigned conversions
No functional change is intended, but generally this should be a bit
more safe.
llvm-svn: 342823
Louis Dionne [Sat, 22 Sep 2018 21:30:12 +0000 (21:30 +0000)]
[NFC][libc++] Fix typo in the description of LIBCXX_INCLUDE_BENCHMARKS
llvm-svn: 342822
Eric Fiselier [Sat, 22 Sep 2018 21:01:07 +0000 (21:01 +0000)]
Mark [[nodiscard]] tests unsupported on GCC prior to 7.0
llvm-svn: 342821
Eric Fiselier [Sat, 22 Sep 2018 20:09:02 +0000 (20:09 +0000)]
Fix UB in SIMD tests.
One of the SIMD tests attempted to left shift a value by 42, which
is UB when the left hand side is a 32 bit integer type.
This patch adjusts the test to use the value 4 instead of 42.
llvm-svn: 342820
Roman Lebedev [Sat, 22 Sep 2018 20:07:02 +0000 (20:07 +0000)]
[libcxx] Readjust nodiscard_extensions.pass.cpp test - just disable for ASAN
In rL342814, i have committed a blind fix to unbreak the asan buildbot,
but as it was later discussed, the leak is intentional,
so we can not fix the failure that way.
So this reverts the leak 'fix',
and simply disables the test in the presence of ASAN.
llvm-svn: 342819
Eric Fiselier [Sat, 22 Sep 2018 20:03:47 +0000 (20:03 +0000)]
Mark test as flaky
llvm-svn: 342818
Eric Fiselier [Sat, 22 Sep 2018 19:52:12 +0000 (19:52 +0000)]
Update docs to reference new libc++ mailing lists.
llvm-svn: 342817
Eric Fiselier [Sat, 22 Sep 2018 19:49:29 +0000 (19:49 +0000)]
Correct docs to reference the new libc++ lists.
We recently added libcxx-dev and libcxx-commits mailing lists.
This patch updates the libc++ documentation to correctly reference
the libc++ lists instead of the old Clang ones.
llvm-svn: 342816