Marek Olšák [Sat, 22 Oct 2022 00:29:31 +0000 (20:29 -0400)]
nir: add nir_intrinsic_optimization_barrier_vgpr_amd for LLVM
We need this for the MSAA resolve shader.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19243>
Alyssa Rosenzweig [Thu, 27 Oct 2022 21:48:02 +0000 (17:48 -0400)]
panfrost: Add lots of perf_debug annotations
Should make it easier to diagnose performance issues in the future.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19358>
Alyssa Rosenzweig [Thu, 27 Oct 2022 20:29:37 +0000 (16:29 -0400)]
panfrost: Enable rendering to 16-bit and 32-bit
Bifrost onwards handle this in hardware, and the Midgard lowering isn't
too terrible. Enable the format, otherwise desktop GL apps such as
Hacknet try to render to the format and get an incomplete framebuffer.
Cc stable because apparently we've been advertising this format
unintentionally as a result of some other interaction? Unclear how
Hacknet is hitting this, maybe it's an app bug. Shrug, it's not a big
deal regardless.
Additionally, we need to restrict texturing from 32-bit normalized due
to a restriction added with the v7 pixel format fiasco. That means
restricting rendering to 32-bit normalized on v7 onwards.
Closes: #7251
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Tested-by: Dang Huynh <danct12@disroot.org>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19358>
Alyssa Rosenzweig [Sat, 29 Oct 2022 17:36:02 +0000 (13:36 -0400)]
panfrost/ci: Disable trace-based testing
Trace-based testing has not worked for Panfrost. It was a neat
experiment, and I'm glad we tried it, but the results have been mostly
negative for the driver. Disable the trace-based tests.
For testing that specific API features work correctly, we run the
conformance tests (dEQP), which are thorough for OpenGL ES. For big GL
features, we run Piglit, and if there are big GL features that we are
not testing adequately, we should extend Piglit for these. For
fine-grained driver correctness, we are already covered.
Where trace-based testing can fit in is as a smoke test, ensuring that
the overall rendering of complex scenes does not regress. In principle,
that's a lovely idea, but the current implementation has not worked out
for Panfrost thus far. The crux of the issue is that the trace based
tests are based on checksums, not fuzzy-compared reference images. That
requires updating checksums any time rendering changes. However, a
rendering change to a trace is NOT a regression. The behaviour of OpenGL
is specified very loosely. For a given trace, there are many different
valid checksums. That means that correct changes to core code frequently
fail CI after running through the rest of CI, only because a checksum
changed in a still correct way. That's a pain to deal with, exacerbated
by rebase pains, and provides negative value to the project. Some recent
examples of this I've hit in the past two weeks alone:
panfrost: Enable rendering to 16-bit and 32-bit
4b49241f7d7 ("panfrost: Use proper formats for pntc varying")
ac2964dfbd1 ("nir: Be smarter fusing ffma")
The last example were virgl traces, but were especially bad: due to a
rebase fail, I had to update traces /twice/, wasting two full runs of
pre-merge CI across *all* hardware. This was extremely wasteful.
The value of trace-based testing is as a smoke test to check that traces
still render correctly. That is useful, but it turns out that checksums
are the wrong way to go about it. A better implementation would be
storing only a single reference image from a software rasterizer per
trace. No driver-specific references would be stored. That reference
image must never change, provided the trace never changes. CI would then
check rendered results against that image with tolerant fuzzy
comparisons. That tolerance matches with the fuzzy comparison that the
human eye would do when investigating a checksum change anyway. Yes, the
image comparison JavaScript will now report that
0 pixels changed within the tolerance, but there's nothing a human eye
can do with that information other than an error prone copypaste of new
checksums back in the yaml file and kicking it back to CI, itself a
waste of time.
Finally, in the time we've had trace-based testing alongside the
conformance tests, I cannot remember a single actual regression in one
of my commits the trace jobs have identified that the conformance tests
have not also identified. By contrast, the conformance test coverage has
prevented the merge of a number of actual regressions, with very few
flakes or xfail changes, and I am grateful we have that coverage. That
means the value added from the trace jobs is close to zero, while the
above checksum issues means that the cost is tremendous, even ignoring
the physical cost of the extra CI jobs.
If you work on trace-based testing and would like to understand how it
could adapted to be useful for Panfrost, see my recommendations above.
If you work on CI in general and would like to improve Panfrost's CI
coverage, what we need right now is not trace-based testing, it's
GLES3.1 conformance runs on MediaTek MT8192 or MT8195. That hardware is
already in the Collabora LAVA lab, but it's not being used for Mesa CI
as the required kernel patches haven't made their way to mainline yet
and nobody has cherry-picked them to the gfx-ci kernel. If you are a
Collaboran and interested in improving Panfrost CI, please ping
AngeloGioacchino for information on which specific patches need to be
backported or cherry-picked to our gfx-ci kernel. Thank you.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19358>
Rob Clark [Fri, 28 Oct 2022 17:22:27 +0000 (10:22 -0700)]
nir: Add way to create passthrough TCS without VS nir
In the case of disk-cache hits, radeonsi no longer has the nir shader
around. So add a way to create a passthrough TCS with just the VS
output locations.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7567
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19382>
Rob Clark [Fri, 28 Oct 2022 20:59:10 +0000 (13:59 -0700)]
docs: Update features.txt
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19388>
Alyssa Rosenzweig [Thu, 9 Jun 2022 13:45:37 +0000 (09:45 -0400)]
gallium: Only use Asahi's software path on macOS
On macOS, we don't have DRM or any real WSI, so Asahi has to pretend to be a
software rasterizer to load. On Linux, we do have DRM and proper WSI, so we
don't want that. For faking Asahi devices on Linux, we should use drm-shim
instead. This makes sure we don't accidentally load Asahi on non-M1 Linux.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15940>
Alyssa Rosenzweig [Thu, 9 Jun 2022 12:50:44 +0000 (08:50 -0400)]
gallium: Stub support for Asahi + DRM
Copy-paste a pile of winsys code from panfrost and find-and-replace the name to
asahi. This should contain all the glue code needed for asahi+kmsro.
The kernel driver is under way (led by Asahi Lina, not me), but it's not
wred up here. My goal was rather to run shader-db, which expects a
render node, which means drm-shim, which means DRM loader support. With
this patch and a trivial drm-shim, shader-db runs.
In general I am reticent to touch UABI related code when the UABI hasn't been
finalized upstream, or started design at all, hence the RFC. Realistically this
patch assumes the following about the future UABI:
0. It will be a DRM driver. This is nonnegotiable.
1. The render node will be named "asahi". The other reasonable name would be
"apple", which I'm using for the display controller (not yet upstream, but
getting close).
2. Display and rendering will be split in the kernel, requiring kmsro in
userspace, as agreed in past discussions.
The 3D accelerator (AGX) and the display controller (DCP) are completely
orthogonal blocks with separate lineages. True, Apple A14 (~= M1) has AGX and
DCP together, and it seems like all the chips that will get upstream support
will have this for the forseeable future. Nevertheless, it's a historical
coincidence. Apple A12 had an AGX block with a pre-DCP Apple display
controller, which would use a completely different display driver. Older SoCs
had a PowerVR block with an Apple shader core, with a pre-DCP Apple display
controller. Even older SoCs had a pure PowerVR block (+ Apple display).
The AGX and DCP kernel drivers are not expected to share any nontrivial code.
We don't gain anything by bundling them together. Likewise, the many
codec blocks are completely orthogonal. This is all standard practice
for Arm SoCs.
It is true that AGX has never been used with a non-Apple display
controller; it is highly unlikely this would change (either by AGX
licensing out or something like Mali-DP getting licensed in). But
an extra kmsro user doesn't actually add more complexity to Mesa, so
shrug.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com> [meson, ack on gallium]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15940>
Gert Wollny [Wed, 26 Oct 2022 20:13:31 +0000 (22:13 +0200)]
r600/sfn: Add .clang-format file and apply style
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19379>
Karol Herbst [Fri, 28 Oct 2022 11:55:17 +0000 (13:55 +0200)]
nir/algebraic: add vec8/16 cmp lowering
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19150>
Karol Herbst [Fri, 28 Oct 2022 11:38:56 +0000 (13:38 +0200)]
nir/algebraic: generalize vector_cmp lowering
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19150>
Karol Herbst [Mon, 17 Oct 2022 23:18:04 +0000 (01:18 +0200)]
nir/algebraic: support CL vector accessors
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19150>
Karol Herbst [Sun, 25 Sep 2022 14:42:15 +0000 (16:42 +0200)]
nir/algebraic: add 8 and 64 bit urol and uror lowering
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19150>
Alyssa Rosenzweig [Thu, 27 Oct 2022 15:23:53 +0000 (11:23 -0400)]
panfrost,asahi: Support ARB_buffer_storage
After a great deal of spec lawyering in #dri-devel, I am convinced this
is probably okay for the same reasons as v3d and freedreno. The batch
reordering and flush deferral optimizations are seemingly still ok. The
requirement that writes are visible "immediately" in the spec actually
means "in the subsequent [OpenGL] command" for the CPU -> GPU direction,
which avoids pitfalls where PERSISTENT|COHERENT could be used as a
"doorbell". With that understanding, the extension doesn't actually
require anything special for tilers other than coherency at GPU submit
boundaries, which is true for any driver that does not use a sync ioctl.
After this commit, the remaining drivers that don't set the CAP are
d3d12, softpipe, etnaviv, and i915g. I am unsure about d3d12, but the
latter 3 could probbaly enable it trivially for the same reason.
v2: Don't use copy_resource path for persistent mappings (Emma). Emma
explained on GitLab:
I don't think you should have the copy_resource path taken for
PIPE_RESOURCE_FLAG_MAP_PERSISTENT BOs. Imagine the user has a
general-purpose BO they're streaming stuff into and doing draws that
they keep persistently mapped until wrapping. They call some GL
function on the same buffer that does a fallback write map on the BO
(u_default_buffer_subdata, util_resource_copy_region, whatever) -- the
buffer is in use, copy triggers, allocates a new BO. Whoops, the user's
pointer for streaming writes is now freed.
Closes: #7570
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19351>
Yusuf Khan [Thu, 27 Oct 2022 06:31:02 +0000 (01:31 -0500)]
gallium/util: add a helper for get_timestamp
Signed-off-by: Yusuf Khan <yusisamerican@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19334>
Rhys Perry [Thu, 27 Oct 2022 11:49:09 +0000 (12:49 +0100)]
aco: insert waitcnt before/after ds_ordered_count
The LLVM backend does this when lowering ordered_xfb_counter_add_amd. I
guess there is some missing dependency checking or something.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19345>
Rhys Perry [Thu, 27 Oct 2022 13:49:31 +0000 (14:49 +0100)]
aco: add storage_gds
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19345>
Emma Anholt [Mon, 17 Oct 2022 21:39:44 +0000 (14:39 -0700)]
zink: Lazily allocate the dummy surfaces.
glmark2 -b texture --fullscreen drops from 141MB of BOs to 85MB on turnip.
Still 29MB more than freedreno (due to a pile of extra fullscreen rgba8
images)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19126>
Emma Anholt [Mon, 17 Oct 2022 22:00:11 +0000 (15:00 -0700)]
zink: No need to use a 2-sample dummy image for bindless without null descs.
This appears to be some leftover copy and paste or something, should be
1-sample just like other dummy usages.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19126>
José Roberto de Souza [Mon, 24 Oct 2022 20:53:34 +0000 (13:53 -0700)]
iris: Do not export iris_bo_wait()
It has a single user, so no need to export it.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19359>
José Roberto de Souza [Mon, 24 Oct 2022 21:11:26 +0000 (14:11 -0700)]
iris: Drop duplicated errno handling in iris_bo_wait()
Both code paths already do this handling, so no need to this again in
iris_bo_wait().
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19359>
José Roberto de Souza [Tue, 11 Oct 2022 19:14:35 +0000 (12:14 -0700)]
iris: Nuke pci_id from iris_screen
We have the same information in devinfo.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19359>
José Roberto de Souza [Tue, 25 Oct 2022 16:50:01 +0000 (09:50 -0700)]
intel/perf: Use intel_device_info functions to compute subslice and eu totals
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19359>
Giancarlo Devich [Mon, 17 Oct 2022 20:24:14 +0000 (13:24 -0700)]
d3d12: Don't align already-aligned size in `d3d12_bufmgr_create_buffer`
This is handled by `pb_cache_manager_create_buffer`.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19082>
Giancarlo Devich [Mon, 17 Oct 2022 20:17:19 +0000 (13:17 -0700)]
gallium/pipe: Align allocation size in `pb_cache_manager_create_buffer`
Some drivers have minimum buffer size or alignment requirements. When a
buffer is created using pb_cache_manager_create_buffer, the cache is
first checked for a compatible buffer to return instead. If the
requested buffer size is less than
(minimum buffer size) / (mgr->size_factor), no buffer in the cache
is _ever_ applicable.
The alignment is used to determine the true allocation size when
evaluating against cached buffers.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19082>
Rob Clark [Mon, 24 Oct 2022 16:33:39 +0000 (09:33 -0700)]
freedreno/ci: Small bit of xfails cleanup
Minor resorting to group similar edgeflags fails together.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>
Rob Clark [Sun, 23 Oct 2022 16:05:52 +0000 (09:05 -0700)]
freedreno: Enable GL_ARB_enhanced_layouts
Seems like ir3 already supports everything that was needed, according to
piglit.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>
Rob Clark [Fri, 21 Oct 2022 21:30:33 +0000 (14:30 -0700)]
freedreno/a6xx: Enable GL_ARB_texture_mirror_clamp_to_edge
It was already supported, might as well turn it on.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>
Rob Clark [Sun, 16 Oct 2022 20:48:51 +0000 (13:48 -0700)]
freedreno/a6xx: Support GL_ARB_viewport_array + gl43
Support multiple viewports and bump supported GLSL version now that we
tick all the boxes.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>
Rob Clark [Sun, 16 Oct 2022 20:35:14 +0000 (13:35 -0700)]
freedreno: Move guardband calc to bind time
No point in re-calculating this at emit time. Even more so when there
are multiple viewports.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>
Rob Clark [Fri, 21 Oct 2022 00:49:27 +0000 (17:49 -0700)]
freedreno: Massage scissor state at bind time
All the generations want maxx/maxy to be inclusive rather than
exclusive, so shift the subtract-one nonsense to bind time rather
than emit time.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>
Rob Clark [Sun, 16 Oct 2022 19:20:01 +0000 (12:20 -0700)]
freedreno: support multiple viewports
Core plumbing to have multiple viewport support. Each viewport has it's
own scissor state.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>
Rob Clark [Fri, 28 Oct 2022 16:12:13 +0000 (09:12 -0700)]
freedreno/a6xx: Support AMD_vertex_shader_layer
Another thing we already supported but didn't set the cap.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>
Rob Clark [Fri, 21 Oct 2022 16:45:24 +0000 (09:45 -0700)]
freedreno/a6xx: Fix buffer size clamping
Fixes spec@arb_texture_buffer_object@texture-buffer-size-clamp@* which
we start hitting after exposing glsl420
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>
Rob Clark [Fri, 21 Oct 2022 00:49:21 +0000 (17:49 -0700)]
freedreno/ir3: Drop unused view_zero/layer_zero lowering
Previous patch removed the only remaining user.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>
Rob Clark [Fri, 21 Oct 2022 00:49:15 +0000 (17:49 -0700)]
freedreno/a6xx: Move layer_zero handling to interp state
We can just bake this into the program state, rather than making it a
shader variant. Turnip had already switched to this approach so it will
let us drop ir3 lowering for this.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>
Rob Clark [Sun, 23 Oct 2022 18:10:20 +0000 (11:10 -0700)]
freedreno: Don't advertise TGSI support for GS/tess
tgsi_to_nir doesn't support these, and we long ago removed support for
consuming TGSI without tgsi_to_nir. So don't claim to support this.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>
Rob Clark [Wed, 19 Oct 2022 21:55:59 +0000 (14:55 -0700)]
Revert "mesa/st: ARB_vertex_attrib_64bit depend on glsl>=410"
Turns out this change was unnecessary
This reverts commit
533b87dff09a0434cd2c0c22718d117501e17915.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19236>
Samuel Pitoiset [Thu, 27 Oct 2022 14:07:43 +0000 (16:07 +0200)]
ac/nir/ngg: fix emitting streamout output by using packed location
In RadeonSI, they are packed but not in RADV, so don't rely on driver
locations.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19343>
Karol Herbst [Wed, 26 Oct 2022 22:58:47 +0000 (00:58 +0200)]
rusticl/kernel: fix more 32 bit problems
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19353>
Samuel Pitoiset [Fri, 28 Oct 2022 06:35:33 +0000 (08:35 +0200)]
radv: move nir_opt_idiv_const/nir_lower_idiv after NGG lowering
NGG streamout lowering creates some idiv instructions that need to be
lowered.
No fossil-db results because it's currently broken.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19364>
Samuel Pitoiset [Fri, 28 Oct 2022 02:47:50 +0000 (02:47 +0000)]
radv/llvm: fix dual source blending on GFX11
Untested but this should be similar to RadeonSI.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19367>
Samuel Pitoiset [Fri, 28 Oct 2022 13:10:07 +0000 (15:10 +0200)]
radv: fix VRS limit when attachmentFragmentShadingRate is disabled
Can be reproduced on GFX10.3 with RADV_DEBUG=nohiz.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19374>
Mike Blumenkrantz [Fri, 28 Oct 2022 13:45:42 +0000 (09:45 -0400)]
zink: don't double-deref bindless texture arrays in shaders
these are already dereferenced
Fixes:
b2fcb34e976 ("zink: rework sampler emission")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19377>
José Roberto de Souza [Thu, 27 Oct 2022 16:42:22 +0000 (09:42 -0700)]
iris: Fix enablement of protected contexts
I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS needs to set otherwise
i915 will ignore the extensions.
Fixes:
57a1d13279c6 ("iris: enable protected contexts")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19373>
Iago Toral Quiroga [Fri, 28 Oct 2022 09:05:39 +0000 (11:05 +0200)]
v3dv: split event implementation to a separate file
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19366>
Iago Toral Quiroga [Fri, 28 Oct 2022 10:10:17 +0000 (12:10 +0200)]
v3dv: return out of host memory if we fail to create event pipelines
Fixes:
ecb01d53fd ('v3dv: refactor events')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19366>
Frank Binns [Tue, 18 Oct 2022 11:12:55 +0000 (12:12 +0100)]
pvr: remove implicit sync support
This is the legacy way of doing synchronisation and is no longer necessary now
that the DMA_BUF_IOCTL_EXPORT_SYNC_FILE / DMA_BUF_IOCTL_IMPORT_SYNC_FILE ioctls
exist, which the wsi code is already making use of.
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19293>
Mykhailo Skorokhodov [Thu, 20 Oct 2022 14:51:39 +0000 (17:51 +0300)]
drirc: Apply fp64_workaround_enabled to DOOM Eternal
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6847
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18854>
Mykhailo Skorokhodov [Thu, 20 Oct 2022 14:49:34 +0000 (17:49 +0300)]
drirc: Add fp64_workaround_enabled option
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18854>
Mykhailo Skorokhodov [Wed, 28 Sep 2022 02:12:19 +0000 (05:12 +0300)]
anv: Add softtp64 workaround
Pass float64.glsl into nir_lower_doubles() resolves the problem on
ICL/TGL when the shader uses float64, but the device doesn't support
that type.
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18854>
Mykhailo Skorokhodov [Thu, 27 Oct 2022 17:38:52 +0000 (20:38 +0300)]
anv/meson: Add float64_spv_h custom target
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18854>
Mykhailo Skorokhodov [Wed, 19 Oct 2022 20:00:17 +0000 (23:00 +0300)]
glsl/meson: Add variable to export float64.glsl
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18854>
Mykhailo Skorokhodov [Tue, 4 Oct 2022 02:47:01 +0000 (05:47 +0300)]
nir: Add assert in nir_lower_doubles
Cc: mesa-stable
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18854>
Mykhailo Skorokhodov [Wed, 19 Oct 2022 20:25:25 +0000 (23:25 +0300)]
nir: Make lower_double_ops recognize SPIR-V mangling
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18854>
Mykhailo Skorokhodov [Mon, 17 Oct 2022 14:39:03 +0000 (17:39 +0300)]
util: Add glsl2spirv.py script
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18854>
Nanley Chery [Wed, 26 Oct 2022 15:12:52 +0000 (08:12 -0700)]
iris: Enable INTEL_MEASURE for compute dispatches on XeHP
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19324>
Lucas Stach [Thu, 27 Oct 2022 10:55:13 +0000 (12:55 +0200)]
etnaviv: blt: try to find exact format match first
For MSAA downsampling to work correctly, the BLT engine needs to know
the exact format of the blit source/target. The compatible formats are
fine as long as the BLT is only used as a tiler without doing any
conversion.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19349>
Lucas Stach [Thu, 27 Oct 2022 08:14:43 +0000 (10:14 +0200)]
etnaviv: blt: scale operations by MSAA mode
Same as with the RS engine, BLT operations need to be scaled by
the MSAA size.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19349>
Samuel Pitoiset [Wed, 26 Oct 2022 15:59:31 +0000 (17:59 +0200)]
radv: fix suspending/resuming pipeline statistics queries with GDS
This probably doesn't fix anything in practice because GDS is only
used for the number of generated primitives by GS and meta operations
don't use GS.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19348>
Samuel Pitoiset [Thu, 27 Oct 2022 14:07:43 +0000 (16:07 +0200)]
ac/nir/ngg: fix emitting streamout output by using packed location
In RadeonSI, they are packed but not in RADV, so don't rely on driver
locations.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19365>
Lionel Landwerlin [Thu, 27 Oct 2022 09:03:35 +0000 (12:03 +0300)]
intel/compiler: don't allocate compaction arrays on the stack
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7569
Cc: mesa-stable
Reviewed-by: Luis Felipe Strano Moraes <luis.strano@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19339>
Iago Toral Quiroga [Wed, 26 Oct 2022 09:13:48 +0000 (11:13 +0200)]
v3dv: re-enable sync_fd import/export
Now that we implement GPU-side event functions in the GPU we
no longer have the issue that didn't allow us to expose
sync_fd.
Further more, new spec text has also made the problematic
behavior undefined, so the test that caused this issue,
dEQP-VK.api.external.semaphore.sync_fd.import_twice_temporary,
is incorrect and should be fixed.
It should be noted that we still keep sync_fd disabled in the
simulator, at least until the CTS tests are fixed, since the
synchronous execution model of the simulator means that in the
problematic scenario we can block the CPU on the execution
of the command buffer before we ever submit the signaling job,
still causing a deadlock.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19313>
Iago Toral Quiroga [Wed, 19 Oct 2022 07:48:19 +0000 (09:48 +0200)]
v3dv: refactor events
This replaces our current implementation, which is 100% CPU based,
with an implementation that uses compute shaders for the GPU-side
event functions. The benefit of this solution is that we no longer
need to stall on the CPU when we need to handle GPU-side event
commands.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19313>
Iago Toral Quiroga [Wed, 26 Oct 2022 07:01:59 +0000 (09:01 +0200)]
broadcom/compiler: handle vec2 load/store index
In vulkan, we load descriptors via vulkan resource index, which
returns a vec2, of which we want component 0 which holds the actual
index. Typically, this will be cleaned-up by the time we get to
emitting VIR so the index is a single scalar component, but there
are some cases where this might no be the case, so make sure we don't
assume it to be a scalar, like we do in other places.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19313>
Brian Paul [Mon, 17 Oct 2022 19:21:16 +0000 (13:21 -0600)]
llvmpipe: check rectangle vertices have equal W components
The attribute interpolation code does not handle perspective
correction. But it's OK if the vertex W components are non-one as
long as they're equal.
This fixes about 30 CTS/dEQP tests.
Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19331>
Matt Turner [Thu, 27 Oct 2022 17:07:02 +0000 (13:07 -0400)]
intel/dev: Set display_ver = 13 on all ADL/RPL/DG2
display_ver doesn't seem to be used anywhere, but if that were to
change, we'd want this to be consistent.
Fixes:
c746bf4c5c8 ("intel/dev: Add display_ver and set adl-p to 13")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19354>
Karol Herbst [Fri, 28 Oct 2022 00:05:21 +0000 (02:05 +0200)]
zink: remove leftover work_dim lowering code
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19362>
Karol Herbst [Thu, 27 Oct 2022 23:45:46 +0000 (01:45 +0200)]
rusticl/kernel: add work_dim lowering
No driver implements this in hardware, so let's implement it once in the
frontend.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19362>
Karol Herbst [Thu, 27 Oct 2022 23:44:45 +0000 (01:44 +0200)]
rusticl/kernel: lower system values before gathering info
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19362>
Karol Herbst [Thu, 27 Oct 2022 23:45:34 +0000 (01:45 +0200)]
rusticl/nir: add reads_sysval wrapper
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19362>
Karol Herbst [Thu, 27 Oct 2022 23:28:12 +0000 (01:28 +0200)]
rusticl: add small bitset impl
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19362>
Mike Blumenkrantz [Wed, 19 Oct 2022 10:47:16 +0000 (06:47 -0400)]
zink: always add MUTABLE with EXTENDED_USAGE for image creation
this otherwise makes little sense
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19018>
Mike Blumenkrantz [Mon, 10 Oct 2022 11:58:13 +0000 (07:58 -0400)]
zink: don't force attachment usage for images when unsupported
this is illegal even with EXTENDED_USAGE, but it will also probably
explode later when trying to populate the image
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19018>
Mike Blumenkrantz [Mon, 10 Oct 2022 11:48:59 +0000 (07:48 -0400)]
zink: fix weird formatting
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19018>
Jesse Natalie [Thu, 27 Oct 2022 22:55:58 +0000 (15:55 -0700)]
d3d12: Set PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19357>
Jesse Natalie [Thu, 27 Oct 2022 19:49:04 +0000 (12:49 -0700)]
d3d12: Don't multiply cube array sizes by 6
Gallium already does this for us.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19357>
Jesse Natalie [Thu, 27 Oct 2022 19:47:24 +0000 (12:47 -0700)]
d3d12: Don't put permanently-resident resources in the residency bo list
If the permanently-resident resources are never used, such as a swapchain
buffer in a purely offscreen renderer, it can cause the residency algorithm
to fail, when the permanently-resident resource is least-recently-used,
so we try to wait for it to be idle and evict it, but it never gets evicted.
This triggers an infinite loop.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19357>
Mike Blumenkrantz [Wed, 26 Oct 2022 18:18:57 +0000 (14:18 -0400)]
zink: rip out unused kernel push constant
this was for supporting clover, but I don't care anymore
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Mike Blumenkrantz [Tue, 18 Oct 2022 15:45:16 +0000 (11:45 -0400)]
zink: add handling for CL-style discrete shader samplers
this splits the bindings for sampler desc sets in CL like
* 32 samplers
* 128 samplerviews
* (compacted only) shader images
and then handles recombination during texop emission
it does NOT change the descriptor limits, which are still clamped to 32
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Mike Blumenkrantz [Tue, 18 Oct 2022 15:42:45 +0000 (11:42 -0400)]
zink: add handling on the vk side for discrete sampler descriptors
just the descriptor layout/set management
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Mike Blumenkrantz [Tue, 18 Oct 2022 15:42:04 +0000 (11:42 -0400)]
zink: always take the compact descriptor size path with kernel shaders
this guarantees compaction of the size arrays
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Mike Blumenkrantz [Tue, 18 Oct 2022 15:38:18 +0000 (11:38 -0400)]
zink: emit explicit samplers in ntv based on sampler_mask
not actually used yet
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Mike Blumenkrantz [Tue, 18 Oct 2022 15:36:10 +0000 (11:36 -0400)]
zink: add some spirv builder handling for sampled image ops
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Mike Blumenkrantz [Mon, 17 Oct 2022 16:18:08 +0000 (12:18 -0400)]
zink: simplify image deref handling
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Mike Blumenkrantz [Mon, 17 Oct 2022 17:22:25 +0000 (13:22 -0400)]
zink: add a nir pass for CL image typing and sampler tracking
cl images and samplers come through untyped, so they need to be typed
before they can be used
samplers are also not combined into the descriptor, so track a mask which
can be used later for emission
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Mike Blumenkrantz [Mon, 17 Oct 2022 15:07:34 +0000 (11:07 -0400)]
zink: pass image type to image emission
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Mike Blumenkrantz [Mon, 17 Oct 2022 15:00:37 +0000 (11:00 -0400)]
zink: rework sampler emission
this simplifies all the different sampler metadata tracking fields to be
more comprehensible
it also increases some array sizes in case future work increases them outside
the compiler areas
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Mike Blumenkrantz [Mon, 17 Oct 2022 14:11:08 +0000 (10:11 -0400)]
zink: pass KERNEL shaders through successfully
basically just merging with COMPUTE cases
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Mike Blumenkrantz [Mon, 17 Oct 2022 14:10:53 +0000 (10:10 -0400)]
zink: match bitsizes in bo rewriting
technically this matters
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19327>
Lionel Landwerlin [Thu, 15 Sep 2022 19:10:46 +0000 (22:10 +0300)]
intel/fs: use fs implementation of dump_instructions
This specialized version prints out the liveness count as well as the
maximum liveness count. It was eye opening when seeing the max
liveness jump after lowering of packing instructions which should not
have changed the count.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18657>
Lionel Landwerlin [Tue, 13 Sep 2022 23:40:01 +0000 (02:40 +0300)]
intel/fs: reduce liveness of variables in lowering passes
When lowering a single instruction with a destination VGRF to 2 or
more, the VGRF is now considered partially written by each generated
instruction and that increases its liveness especially in loops. Thus
potentially increasing the number of spills/fills due to register
allocation.
Putting an UNDEF instruction in front of the lowered instructions
allows the IR to limit the liveness of the VGRF, reducing register
pressure.
This has a pretty dramatic effect on spills/fills for RT shaders. Here
the stats on Q2RTX shaders on DG2 (wipping out any spills/fills due to
register allocation) :
Instructions in all programs: 26150 -> 24955 (-4.6%)
SENDs in all programs: 1148 -> 1148 (+0.0%)
Loops in all programs: 4 -> 4 (+0.0%)
Cycles in all programs: 392179 -> 332787 (-15.1%)
Spills in all programs: 132 -> 116 (-12.1%)
Fills in all programs: 262 -> 154 (-41.2%)
Shader-db results on TGL :
total instructions in shared programs:
21158140 ->
21158377 (<.01%)
instructions in affected programs: 76629 -> 76866 (0.31%)
helped: 18
HURT: 20
helped stats (abs) min: 1 max: 60 x̄: 18.89 x̃: 12
helped stats (rel) min: 0.21% max: 3.61% x̄: 1.02% x̃: 0.77%
HURT stats (abs) min: 1 max: 79 x̄: 28.85 x̃: 18
HURT stats (rel) min: 0.04% max: 2.81% x̄: 1.13% x̃: 0.79%
95% mean confidence interval for instructions value: -4.82 17.30
95% mean confidence interval for instructions %-change: -0.34% 0.57%
Inconclusive result (value mean confidence interval includes 0).
total loops in shared programs: 5753 -> 5753 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0
total cycles in shared programs:
798856834 ->
798870688 (<.01%)
cycles in affected programs: 6208395 -> 6222249 (0.22%)
helped: 22
HURT: 17
helped stats (abs) min: 2 max: 8794 x̄: 1438.18 x̃: 782
helped stats (rel) min: 0.05% max: 2.28% x̄: 0.63% x̃: 0.44%
HURT stats (abs) min: 2 max: 19178 x̄: 2676.12 x̃: 1358
HURT stats (rel) min: 0.04% max: 23.49% x̄: 2.25% x̃: 0.71%
95% mean confidence interval for cycles value: -952.19 1662.65
95% mean confidence interval for cycles %-change: -0.64% 1.90%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 4078 -> 4066 (-0.29%)
spills in affected programs: 40 -> 28 (-30.00%)
helped: 2
HURT: 0
total fills in shared programs: 2856 -> 2832 (-0.84%)
fills in affected programs: 127 -> 103 (-18.90%)
helped: 2
HURT: 0
total sends in shared programs: 998554 -> 998554 (0.00%)
sends in affected programs: 0 -> 0
helped: 0
HURT: 0
LOST: 0
GAINED: 0
Total CPU time (seconds): 2346.06 -> 2304.80 (-1.76%)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18657>
Lionel Landwerlin [Fri, 16 Sep 2022 20:35:08 +0000 (23:35 +0300)]
intel/fs: make split_virtual_grfs deal with partial undefs
v2: fix up UNDEFs instructions (Curro)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18657>
Lionel Landwerlin [Thu, 22 Sep 2022 07:14:28 +0000 (10:14 +0300)]
intel/fs: require UNDEFs register offsets to be aligned to REG_SIZE
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18657>
Emma Anholt [Wed, 21 Sep 2022 19:49:07 +0000 (12:49 -0700)]
turnip: Fix reservation for indirect compute's IR3_DP_SUBGROUP_ID_SHIFT.
Fixes an assert in GravityMark.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19203>
Alyssa Rosenzweig [Fri, 21 Oct 2022 20:46:21 +0000 (16:46 -0400)]
pan/mdg: Don't schedule across memory barrier
Fixes KHR-GLES31.core.shader_image_load_store.basic-glsl-misc-cs
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
Alyssa Rosenzweig [Fri, 21 Oct 2022 20:38:38 +0000 (16:38 -0400)]
panfrost: Lower MAX_BLOCK_SIZE on Midgard
To match PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK, having it be higher in any
dimension is nonsensical and can confuse apps. Fixes tests in
KHR-GLES31.core.texture_buffer.* on Mali-T860.
Fixes:
9b19104a30b ("pan/mdg: Lower PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK on Midgard")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
Alyssa Rosenzweig [Fri, 21 Oct 2022 19:36:03 +0000 (15:36 -0400)]
panfrost: Avoid a XFB special case
This worked around an issue that doesn't apply to the Valhall XFB lowering.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
Alyssa Rosenzweig [Fri, 21 Oct 2022 16:28:35 +0000 (12:28 -0400)]
panfrost: Use compute-based XFB on Midgard
Now we're back to a single XFB implementation for all gens. Fixes:
KHR-GLES31.core.draw_indirect.advanced-twoPasses-transformFeedback-arrays
KHR-GLES31.core.draw_indirect.advanced-twoPasses-transformFeedback-elements
Cc: mesa-stable
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>
Alyssa Rosenzweig [Fri, 21 Oct 2022 19:34:52 +0000 (15:34 -0400)]
pan/mdg: Fix 64-bit address arithmetic
Cc: mesa-stable
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19238>